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Miller" , Ashish Kalra , Joerg Roedel , "Suravee Suthikulpanit" , Will Deacon , Robin Murphy , Dan Williams , Bjorn Helgaas , Eric Biggers , Brijesh Singh , Gary R Hook , "Borislav Petkov (AMD)" , Kim Phillips , Vasant Hegde , Jason Gunthorpe , "Michael Roth" , Jonathan Cameron , Xu Yilun , Gao Shiyuan , "Sean Christopherson" , Nikunj A Dadhania , Dionna Glaze , , , Alexey Kardashevskiy Subject: [PATCH kernel 1/6] PCI/TSM: Add secure SPDM DOE mailbox Date: Tue, 11 Nov 2025 17:38:13 +1100 Message-ID: <20251111063819.4098701-2-aik@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251111063819.4098701-1-aik@amd.com> References: <20251111063819.4098701-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD74:EE_|PH7PR12MB7986:EE_ X-MS-Office365-Filtering-Correlation-Id: c6071811-be8d-4074-85ec-08de20ed05f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?agpUSwKQnRiveYg42rWCmQp/jGW9I53U+U32fZDUQoMcOrTwyY8lxFxaeJdz?= =?us-ascii?Q?Knt9q8894mrHeasapALez7/Oo5rKLbw/1s+szYmTEW7Glp4CvI8fNPrSbQeo?= =?us-ascii?Q?6ACcw0szwjO/Gmq4SObXD7ksv3v/a9Yiik2xdAo9QfNwRNz8NqAfXqNfYNLB?= =?us-ascii?Q?lm+BD5BeUTknpBloLJmiwNV73BpJzleFKgfBN1G5YKpm9PjYbRxezqcnjygY?= =?us-ascii?Q?+FGF2RCnsDnY3kHthbnnNOlJTZd/rAKCmx5tHdWEF27DDt8aQcaqQ8zo8uTC?= =?us-ascii?Q?a2DxMMFjBYQcJbeN8elSdrY8L5FBeJWyDSRKelSpJiw0t6BBR6EDDSUgn3Qh?= =?us-ascii?Q?omHNBRYRe4KCLb/376QK9sgg5FTujz83vyBwo/HuooGJPaRaxDLP4e3lPRMG?= =?us-ascii?Q?v2YkwI1uIRhQE5WGQ11r8K3j/Klzpe8maqqTzFRQP6vPznVhQ43m2JrM3Rus?= =?us-ascii?Q?NqUS1lBYl1vlteqTtJ+OmlIu7N3P91FzlCT+rmPf3+g1RNiQuhWn+OctIxx6?= =?us-ascii?Q?fpvKsA5pcMwU9+ymq+tuTqp+fP4y5iNCPPrOjmKzmfTMk5R45NqT9cF4eLH1?= =?us-ascii?Q?KWPjnNEtKuoWkziDvQYziJKIjBgtG9sg2zrkxIdDbrKZzGtmM1dVyw2Kr2gr?= =?us-ascii?Q?7uzBFxdheQ4UbqMRZGWO4jwcd8fct2QzhRffRp/AyNd9wz0v/8XwR9R1CfKq?= =?us-ascii?Q?zD7ustyCHxKOUxuYF4BLq/Ij8ARiFBP87Rel3EGPkKXVu/dbGm0dSY/Qx1rm?= =?us-ascii?Q?y4j9RG3kpqOj+OpNLA6zOno2ofg27jPoQIxTDxrDUOecXUgbPdYKD0orkcCm?= =?us-ascii?Q?ECc46A8IKtdekbWn7kItxp5V9qfN4duk1LFHHLkl1ROYReCJO8w9wf6aBUz4?= =?us-ascii?Q?MIiysCCRK8AnKh9kPMswAL347aTJ8FC4S5zjL1GjPj4/Pc7nfyadHXuWejRY?= =?us-ascii?Q?JqXQ7Y9CzsQw/xsBdtBxGFT28WO5cOnNjhQeCwyzQ5CjpWMJGCjDIodLnoGw?= =?us-ascii?Q?ioPQF3rkjkqj1jIQ/1i8d514nnINQSZ/Q0TuCDiMZX2WCPl59RJ/Snf72DO/?= =?us-ascii?Q?q33eIWyAbFYgB4M20OE2TGRb81F7iV0ONpgfKkZnTDR5OFiVw/JT1D0N0wA9?= =?us-ascii?Q?YjHWIGgYP6QoEYbIJMiR761sLopKG09to3EARsOOx/UuE/zqqm7IyCh4wEuo?= =?us-ascii?Q?qyjEmiZ3cZL9ztVBD546TGqBSfxHY1sA1Xapi1dAK9b2Ve9comjHYsMu0YxB?= =?us-ascii?Q?1lqXB7DEEPm0CseA0bmL/xBd9zHwZ2I/1jV1m752Q/yc098NEEEX5N9//i22?= =?us-ascii?Q?ZZ675z5y0NpJshZlygl5IEgduI/CrufFD95apO5gN+Wm5JHsZLuZqTgaK8SI?= =?us-ascii?Q?+/wi3ixkUx1FLSBYA7vepWTB7OWIi5wBNH5FgsMxu1QIXtrqBgPvwoGJdAWg?= =?us-ascii?Q?YfQS7X091PGCrBiuljiLrqIQwIH8Cg/+oJzIpovEaxT5M8I8tjLwkLIZnIEK?= =?us-ascii?Q?/W6b/9/TqTEBqBlrf1QSAeaK9UXsXrmVppVyN6Thk9Bg8aGzmmlw158ySi6a?= =?us-ascii?Q?HO70C9G24UKcrJrLMOk=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 06:39:11.2244 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6071811-be8d-4074-85ec-08de20ed05f9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7986 Content-Type: text/plain; charset="utf-8" The IDE key programming happens via Secure SPDM channel, initialise it at the PF0 probing. Add the SPDM certificate slot (up to 8 are allowed by SPDM), the platform is expected to select one. While at this, add a common struct for SPDM request/response as these are going to needed by every platform. Signed-off-by: Alexey Kardashevskiy --- (!tsm->doe_mb_sec) is definitely an error on AMD SEV-TIO, is not it on othe= r platforms? --- include/linux/pci-tsm.h | 14 ++++++++++++++ drivers/pci/tsm.c | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/include/linux/pci-tsm.h b/include/linux/pci-tsm.h index 40c5e4c31a3f..b6866f7c14b4 100644 --- a/include/linux/pci-tsm.h +++ b/include/linux/pci-tsm.h @@ -10,6 +10,14 @@ struct tsm_dev; struct kvm; enum pci_tsm_req_scope; =20 +/* SPDM control structure for DOE */ +struct tsm_spdm { + unsigned long req_len; + void *req; + unsigned long rsp_len; + void *rsp; +}; + /* * struct pci_tsm_ops - manage confidential links and security state * @link_ops: Coordinate PCIe SPDM and IDE establishment via a platform TS= M. @@ -130,11 +138,17 @@ struct pci_tsm { * @base_tsm: generic core "tsm" context * @lock: mutual exclustion for pci_tsm_ops invocation * @doe_mb: PCIe Data Object Exchange mailbox + * @doe_mb_sec: DOE mailbox used when secured SPDM is requested + * @spdm: cached SPDM request/response buffers for the link + * @cert_slot: SPDM certificate slot */ struct pci_tsm_pf0 { struct pci_tsm base_tsm; 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Mon, 10 Nov 2025 22:39:25 -0800 From: Alexey Kardashevskiy To: CC: , , Tom Lendacky , John Allen , Herbert Xu , "David S. Miller" , Ashish Kalra , Joerg Roedel , "Suravee Suthikulpanit" , Will Deacon , Robin Murphy , Dan Williams , Bjorn Helgaas , Eric Biggers , Brijesh Singh , Gary R Hook , "Borislav Petkov (AMD)" , Kim Phillips , Vasant Hegde , Jason Gunthorpe , "Michael Roth" , Jonathan Cameron , Xu Yilun , Gao Shiyuan , "Sean Christopherson" , Nikunj A Dadhania , Dionna Glaze , , , Alexey Kardashevskiy Subject: [PATCH kernel 2/6] ccp: Make snp_reclaim_pages and __sev_do_cmd_locked public Date: Tue, 11 Nov 2025 17:38:14 +1100 Message-ID: <20251111063819.4098701-3-aik@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251111063819.4098701-1-aik@amd.com> References: <20251111063819.4098701-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7A:EE_|CH3PR12MB9456:EE_ X-MS-Office365-Filtering-Correlation-Id: fc448f57-83c3-40be-81e6-08de20ed1519 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QIEwzHDZILcdTwNqe2ogTJircpE0FtMWnnmEYzlFIUxk8G5KA6u/4ZDInIBo?= =?us-ascii?Q?1+4a2bxzwcA7oJWrbY/H6R3GlpLdQpwcWs+qRDkzkkul62Xas3qHW/FvS1GI?= =?us-ascii?Q?kLQ0v6u7978JulZekGJK/aBnrDPHF8zGT/k6hODVR7NVGhGxZ8l4+Ck6I7n2?= =?us-ascii?Q?9X7IWwx/gP6UY5rzXjauDRXaw87pJ09fyYP+ZChP9+EkqkduE+aXUNPQI8Sw?= =?us-ascii?Q?8ZcfqFpELoRC9szhD0Iq5YGkBYg6vlHCTJIJ2exLG6qZlrYCWFLAIya2SwOl?= =?us-ascii?Q?l53qTWblzV033PepRlSnWnxiC/fZFg92IUm3KVyMlYK6cJ+rV1Xa9Nqm1Elb?= =?us-ascii?Q?KeHcNK0PMplamknTAzAnG/y8YtCGFDYs9b3nzm+5oT3kuLRl9xhP3rOlLE0N?= =?us-ascii?Q?vq2pdqmKLjAjz1phFAu097FZGOdEBLnzGPqJRShzYe0JLJyxkORLgIblweqf?= =?us-ascii?Q?bK+jkoToNYumFxsaLk1SxuYDMkVLnShmi7tbtp4QghHgLHHgtz6r0CM2GBL4?= =?us-ascii?Q?y/GNbLK14GPSAKCYMRcJlgaKmWVv+oxAGHDHONGU+SOxU6KEwiPITxrdw4bl?= =?us-ascii?Q?BcUMqG1cz2yRPB7ApTqJHhpUJYc+xs4CgYrf/D1bOCuip45221CafJTkaLq8?= =?us-ascii?Q?4Hgm1xQI5/+J7JtjkCXIuNjPgoai61IEGdHxV+awDE/vtRZKhDGyUtVBCdwJ?= =?us-ascii?Q?EwqK76tl1T033xUAWNaGsClDY9kDvACP1psHLBuvhMpJc9fVuSkJ7JHUmcVQ?= =?us-ascii?Q?8jYUwo1fUPuGHryWmfXbHWOvze10WQtfBlDy9QMERgg1XQ4TqMX7DQyerT16?= =?us-ascii?Q?lK1NB+lvy5i2PE0KlHUjtyGKqtrarQOHq6iILeTJjoyzfnI5AXUIVbHkqPN7?= =?us-ascii?Q?ld2vc1vgGcfVK3TSk6M7t4I9HzmVa/5sHXiIXvU/gME2rdCz12OwdJlKJ3TO?= =?us-ascii?Q?jVnRwDQBatRgeE+jEitwjOtjA0a3d2oOmc/Sy2xd+r+tkgoU3YZVacOc4Nt/?= =?us-ascii?Q?6AQh2LApHuDNUSKFQF1wtcsTyU+9fWerkxjh8Z9tMZtbS9E7Dpn71Wiho1oX?= =?us-ascii?Q?FX+902XA12tTAROr5anK0AHDinLYWtDR+NhiQBu6mPVJr4uc7t2wB/3JSZn2?= =?us-ascii?Q?PFf9XUPTNcJMdxwkBaYqz6AxgDGxtsJxRkaLY5Mnv6K2WG/PPLx+3C9B/vRX?= =?us-ascii?Q?sNQa/JpiEmrhNmS/OMyUov7z7vnxED3imJsSiYDadV8dWAzUnvTQus8/IDfW?= =?us-ascii?Q?iXFiho7zyY2t0QZaHDzgv6txHIa+Jo62JpT7Scho8N8rfZ7tmF9bbo0r7ja+?= =?us-ascii?Q?fwoJHsaOi6CH/Z6fxEa3sxB1sxTAgHx5Md2RkOf3rmzBMMArfzXqDf8HDgq+?= =?us-ascii?Q?ow7QbwfSaAnUOvZYp/yhA4dOfs97CrNANgnxFlBQE88niS6laV+h2ETTYWtL?= =?us-ascii?Q?iygVAjF964sPP8u51cyTAbitBuJrufGM9/esHubvKAyv7UK9rN4kq3FRH41j?= =?us-ascii?Q?h0mHgJxgbaPFg8NJJff/CFKGcrM7V4nsJFK5vv8fdoiVdAeZc8xABEaBjSi0?= =?us-ascii?Q?rubwhEErGwVRSbgqtXE=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 06:39:36.5988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc448f57-83c3-40be-81e6-08de20ed1519 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9456 Content-Type: text/plain; charset="utf-8" The snp_reclaim_pages() helper reclaims pages in the FW state. SEV-TIO and the TMPM driver (a hardware engine which smashes IOMMU PDEs among other things) will use to reclaim memory when cleaning up. Share and export snp_reclaim_pages(). Most of the SEV-TIO code uses sev_do_cmd() which locks the sev_cmd_mutex and already exported. But the SNP init code (which also sets up SEV-TIO) executes under the sev_cmd_mutex lock so the SEV-TIO code has to use the __sev_do_cmd_locked() helper. This one though does not need to be exported/shared globally as SEV-TIO is a part of the CCP driver still. Share __sev_do_cmd_locked() via the CCP internal header. Signed-off-by: Alexey Kardashevskiy --- drivers/crypto/ccp/sev-dev.h | 1 + include/linux/psp-sev.h | 6 ++++++ drivers/crypto/ccp/sev-dev.c | 11 +++-------- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/crypto/ccp/sev-dev.h b/drivers/crypto/ccp/sev-dev.h index ac03bd0848f7..5cc08661b5b6 100644 --- a/drivers/crypto/ccp/sev-dev.h +++ b/drivers/crypto/ccp/sev-dev.h @@ -71,5 +71,6 @@ void sev_pci_exit(void); =20 struct page *snp_alloc_hv_fixed_pages(unsigned int num_2mb_pages); void snp_free_hv_fixed_pages(struct page *page); +int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret); =20 #endif /* __SEV_DEV_H */ diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index e0dbcb4b4fd9..e3db92e9c687 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -995,6 +995,7 @@ void *snp_alloc_firmware_page(gfp_t mask); void snp_free_firmware_page(void *addr); void sev_platform_shutdown(void); bool sev_is_snp_ciphertext_hiding_supported(void); +int snp_reclaim_pages(unsigned long paddr, unsigned int npages, bool locke= d); =20 #else /* !CONFIG_CRYPTO_DEV_SP_PSP */ =20 @@ -1033,6 +1034,11 @@ static inline void sev_platform_shutdown(void) { } =20 static inline bool sev_is_snp_ciphertext_hiding_supported(void) { return f= alse; } =20 +static inline int snp_reclaim_pages(unsigned long paddr, unsigned int npag= es, bool locked) +{ + return -ENODEV; +} + #endif /* CONFIG_CRYPTO_DEV_SP_PSP */ =20 #endif /* __PSP_SEV_H__ */ diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 0d13d47c164b..9e0c16b36f9c 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -387,13 +387,7 @@ static int sev_write_init_ex_file_if_required(int cmd_= id) return sev_write_init_ex_file(); } =20 -/* - * snp_reclaim_pages() needs __sev_do_cmd_locked(), and __sev_do_cmd_locke= d() - * needs snp_reclaim_pages(), so a forward declaration is needed. - */ -static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret); - -static int snp_reclaim_pages(unsigned long paddr, unsigned int npages, boo= l locked) +int snp_reclaim_pages(unsigned long paddr, unsigned int npages, bool locke= d) { int ret, err, i; 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Mon, 10 Nov 2025 22:39:50 -0800 From: Alexey Kardashevskiy To: CC: , , Tom Lendacky , John Allen , Herbert Xu , "David S. Miller" , Ashish Kalra , Joerg Roedel , "Suravee Suthikulpanit" , Will Deacon , Robin Murphy , Dan Williams , Bjorn Helgaas , Eric Biggers , Brijesh Singh , Gary R Hook , "Borislav Petkov (AMD)" , Kim Phillips , Vasant Hegde , Jason Gunthorpe , "Michael Roth" , Jonathan Cameron , Xu Yilun , Gao Shiyuan , "Sean Christopherson" , Nikunj A Dadhania , Dionna Glaze , , , Alexey Kardashevskiy Subject: [PATCH kernel 3/6] psp-sev: Assign numbers to all status codes and add new Date: Tue, 11 Nov 2025 17:38:15 +1100 Message-ID: <20251111063819.4098701-4-aik@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251111063819.4098701-1-aik@amd.com> References: <20251111063819.4098701-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD77:EE_|PH0PR12MB5647:EE_ X-MS-Office365-Filtering-Correlation-Id: 606af4f7-7f34-45db-d123-08de20ed25cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?i6+5V/e4rl72iVqC3vZUO6p6YrfV3/WOFAYfh1JqT+7H3ramO8ETdDS8dd8R?= =?us-ascii?Q?8TczDfTuT1rlwHAQ1xOGJaZJQ9KAIm+eUKPtPgciy9oBlzGv9fz7VPcOyGEG?= =?us-ascii?Q?dKc5ZloOz5QD/VE4c3JPyo7itJdsAGWYewb/uTSo4rheaDpir7NrEth5EX+p?= =?us-ascii?Q?XvRjRx+vkDKGo67Q9aaFD2FkZamHnKZ0GUPqwwLgnuiYQdgnaV+ZrIvdr3G+?= =?us-ascii?Q?xOnzs54QQtT9KgcjdUu8Ff4zpip+pnkDZOgIXnY/gG5KK7I7+L93etpJ/luS?= =?us-ascii?Q?oDF6Ry6NrIRJKOEo+58yYTXb2/PpxRK2ctubnkZQTaTaA6sPbuqJLCG7GaDu?= =?us-ascii?Q?Yd6Pa4TftqL0rgAkD807ncbP5x1HYATl+LeAYTfjlLwlwEnGsviRvsFBRmyU?= =?us-ascii?Q?RK7v6x1eEFdpMcSJhzQ+WkwExRhuAJYh1TR1tRveIFpT6CRH8WmEZRTLrlV0?= =?us-ascii?Q?xdmqbW3pp+nD/4YMH2ytvAuIPC35xAK35TFun2zKUyy4Y1Cyh0J2eQp8RgNx?= =?us-ascii?Q?NivMTybrwR0850UzyteNjEjAVVqDtdFj4aBE5t4ncbWE3AL3fE8n7fG9Wgwh?= =?us-ascii?Q?Vdvy5IoCNoWqdZfPZiGoqWbaAH4Wr/TmuqKPdMqtB5OkPcpFT847rG8QZvJ8?= =?us-ascii?Q?hGy6xsSi+AB9pGh4a16xknYzJMNKTtT7KthV9FhaDvLu00xbTgfX7lohXG9F?= =?us-ascii?Q?XueBjrRjI5QDHe5qr1jWaA46dmC020egP1nSLpCf3pKVrKehpMPqkv0pJRjE?= =?us-ascii?Q?YJnefSKGNOyatnBX+Ny3H2/Xc1kCkY2A9dW1UPdIzTLhGM6kV8KfXYB1GV7q?= =?us-ascii?Q?Jxn2AS/POZmNEN2tWbXlXoGssEuFyFgSzq+JP9kZu7ivZc9tw3aTI4k2YnYt?= =?us-ascii?Q?R7AQhjhJhARNe9fIksy8CM96W8F18V1mYy7IUx0SeJOMruePQ0K9Cp9DZInN?= =?us-ascii?Q?HhYZ4WAZfsRM96HTljElYfMhcQUBZAiNhGcW9ZceOsLSHal9E8Mb4/Jw6BlJ?= =?us-ascii?Q?ewVQ1xF8S7cWVUdsANm1eh6WWAew1iIYIKOnXquraFe5GYEYjxUKzMKXepLG?= =?us-ascii?Q?vQBB2bwbgguCILkU+QAll9myYGx2ACTIaF/J5NIEbmPbTZ2xktPmMDYzUwXH?= =?us-ascii?Q?vZbepMKltgFGddR9+Fjjr7QrBIP+kzOugF0JSknaAogxm3uJ7Gl2w+BiKp0Z?= =?us-ascii?Q?A49EDqNrk5D/Edmv5/u9LGjwocwoJ77fvfC5I/gRdPzG4bhdfw4cPt9KUEhc?= =?us-ascii?Q?ESrzcuBrd5PY1WOxJe7MrLY0EbDEZbXnRypaotRlR3xqMZn7/5MIbWBg7SeM?= =?us-ascii?Q?2V3XFJhR0K8g5etRaMWSm10tcCNjMIvaZF4UDIntW2ajTWCMGTAcBRYy5HhZ?= =?us-ascii?Q?zCNPdeBs5mgpmVGtChCO5YIdAc74kkR9BQMXg05cSFkg3izAPVlvfs8XpBHY?= =?us-ascii?Q?N7ZqE6qFh6U4nDxouU7sPelK3vJHJIVirLUXdRC5SNbs7X2TPcO3qvmKRLlz?= =?us-ascii?Q?qCahHmNausNNZdk4WvHmjCvKoP+FtV8PdRHNvzYb/4YAulwwVwQL5sr7rvqB?= =?us-ascii?Q?sqbmjnUQPRqMHxiE8Wk=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 06:40:04.6177 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 606af4f7-7f34-45db-d123-08de20ed25cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD77.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5647 Content-Type: text/plain; charset="utf-8" Make the definitions explicit. Add some more new codes. The following patches will be using SPDM_REQUEST and EXPAND_BUFFER_LENGTH_REQUEST, others are useful for the PSP FW diagnostics. Signed-off-by: Alexey Kardashevskiy --- include/uapi/linux/psp-sev.h | 66 ++++++++++++-------- 1 file changed, 41 insertions(+), 25 deletions(-) diff --git a/include/uapi/linux/psp-sev.h b/include/uapi/linux/psp-sev.h index c2fd324623c4..2b5b042eb73b 100644 --- a/include/uapi/linux/psp-sev.h +++ b/include/uapi/linux/psp-sev.h @@ -47,32 +47,32 @@ typedef enum { * with possible values from the specification. */ SEV_RET_NO_FW_CALL =3D -1, - SEV_RET_SUCCESS =3D 0, - SEV_RET_INVALID_PLATFORM_STATE, - SEV_RET_INVALID_GUEST_STATE, - SEV_RET_INAVLID_CONFIG, + SEV_RET_SUCCESS =3D 0, + SEV_RET_INVALID_PLATFORM_STATE =3D 0x0001, + SEV_RET_INVALID_GUEST_STATE =3D 0x0002, + SEV_RET_INAVLID_CONFIG =3D 0x0003, SEV_RET_INVALID_CONFIG =3D SEV_RET_INAVLID_CONFIG, - SEV_RET_INVALID_LEN, - SEV_RET_ALREADY_OWNED, - SEV_RET_INVALID_CERTIFICATE, - SEV_RET_POLICY_FAILURE, - SEV_RET_INACTIVE, - SEV_RET_INVALID_ADDRESS, - SEV_RET_BAD_SIGNATURE, - SEV_RET_BAD_MEASUREMENT, - SEV_RET_ASID_OWNED, - SEV_RET_INVALID_ASID, - SEV_RET_WBINVD_REQUIRED, - SEV_RET_DFFLUSH_REQUIRED, - SEV_RET_INVALID_GUEST, - SEV_RET_INVALID_COMMAND, - SEV_RET_ACTIVE, - SEV_RET_HWSEV_RET_PLATFORM, - SEV_RET_HWSEV_RET_UNSAFE, - SEV_RET_UNSUPPORTED, - SEV_RET_INVALID_PARAM, - SEV_RET_RESOURCE_LIMIT, - SEV_RET_SECURE_DATA_INVALID, + SEV_RET_INVALID_LEN =3D 0x0004, + SEV_RET_ALREADY_OWNED =3D 0x0005, + SEV_RET_INVALID_CERTIFICATE =3D 0x0006, + SEV_RET_POLICY_FAILURE =3D 0x0007, + SEV_RET_INACTIVE =3D 0x0008, + SEV_RET_INVALID_ADDRESS =3D 0x0009, + SEV_RET_BAD_SIGNATURE =3D 0x000A, + SEV_RET_BAD_MEASUREMENT =3D 0x000B, + SEV_RET_ASID_OWNED =3D 0x000C, + SEV_RET_INVALID_ASID =3D 0x000D, + SEV_RET_WBINVD_REQUIRED =3D 0x000E, + SEV_RET_DFFLUSH_REQUIRED =3D 0x000F, + SEV_RET_INVALID_GUEST =3D 0x0010, + SEV_RET_INVALID_COMMAND =3D 0x0011, + SEV_RET_ACTIVE =3D 0x0012, + SEV_RET_HWSEV_RET_PLATFORM =3D 0x0013, + SEV_RET_HWSEV_RET_UNSAFE =3D 0x0014, + SEV_RET_UNSUPPORTED =3D 0x0015, + SEV_RET_INVALID_PARAM =3D 0x0016, + SEV_RET_RESOURCE_LIMIT =3D 0x0017, + SEV_RET_SECURE_DATA_INVALID =3D 0x0018, SEV_RET_INVALID_PAGE_SIZE =3D 0x0019, SEV_RET_INVALID_PAGE_STATE =3D 0x001A, SEV_RET_INVALID_MDATA_ENTRY =3D 0x001B, @@ -87,6 +87,22 @@ typedef enum { SEV_RET_RESTORE_REQUIRED =3D 0x0025, SEV_RET_RMP_INITIALIZATION_FAILED =3D 0x0026, SEV_RET_INVALID_KEY =3D 0x0027, + SEV_RET_SHUTDOWN_INCOMPLETE =3D 0x0028, + SEV_RET_INCORRECT_BUFFER_LENGTH =3D 0x0030, + SEV_RET_EXPAND_BUFFER_LENGTH_REQUEST =3D 0x0031, + SEV_RET_SPDM_REQUEST =3D 0x0032, + SEV_RET_SPDM_ERROR =3D 0x0033, + SEV_RET_SEV_STATUS_ERR_IN_DEV_CONN =3D 0x0035, + SEV_RET_SEV_STATUS_INVALID_DEV_CTX =3D 0x0036, + SEV_RET_SEV_STATUS_INVALID_TDI_CTX =3D 0x0037, + SEV_RET_SEV_STATUS_INVALID_TDI =3D 0x0038, + SEV_RET_SEV_STATUS_RECLAIM_REQUIRED =3D 0x0039, + SEV_RET_IN_USE =3D 0x003A, + SEV_RET_SEV_STATUS_INVALID_DEV_STATE =3D 0x003B, + SEV_RET_SEV_STATUS_INVALID_TDI_STATE =3D 0x003C, + SEV_RET_SEV_STATUS_DEV_CERT_CHANGED =3D 0x003D, + SEV_RET_SEV_STATUS_RESYNC_REQ =3D 0x003E, + SEV_RET_SEV_STATUS_RESPONSE_TOO_LARGE =3D 0x003F, SEV_RET_MAX, } sev_ret_code; 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Miller" , Ashish Kalra , Joerg Roedel , "Suravee Suthikulpanit" , Will Deacon , Robin Murphy , Dan Williams , Bjorn Helgaas , Eric Biggers , Brijesh Singh , Gary R Hook , "Borislav Petkov (AMD)" , Kim Phillips , Vasant Hegde , Jason Gunthorpe , "Michael Roth" , Jonathan Cameron , Xu Yilun , Gao Shiyuan , "Sean Christopherson" , Nikunj A Dadhania , Dionna Glaze , , , Alexey Kardashevskiy Subject: [PATCH kernel 4/6] iommu/amd: Report SEV-TIO support Date: Tue, 11 Nov 2025 17:38:16 +1100 Message-ID: <20251111063819.4098701-5-aik@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251111063819.4098701-1-aik@amd.com> References: <20251111063819.4098701-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|IA1PR12MB6459:EE_ X-MS-Office365-Filtering-Correlation-Id: 498cd9cb-aa24-45de-b1f6-08de20ed3369 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Ro+V2vz30ibsykxNCy6xdfR86fOkr18zymnLTQoUfiDqwkyUn8PojcW6bGdI?= =?us-ascii?Q?lPGCbI56Ik0Lq6mebAgLaKoXhXmilsRJMa+XqQaH9oSxZpJoWhkCIi+CR3BC?= =?us-ascii?Q?kKqd0xKA2kbTPqpRNLMGoRTwm0ICICQQRAba9HMY+F2tQdydCnt7VMqjJSu4?= =?us-ascii?Q?lQy5qDbO0K+3e8ecHJc5enV1WNVxaCiiJ4Jo3gST2y3804KnRlvqTWyw2yDw?= =?us-ascii?Q?oiTQAfjhGUEb2sYDeU17IXfxVrntxu6y6+HVe8n8LOhCKq9o+3kqM6O6af1o?= =?us-ascii?Q?S994CHHEXDC7CIosLbMz67MKAa8gT9MfLoNhGeSnGfXjNopEC0RH/Vo6z6ne?= =?us-ascii?Q?Q2vvGydD83MvGhRlLLZsOf9C+iI03sowg4ySQCIQhHvsXp4FBQu/bIF/SPo6?= =?us-ascii?Q?MZ/AF+OoSBkF1X+7O8Nj0AJdFtGyyM0SpjhM+lkz6VIUSQpGOpzfxLakMTut?= =?us-ascii?Q?KloyZKXfTL8DYcn3orKx4m5/QzJc58kmEg1XYybbPupzOrQrpbH9a2qZAs8d?= =?us-ascii?Q?9oVjdfPv/Jb3u3tFh03Ig4qu8R2qq5s5zLtMLmJfDihVcwD6y+0sXNQnTfEK?= =?us-ascii?Q?rVd+MTWcy3v5LDxONRewhNm4ZxeQqGEXRZPMgM7bASfnwr0JXNS4lwYqlUA9?= =?us-ascii?Q?ZMuNsqg4Kr2ASLCwaX7TWqeK10+QkI8k9wpfBnJOvP53vQfMpQzNXREZ2MsC?= =?us-ascii?Q?X5/d99Lt5RDAIjmLgXHfx1IKlv/XQ+ijhrYMcTq9pBdoxrG1VIWEFAq7mIk5?= =?us-ascii?Q?xmUWw83K/cHJn3fa4yRrpkfmyjQ87iz8UfFMbamyFPC1OxAU7ahZGPHvcgWO?= =?us-ascii?Q?C7qSSPWTeMhbgmaIFpU/0uUjsZnqNFTqxt1MzwLTCd230r+8EpTQ6Zm2Fjrd?= =?us-ascii?Q?C4Tv6nPsP0aGoOTC5/8wEtZniqjVch1Qf+2re1ppBSyFgGASN/khz53e/lsj?= =?us-ascii?Q?8qjRNTGdasTCszqUqScemujGWo9539d0fXqlGefe6ocfWYMCObcBwnr9ArQm?= =?us-ascii?Q?yPbDm4jfzCvJcbugcGTcxwPLefefQ4WwnodUGOOiQ4Op+EnrkynZv9fyP4ET?= =?us-ascii?Q?S6HpgLMlwp3srCqaZTNo4d5UCgpleK9k9qD+YjqsH5AXJ8Ygbqey2mQwsAXT?= =?us-ascii?Q?J6my7drkTBO56B0G4RDXrkM7GMqrqjMvImbSXWbotGHMMqqNrG7Vtu3nJQgj?= =?us-ascii?Q?E5UIp07tloTcNfwsGMX3yLFbFolSDB0IhUj0oK8WOWubUHgKue4Ueew6E3hZ?= =?us-ascii?Q?mhdT5Me4vPxsNI8Bc6RHWiDAAbS21Mdr/BTE9OHy2lG5WHEtWruZT0vpadqF?= =?us-ascii?Q?+uycJaA2kopnnXdT1FB4dqlOcnwMMY9doC8v/I2fpLcn3S+JJ++AzdzWkf9u?= =?us-ascii?Q?MweYmjETgN5Mlm23r8nexyBGu+ZIz62zBILE/YVwWUptGClYQ/rjsPBD1gYu?= =?us-ascii?Q?cslMbL+U4RG2KLXDlRr03YtwDDrTYizotUPLXJWjXaNIyvkB530cnXq7ha6g?= =?us-ascii?Q?up4aCJxZ3ZpjISFvfwZzatqH9kiuwkxKVDGchpD1fTsU8ZMf9PIwlD9+Gk2j?= =?us-ascii?Q?Jsq+yqHeUdLgiUef0dI=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 06:40:27.3761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 498cd9cb-aa24-45de-b1f6-08de20ed3369 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6459 Content-Type: text/plain; charset="utf-8" The SEV-TIO switch in the AMD BIOS is reported to the OS via the IOMMU Extended Feature 2 register (EFR2), bit 1. Add helper to parse the bit and report the feature presence. Signed-off-by: Alexey Kardashevskiy --- drivers/iommu/amd/amd_iommu_types.h | 1 + include/linux/amd-iommu.h | 2 ++ drivers/iommu/amd/init.c | 9 +++++++++ 3 files changed, 12 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index a698a2e7ce2a..a2f72c53d3cc 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -107,6 +107,7 @@ =20 =20 /* Extended Feature 2 Bits */ +#define FEATURE_SEVSNPIO_SUP BIT_ULL(1) #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) #define FEATURE_SNPAVICSUP_GAM(x) \ (FIELD_GET(FEATURE_SNPAVICSUP, x) =3D=3D 0x1) diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index 8cced632ecd0..0f64f09d1f34 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -18,10 +18,12 @@ struct task_struct; struct pci_dev; =20 extern void amd_iommu_detect(void); +extern bool amd_iommu_sev_tio_supported(void); =20 #else /* CONFIG_AMD_IOMMU */ =20 static inline void amd_iommu_detect(void) { } +static inline bool amd_iommu_sev_tio_supported(void) { return false; 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Mon, 10 Nov 2025 22:40:41 -0800 From: Alexey Kardashevskiy To: CC: , , Tom Lendacky , John Allen , Herbert Xu , "David S. Miller" , Ashish Kalra , Joerg Roedel , "Suravee Suthikulpanit" , Will Deacon , Robin Murphy , Dan Williams , Bjorn Helgaas , Eric Biggers , Brijesh Singh , Gary R Hook , "Borislav Petkov (AMD)" , Kim Phillips , Vasant Hegde , Jason Gunthorpe , "Michael Roth" , Jonathan Cameron , Xu Yilun , Gao Shiyuan , "Sean Christopherson" , Nikunj A Dadhania , Dionna Glaze , , , Alexey Kardashevskiy Subject: [PATCH kernel 5/6] crypto: ccp: Enable SEV-TIO feature in the PSP when supported Date: Tue, 11 Nov 2025 17:38:17 +1100 Message-ID: <20251111063819.4098701-6-aik@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251111063819.4098701-1-aik@amd.com> References: <20251111063819.4098701-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7A:EE_|BL3PR12MB6427:EE_ X-MS-Office365-Filtering-Correlation-Id: d75020c2-f469-4813-4a2a-08de20ed42c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?eCcgCXdc7aujZ63af/zcgUnm5ihvctw6eOf09JrL+JlbZZ1LI9YPcxbpOiY/?= =?us-ascii?Q?JuD6AKo2i9NAUzK9IUi8MKj5xQRjsnHSwglsf2QUBkUJldWEMPdxuU+45gg4?= =?us-ascii?Q?HFGFZ8CyYr2YDu7KmrbCQ+ed1wm5HEHoeSevZsUrGDyMQROQAkgtS80ry17G?= =?us-ascii?Q?K77LpgBleWslDNbSUxRXWJ00vNfDAZHDefDn7JrdaE2gfThIFPessuD0DJjo?= =?us-ascii?Q?0v5zScB4jw5dM1oR7D9/yQvg/O7d2aBJaCbGTcJOK/AxE0EUAHJih213AuQI?= =?us-ascii?Q?VpHAth1euctAET9MB9g5j5Attcvg/ptfshEmo1aHtEh1DwqHosFCHZo6rVos?= =?us-ascii?Q?z1/a3OO6eTdFa7C0tcE4CGTs1lofh5FCOlcLMlNh7s95a88QUpQzPT1HpKej?= =?us-ascii?Q?fLCMhIf3AaAhHH1SBVkXKGTuBGC4sblJUJ8ikmwO6LGBrV1C3PkwtrF5JSjM?= =?us-ascii?Q?VKDe0X+DV3xBY0V5u2jnRCfuWI88RbbpliNmNWDp0RQXOAiOgurXxzpqGxFt?= =?us-ascii?Q?uMxizcUs6jGaOLaPpdVZ6Wsbgmmqc8IXJ9LkTatdUdbmwoRlc6DJ5pHiKzFn?= =?us-ascii?Q?NaLgCabyBWHS45M1HvSvn0lYQfXg3jQXlvTiygHnjHs546xruoo65DfRB6AS?= =?us-ascii?Q?hxKMzMyuoR2zxgMlBE7z68TC84L/h7rvtMI8cgV6dZClxHhkCNweQmLb5yGR?= =?us-ascii?Q?gWeijR9nbcsgiq3xlkxELjUPmIOkIxMOQP2Z1RttUNverKB9I/JSe+YgSjzy?= =?us-ascii?Q?YpHMiqUg1nc2g8KaX32/5W1t27ciwlC6ZtrgrodyGbfys9e7KSlvVo4gB+r9?= =?us-ascii?Q?Pl/kddwJ2vkuAn0lLNQX/ExZ5PxIS2NdNod/0RSdT9at/CgmOJvmaET/ExIY?= =?us-ascii?Q?zBwjqOQkfvGTYBCBYGbfiyXGfuNjAOuQeygv1duXN9NkISZFjZgjyh63VC7T?= =?us-ascii?Q?PegPK5U03HzpshmYzDTNTbJoXfLaENuwyTh7n9Q+s3TiryUi9DA440Fwxe76?= =?us-ascii?Q?RzcbbBGE9mgYv5RbTMTOIw/8bpv+tYejZRJBP9E4P1rKvrRUi42Z+qA4gjsf?= =?us-ascii?Q?DXgCwUaPmEs9beWO9/MD1oLy9kzuYkpWRGUeyn+S+T6NRLqgmpWvztj39y14?= =?us-ascii?Q?njL1K2MTsjjGej0L56zbPw0BKuNMsbfiAWmKSHV4kUeLZj5VH0r8gUYy8HYY?= =?us-ascii?Q?89sy0xxiPejpvhyAz4JUHq/e3qUiAu+AJBf/dKJtJk912Un971mgjOOCBMMs?= =?us-ascii?Q?mR0VtZhbqjNI/2Zn4lexuNIuIAYG48P8qaPrbNCOiYQUGBzBN8lI40DiDmkh?= =?us-ascii?Q?xpIENIQxX9MG9SJnCi666AQ0ZPqF6tY/Vi4b6QLYyWmqw4oKW2iWj8jawM/B?= =?us-ascii?Q?ZrNPYaAtzN0aTZdIQJpMxRQjt0coyPwLrYaY3c6xAIgcFLaddThzZDZ6NCZH?= =?us-ascii?Q?i+KZM/UiR15B2Pa9O038g4yuPTXOiccSAtWQURB3WWqFxQTCmEG17eO+l4kg?= =?us-ascii?Q?uzxscFvfm3eBCT7YHveEP5MOPaOj7dDiqd6PDhFk4E/Co7jFA/7YL5D8B1iV?= =?us-ascii?Q?oEG22t8ycDhy2XsgZIU=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 06:40:53.1973 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d75020c2-f469-4813-4a2a-08de20ed42c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6427 Content-Type: text/plain; charset="utf-8" The PSP advertises the SEV-TIO support via the FEATURE_INFO command advertised via SNP_PLATFORM_STATUS. The BIOS advertises the SEV-TIO enablement via the IOMMU EFR2 register (added in an earlier patch). Enable SEV-TIO during the SNP_INIT_EX call if both the PSP and the BIOS advertise support for it. Signed-off-by: Alexey Kardashevskiy --- include/linux/psp-sev.h | 4 +++- drivers/crypto/ccp/sev-dev.c | 10 +++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index e3db92e9c687..6162cf5dccde 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -750,7 +750,8 @@ struct sev_data_snp_init_ex { u32 list_paddr_en:1; u32 rapl_dis:1; u32 ciphertext_hiding_en:1; - u32 rsvd:28; + u32 tio_en:1; + u32 rsvd:27; u32 rsvd1; u64 list_paddr; u16 max_snp_asid; @@ -850,6 +851,7 @@ struct snp_feature_info { } __packed; =20 #define SNP_CIPHER_TEXT_HIDING_SUPPORTED BIT(3) +#define SNP_SEV_TIO_SUPPORTED BIT(1) /* EBX */ =20 #ifdef CONFIG_CRYPTO_DEV_SP_PSP =20 diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 9e0c16b36f9c..2f1c9614d359 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -1358,6 +1358,11 @@ static int snp_filter_reserved_mem_regions(struct re= source *rs, void *arg) return 0; } =20 +static bool sev_tio_present(struct sev_device *sev) +{ + return (sev->snp_feat_info_0.ebx & SNP_SEV_TIO_SUPPORTED) !=3D 0; +} + static int __sev_snp_init_locked(int *error, unsigned int max_snp_asid) { struct psp_device *psp =3D psp_master; @@ -1434,6 +1439,8 @@ static int __sev_snp_init_locked(int *error, unsigned= int max_snp_asid) data.init_rmp =3D 1; data.list_paddr_en =3D 1; data.list_paddr =3D __psp_pa(snp_range_list); + data.tio_en =3D sev_tio_present(sev) && + amd_iommu_sev_tio_supported(); cmd =3D SEV_CMD_SNP_INIT_EX; } else { cmd =3D SEV_CMD_SNP_INIT; @@ -1471,7 +1478,8 @@ static int __sev_snp_init_locked(int *error, unsigned= int max_snp_asid) =20 snp_hv_fixed_pages_state_update(sev, HV_FIXED); sev->snp_initialized =3D true; - dev_dbg(sev->dev, "SEV-SNP firmware initialized\n"); + dev_dbg(sev->dev, "SEV-SNP firmware initialized, SEV-TIO is %s\n", + data.tio_en ? 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Miller" , Ashish Kalra , Joerg Roedel , "Suravee Suthikulpanit" , Will Deacon , Robin Murphy , Dan Williams , Bjorn Helgaas , Eric Biggers , Brijesh Singh , Gary R Hook , "Borislav Petkov (AMD)" , Kim Phillips , Vasant Hegde , Jason Gunthorpe , "Michael Roth" , Jonathan Cameron , Xu Yilun , Gao Shiyuan , "Sean Christopherson" , Nikunj A Dadhania , Dionna Glaze , , , Alexey Kardashevskiy Subject: [PATCH kernel 6/6] crypto/ccp: Implement SEV-TIO PCIe IDE (phase1) Date: Tue, 11 Nov 2025 17:38:18 +1100 Message-ID: <20251111063819.4098701-7-aik@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251111063819.4098701-1-aik@amd.com> References: <20251111063819.4098701-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636C:EE_|SA3PR12MB7952:EE_ X-MS-Office365-Filtering-Correlation-Id: 1bf3a512-2f2c-4079-422b-08de20ed52a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0x/9uP3zpGipQKXCABmvmfncLWhrsU66VNvy8KTTNcu7T30P6xyKinXrARbK?= =?us-ascii?Q?XsNcHGxSaUYBAAv005p0hs9BTT/z/ySQfUGIenWrlwToY35H0B7fX7PNg8JE?= =?us-ascii?Q?kpPCm6XKy3OAmw5+7PeiYAOTnMHQwQudGZyJfKIO1MJlfbSRMDq+DR9xEgph?= =?us-ascii?Q?ePvf2j34ISxAaml+kOf9rhPxnJ1jbuHubCFpvvCT10CbHzz7sK78ZY6XY6q2?= =?us-ascii?Q?IYpPqWUc0wJZ/trb+KP84UD4i/53K/ymxUTDTRGHekAHxTE2r2zEFSzPTIJw?= =?us-ascii?Q?fV1UDyvd9Bmfk+x6K2SWBNngYQ9WwJgNudbAoHe7Oys2QEOVc2Qu1uyuDt6r?= =?us-ascii?Q?BW8irCE4TcYLrFm+6uByuu3brEb2Fsmr4ump9O13Wx40cnyPAoYqv7nBZkUk?= =?us-ascii?Q?iKRE8dApgkI3zESgfeMueh+gn44RfwptLMKNiEkqJpprVObC/Lic5sx9ed1o?= =?us-ascii?Q?tf6CT1A7UxAGwlZgDRP7D61op/Pq6RndhRX90521rYn1RhfPLqqEpQH0aTGF?= =?us-ascii?Q?7q2q4QrCvS3Hi9bJLfExcbuJQy9DucUtxEGJkQx0ybFXjO9Hz/Kvo6U13qlK?= =?us-ascii?Q?IBwJ+7UJSaG6iGR+2QRn/fwKaXLVwuqGPc/lfz4WfiZaW9iummf851e82Xj4?= =?us-ascii?Q?dh8XBgVTzvNDsBH6Eoeznq1RG1GOf5FY2xuFaXmttfSSKftKdwujGFE5cwyR?= =?us-ascii?Q?PMEK9DSXomS0fbKcGdM0MPPeh2P5fCallfKRGlaCkATEBPFI2W5HENBdWNLP?= =?us-ascii?Q?k9Dk2YLpXuW4fmQpPSnpvvc8fmBbtQwIKbil7d3o/hcr4u7nZuBu3dv+ylf1?= =?us-ascii?Q?AhQbQyL5btMNn5QqXS1XUOU0+tlUnrzFKSfqLvn+gn+TO/U4St8zcMrkjKib?= =?us-ascii?Q?lRXj8jy0JqbVOcY5ewjxMIrm5CW6CNLyFRYs3V+pEIQGwXOJQ1Z2PQRxLbUb?= =?us-ascii?Q?lJL3j+gHP2ARPrMYjmsMCEOPB0a2PZsI11cSz5TvXHyUju7j+bfihF8ASVNh?= =?us-ascii?Q?gwpJ+nRph0j48bqs7lYnQjB1hZERbvDXBxhvOj/JHUDJ2qtoEhcQUWhd6ghh?= =?us-ascii?Q?M3cK/kK+cxfMGQlwxjF+xTr4xwi0IiLOT/9MuIdAehPkODmcogG3Y8sZG4mR?= =?us-ascii?Q?x5HJKM6TpA0GFj2Z9RkjV3f23LCuC3JExRm7Ijs1/SFpacPSg0oN+O4NyrZv?= =?us-ascii?Q?imIX1j1Q2oZzknzVjYxTd+79ir+NxCfA47h8h2v9ZVr4FhWbhr9u7RIvbLYS?= =?us-ascii?Q?ZdOkpEKdpWw5lgQLsgLaYSAhXjIDOWM6Q6cpE4vS2krEMSZYaCCOGWHzEQjm?= =?us-ascii?Q?Y/qYR4TJV04Isr3/A+zLk9IHjsqY5w1jhY7eAiiTCPP94vVnXWuS3kTewgST?= =?us-ascii?Q?NAmvaV2Ogd6odNRfl6UmuB/uit+cIJXEkJPntogKnToo8mzQ+BOQh7fq79aE?= =?us-ascii?Q?R05DX2IwVb5VAy0DonnJN6yY3XFplkxdQWcbkXlLtgAs/D0OhmC3lXRzBuoO?= =?us-ascii?Q?CIqNQJGmpENjVmAMcFJc72wBtaZbIanNvQD0Yfr/GX5hG78BqkgtyyK5HGge?= =?us-ascii?Q?K9v18pIDrmJZ09gxubU=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 06:41:19.8480 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1bf3a512-2f2c-4079-422b-08de20ed52a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7952 Content-Type: text/plain; charset="utf-8" Implement the SEV-TIO (Trusted I/O) firmware interface for PCIe TDISP (Trust Domain In-Socket Protocol). This enables secure communication between trusted domains and PCIe devices through the PSP (Platform Security Processor). The implementation includes: - Device Security Manager (DSM) operations for establishing secure links - SPDM (Security Protocol and Data Model) over DOE (Data Object Exchange) - IDE (Integrity Data Encryption) stream management for secure PCIe This module bridges the SEV firmware stack with the generic PCIe TSM framework. This is phase1 as described in Documentation/driver-api/pci/tsm.rst. On AMD SEV, the AMD PSP firmware acts as TSM (manages the security/trust). The CCP driver provides the interface to it and registers in the TSM subsystem. Implement SEV TIO PSP command wrappers in sev-dev-tio.c and store the data in the SEV-TIO-specific structs. Implement TSM hooks and IDE setup in sev-dev-tsm.c. Signed-off-by: Alexey Kardashevskiy --- drivers/crypto/ccp/Kconfig | 1 + drivers/crypto/ccp/Makefile | 8 + drivers/crypto/ccp/sev-dev-tio.h | 141 +++ drivers/crypto/ccp/sev-dev.h | 7 + include/linux/psp-sev.h | 12 + drivers/crypto/ccp/sev-dev-tio.c | 989 ++++++++++++++++++++ drivers/crypto/ccp/sev-dev-tsm.c | 435 +++++++++ drivers/crypto/ccp/sev-dev.c | 48 +- 8 files changed, 1640 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/ccp/Kconfig b/drivers/crypto/ccp/Kconfig index f394e45e11ab..3e737d3e21c8 100644 --- a/drivers/crypto/ccp/Kconfig +++ b/drivers/crypto/ccp/Kconfig @@ -25,6 +25,7 @@ config CRYPTO_DEV_CCP_CRYPTO default m depends on CRYPTO_DEV_CCP_DD depends on CRYPTO_DEV_SP_CCP + select PCI_TSM select CRYPTO_HASH select CRYPTO_SKCIPHER select CRYPTO_AUTHENC diff --git a/drivers/crypto/ccp/Makefile b/drivers/crypto/ccp/Makefile index a9626b30044a..839df68b70ff 100644 --- a/drivers/crypto/ccp/Makefile +++ b/drivers/crypto/ccp/Makefile @@ -16,6 +16,14 @@ ccp-$(CONFIG_CRYPTO_DEV_SP_PSP) +=3D psp-dev.o \ hsti.o \ sfs.o =20 +ifeq ($(CONFIG_CRYPTO_DEV_SP_PSP)$(CONFIG_PCI_TSM),yy) +ccp-y +=3D sev-dev-tsm.o sev-dev-tio.o +endif + +ifeq ($(CONFIG_CRYPTO_DEV_SP_PSP)$(CONFIG_PCI_TSM),my) +ccp-m +=3D sev-dev-tsm.o sev-dev-tio.o +endif + obj-$(CONFIG_CRYPTO_DEV_CCP_CRYPTO) +=3D ccp-crypto.o ccp-crypto-objs :=3D ccp-crypto-main.o \ ccp-crypto-aes.o \ diff --git a/drivers/crypto/ccp/sev-dev-tio.h b/drivers/crypto/ccp/sev-dev-= tio.h new file mode 100644 index 000000000000..c72ac38d4351 --- /dev/null +++ b/drivers/crypto/ccp/sev-dev-tio.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __PSP_SEV_TIO_H__ +#define __PSP_SEV_TIO_H__ + +#include +#include +#include +#include + +#if defined(CONFIG_CRYPTO_DEV_SP_PSP) + +/* Return codes from SEV-TIO helpers to request DOE MB transaction */ +#define TSM_PROTO_CMA_SPDM 1 +#define TSM_PROTO_SECURED_CMA_SPDM 2 + +struct sla_addr_t { + union { + u64 sla; + struct { + u64 page_type:1; + u64 page_size:1; + u64 reserved1:10; + u64 pfn:40; + u64 reserved2:12; + }; + }; +} __packed; + +#define SEV_TIO_MAX_COMMAND_LENGTH 128 + +/* Describes TIO device */ +struct tsm_dsm_tio { + struct sla_addr_t dev_ctx; + struct sla_addr_t req; + struct sla_addr_t resp; + struct sla_addr_t scratch; + struct sla_addr_t output; + size_t output_len; + size_t scratch_len; + struct sla_buffer_hdr *reqbuf; /* vmap'ed @req for DOE */ + struct sla_buffer_hdr *respbuf; /* vmap'ed @resp for DOE */ + + int cmd; + int psp_ret; + u8 cmd_data[SEV_TIO_MAX_COMMAND_LENGTH]; + void *data_pg; /* Data page for DEV_STATUS/TDI_STATUS/TDI_INFO/ASID_FENCE= */ + +#define TIO_IDE_MAX_TC 8 + struct pci_ide *ide[TIO_IDE_MAX_TC]; +}; + +/* Described TSM structure for PF0 pointed by pci_dev->tsm */ +struct tio_dsm { + struct pci_tsm_pf0 tsm; + struct tsm_dsm_tio data; + struct sev_device *sev; +}; + +/* Data object IDs */ +#define SPDM_DOBJ_ID_NONE 0 +#define SPDM_DOBJ_ID_REQ 1 +#define SPDM_DOBJ_ID_RESP 2 + +struct spdm_dobj_hdr { + u32 id; /* Data object type identifier */ + u32 length; /* Length of the data object, INCLUDING THIS HEADER */ + union { + u16 ver; /* Version of the data object structure */ + struct { + u8 minor; + u8 major; + } version; + }; +} __packed; + +/** + * struct sev_tio_status - TIO_STATUS command's info_paddr buffer + * + * @length: Length of this structure in bytes + * @tio_en: Indicates that SNP_INIT_EX initialized the RMP for SEV-TIO + * @tio_init_done: Indicates TIO_INIT has been invoked + * @spdm_req_size_min: Minimum SPDM request buffer size in bytes + * @spdm_req_size_max: Maximum SPDM request buffer size in bytes + * @spdm_scratch_size_min: Minimum SPDM scratch buffer size in bytes + * @spdm_scratch_size_max: Maximum SPDM scratch buffer size in bytes + * @spdm_out_size_min: Minimum SPDM output buffer size in bytes + * @spdm_out_size_max: Maximum for the SPDM output buffer size in bytes + * @spdm_rsp_size_min: Minimum SPDM response buffer size in bytes + * @spdm_rsp_size_max: Maximum SPDM response buffer size in bytes + * @devctx_size: Size of a device context buffer in bytes + * @tdictx_size: Size of a TDI context buffer in bytes + * @tio_crypto_alg: TIO crypto algorithms supported + */ +struct sev_tio_status { + u32 length; + union { + u32 flags; + struct { + u32 tio_en:1; + u32 tio_init_done:1; + }; + }; + u32 spdm_req_size_min; + u32 spdm_req_size_max; + u32 spdm_scratch_size_min; + u32 spdm_scratch_size_max; + u32 spdm_out_size_min; + u32 spdm_out_size_max; + u32 spdm_rsp_size_min; + u32 spdm_rsp_size_max; + u32 devctx_size; + u32 tdictx_size; + u32 tio_crypto_alg; + u8 reserved[12]; +} __packed; + +int sev_tio_init_locked(void *tio_status_page); +int sev_tio_continue(struct tsm_dsm_tio *dev_data, struct tsm_spdm *spdm); + +int sev_tio_dev_create(struct tsm_dsm_tio *dev_data, u16 device_id, u16 ro= ot_port_id, + u8 segment_id); +int sev_tio_dev_connect(struct tsm_dsm_tio *dev_data, u8 tc_mask, u8 ids[8= ], u8 cert_slot, + struct tsm_spdm *spdm); +int sev_tio_dev_disconnect(struct tsm_dsm_tio *dev_data, struct tsm_spdm *= spdm, bool force); +int sev_tio_dev_reclaim(struct tsm_dsm_tio *dev_data, struct tsm_spdm *spd= m); + +int sev_tio_asid_fence_clear(struct sla_addr_t dev_ctx, u64 gctx_paddr, in= t *psp_ret); +int sev_tio_asid_fence_status(struct tsm_dsm_tio *dev_data, u16 device_id,= u8 segment_id, + u32 asid, bool *fenced); + +#endif /* CONFIG_CRYPTO_DEV_SP_PSP */ + +#if defined(CONFIG_PCI_TSM) +void sev_tsm_init_locked(struct sev_device *sev, void *tio_status_page); +void sev_tsm_uninit(struct sev_device *sev); +int sev_tio_cmd_buffer_len(int cmd); +#else +static inline int sev_tio_cmd_buffer_len(int cmd) { return 0; } +#endif + +#endif /* __PSP_SEV_TIO_H__ */ diff --git a/drivers/crypto/ccp/sev-dev.h b/drivers/crypto/ccp/sev-dev.h index 5cc08661b5b6..754353becc9c 100644 --- a/drivers/crypto/ccp/sev-dev.h +++ b/drivers/crypto/ccp/sev-dev.h @@ -34,6 +34,8 @@ struct sev_misc_dev { struct miscdevice misc; }; =20 +struct sev_tio_status; + struct sev_device { struct device *dev; struct psp_device *psp; @@ -61,6 +63,11 @@ struct sev_device { =20 struct sev_user_data_snp_status snp_plat_status; struct snp_feature_info snp_feat_info_0; + +#if defined(CONFIG_PCI_TSM) + struct tsm_dev *tsmdev; + struct sev_tio_status *tio_status; +#endif }; =20 int sev_dev_init(struct psp_device *psp); diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index 6162cf5dccde..14263b6f6e32 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -109,6 +109,18 @@ enum sev_cmd { SEV_CMD_SNP_VLEK_LOAD =3D 0x0CD, SEV_CMD_SNP_FEATURE_INFO =3D 0x0CE, =20 + /* SEV-TIO commands */ + SEV_CMD_TIO_STATUS =3D 0x0D0, + SEV_CMD_TIO_INIT =3D 0x0D1, + SEV_CMD_TIO_DEV_CREATE =3D 0x0D2, + SEV_CMD_TIO_DEV_RECLAIM =3D 0x0D3, + SEV_CMD_TIO_DEV_CONNECT =3D 0x0D4, + SEV_CMD_TIO_DEV_DISCONNECT =3D 0x0D5, + SEV_CMD_TIO_DEV_STATUS =3D 0x0D6, + SEV_CMD_TIO_DEV_MEASUREMENTS =3D 0x0D7, + SEV_CMD_TIO_DEV_CERTIFICATES =3D 0x0D8, + SEV_CMD_TIO_ASID_FENCE_CLEAR =3D 0x0E1, + SEV_CMD_TIO_ASID_FENCE_STATUS =3D 0x0E2, SEV_CMD_MAX, }; =20 diff --git a/drivers/crypto/ccp/sev-dev-tio.c b/drivers/crypto/ccp/sev-dev-= tio.c new file mode 100644 index 000000000000..ca0db6e64839 --- /dev/null +++ b/drivers/crypto/ccp/sev-dev-tio.c @@ -0,0 +1,989 @@ +// SPDX-License-Identifier: GPL-2.0-only + +// Interface to PSP for CCP/SEV-TIO/SNP-VM + +#include +#include +#include +#include +#include +#include +#include +#include +#include "sev-dev.h" +#include "sev-dev-tio.h" + +#define to_tio_status(dev_data) \ + (container_of((dev_data), struct tio_dsm, data)->sev->tio_status) + +static void *__prep_data_pg(struct tsm_dsm_tio *dev_data, size_t len) +{ + void *r =3D dev_data->data_pg; + + if (snp_reclaim_pages(virt_to_phys(r), 1, false)) + return NULL; + + memset(r, 0, len); + + if (rmp_make_private(page_to_pfn(virt_to_page(r)), 0, PG_LEVEL_4K, 0, tru= e)) + return NULL; + + return r; +} + +#define prep_data_pg(type, tdev) ((type *) __prep_data_pg((tdev), sizeof(t= ype))) + +#define SLA_PAGE_TYPE_DATA 0 +#define SLA_PAGE_TYPE_SCATTER 1 +#define SLA_PAGE_SIZE_4K 0 +#define SLA_PAGE_SIZE_2M 1 +#define SLA_SZ(s) ((s).page_size =3D=3D SLA_PAGE_SIZE_2M ? SZ_2M : SZ_4K) +#define SLA_SCATTER_LEN(s) (SLA_SZ(s) / sizeof(struct sla_addr_t)) +#define SLA_EOL ((struct sla_addr_t) { .pfn =3D ((1UL << 40) - 1) }) +#define SLA_NULL ((struct sla_addr_t) { 0 }) +#define IS_SLA_NULL(s) ((s).sla =3D=3D SLA_NULL.sla) +#define IS_SLA_EOL(s) ((s).sla =3D=3D SLA_EOL.sla) + +static phys_addr_t sla_to_pa(struct sla_addr_t sla) +{ + u64 pfn =3D sla.pfn; + u64 pa =3D pfn << PAGE_SHIFT; + + return pa; +} + +static void *sla_to_va(struct sla_addr_t sla) +{ + void *va =3D __va(__sme_clr(sla_to_pa(sla))); + + return va; +} + +#define sla_to_pfn(sla) (__pa(sla_to_va(sla)) >> PAGE_SHIFT) +#define sla_to_page(sla) virt_to_page(sla_to_va(sla)) + +static struct sla_addr_t make_sla(struct page *pg, bool stp) +{ + u64 pa =3D __sme_set(page_to_phys(pg)); + struct sla_addr_t ret =3D { + .pfn =3D pa >> PAGE_SHIFT, + .page_size =3D SLA_PAGE_SIZE_4K, /* Do not do SLA_PAGE_SIZE_2M ATM */ + .page_type =3D stp ? SLA_PAGE_TYPE_SCATTER : SLA_PAGE_TYPE_DATA + }; + + return ret; +} + +/* the BUFFER Structure */ +struct sla_buffer_hdr { + u32 capacity_sz; + u32 payload_sz; /* The size of BUFFER_PAYLOAD in bytes. Must be multiple = of 32B */ + union { + u32 flags; + struct { + u32 encryption:1; + }; + }; + u32 reserved1; + u8 iv[16]; /* IV used for the encryption of this buffer */ + u8 authtag[16]; /* Authentication tag for this buffer */ + u8 reserved2[16]; +} __packed; + +enum spdm_data_type_t { + DOBJ_DATA_TYPE_SPDM =3D 0x1, + DOBJ_DATA_TYPE_SECURE_SPDM =3D 0x2, +}; + +struct spdm_dobj_hdr_req { + struct spdm_dobj_hdr hdr; /* hdr.id =3D=3D SPDM_DOBJ_ID_REQ */ + u8 data_type; /* spdm_data_type_t */ + u8 reserved2[5]; +} __packed; + +struct spdm_dobj_hdr_resp { + struct spdm_dobj_hdr hdr; /* hdr.id =3D=3D SPDM_DOBJ_ID_RESP */ + u8 data_type; /* spdm_data_type_t */ + u8 reserved2[5]; +} __packed; + +/* Defined in sev-dev-tio.h so sev-dev-tsm.c can read types of blobs */ +struct spdm_dobj_hdr_cert; +struct spdm_dobj_hdr_meas; +struct spdm_dobj_hdr_report; + +/* Used in all SPDM-aware TIO commands */ +struct spdm_ctrl { + struct sla_addr_t req; + struct sla_addr_t resp; + struct sla_addr_t scratch; + struct sla_addr_t output; +} __packed; + +static size_t sla_dobj_id_to_size(u8 id) +{ + size_t n; + + BUILD_BUG_ON(sizeof(struct spdm_dobj_hdr_resp) !=3D 0x10); + switch (id) { + case SPDM_DOBJ_ID_REQ: + n =3D sizeof(struct spdm_dobj_hdr_req); + break; + case SPDM_DOBJ_ID_RESP: + n =3D sizeof(struct spdm_dobj_hdr_resp); + break; + default: + WARN_ON(1); + n =3D 0; + break; + } + + return n; +} + +#define SPDM_DOBJ_HDR_SIZE(hdr) sla_dobj_id_to_size((hdr)->id) +#define SPDM_DOBJ_DATA(hdr) ((u8 *)(hdr) + SPDM_DOBJ_HDR_SIZE(hdr)) +#define SPDM_DOBJ_LEN(hdr) ((hdr)->length - SPDM_DOBJ_HDR_SIZE(hdr)) + +#define sla_to_dobj_resp_hdr(buf) ((struct spdm_dobj_hdr_resp *) \ + sla_to_dobj_hdr_check((buf), SPDM_DOBJ_ID_RESP)) +#define sla_to_dobj_req_hdr(buf) ((struct spdm_dobj_hdr_req *) \ + sla_to_dobj_hdr_check((buf), SPDM_DOBJ_ID_REQ)) + +static struct spdm_dobj_hdr *sla_to_dobj_hdr(struct sla_buffer_hdr *buf) +{ + if (!buf) + return NULL; + + return (struct spdm_dobj_hdr *) &buf[1]; +} + +static struct spdm_dobj_hdr *sla_to_dobj_hdr_check(struct sla_buffer_hdr *= buf, u32 check_dobjid) +{ + struct spdm_dobj_hdr *hdr =3D sla_to_dobj_hdr(buf); + + if (WARN_ON_ONCE(!hdr)) + return NULL; + + if (hdr->id !=3D check_dobjid) { + pr_err("! ERROR: expected %d, found %d\n", check_dobjid, hdr->id); + return NULL; + } + + return hdr; +} + +static void *sla_to_data(struct sla_buffer_hdr *buf, u32 dobjid) +{ + struct spdm_dobj_hdr *hdr =3D sla_to_dobj_hdr(buf); + + if (WARN_ON_ONCE(dobjid !=3D SPDM_DOBJ_ID_REQ && dobjid !=3D SPDM_DOBJ_ID= _RESP)) + return NULL; + + if (!hdr) + return NULL; + + return (u8 *) hdr + sla_dobj_id_to_size(dobjid); +} + +/** + * struct sev_data_tio_status - SEV_CMD_TIO_STATUS command + * + * @length: Length of this command buffer in bytes + * @status_paddr: SPA of the TIO_STATUS structure + */ +struct sev_data_tio_status { + u32 length; + u32 reserved; + u64 status_paddr; +} __packed; + +/* TIO_INIT */ +struct sev_data_tio_init { + u32 length; + u32 reserved[3]; +} __packed; + +/** + * struct sev_data_tio_dev_create - TIO_DEV_CREATE command + * + * @length: Length in bytes of this command buffer. + * @dev_ctx_sla: A scatter list address pointing to a buffer to be used as= a device context buffer. + * @device_id: The PCIe Routing Identifier of the device to connect to. + * @root_port_id: FiXME: The PCIe Routing Identifier of the root port of t= he device. + * @segment_id: The PCIe Segment Identifier of the device to connect to. + */ +struct sev_data_tio_dev_create { + u32 length; + u32 reserved1; + struct sla_addr_t dev_ctx_sla; + u16 device_id; + u16 root_port_id; + u8 segment_id; + u8 reserved2[11]; +} __packed; + +/** + * struct sev_data_tio_dev_connect - TIO_DEV_CONNECT + * + * @length: Length in bytes of this command buffer. + * @spdm_ctrl: SPDM control structure defined in Section 5.1. + * @device_id: The PCIe Routing Identifier of the device to connect to. + * @root_port_id: The PCIe Routing Identifier of the root port of the devi= ce. + * @segment_id: The PCIe Segment Identifier of the device to connect to. + * @dev_ctx_sla: Scatter list address of the device context buffer. + * @tc_mask: Bitmask of the traffic classes to initialize for SEV-TIO usag= e. + * Setting the kth bit of the TC_MASK to 1 indicates that the tr= affic + * class k will be initialized. + * @cert_slot: Slot number of the certificate requested for constructing t= he SPDM session. + * @ide_stream_id: IDE stream IDs to be associated with this device. + * Valid only if corresponding bit in TC_MASK is set. + */ +struct sev_data_tio_dev_connect { + u32 length; + u32 reserved1; + struct spdm_ctrl spdm_ctrl; + u8 reserved2[8]; + struct sla_addr_t dev_ctx_sla; + u8 tc_mask; + u8 cert_slot; + u8 reserved3[6]; + u8 ide_stream_id[8]; + u8 reserved4[8]; +} __packed; + +/** + * struct sev_data_tio_dev_disconnect - TIO_DEV_DISCONNECT + * + * @length: Length in bytes of this command buffer. + * @force: Force device disconnect without SPDM traffic. + * @spdm_ctrl: SPDM control structure defined in Section 5.1. + * @dev_ctx_sla: Scatter list address of the device context buffer. + */ +struct sev_data_tio_dev_disconnect { + u32 length; + union { + u32 flags; + struct { + u32 force:1; + }; + }; + struct spdm_ctrl spdm_ctrl; + struct sla_addr_t dev_ctx_sla; +} __packed; + +/** + * struct sev_data_tio_dev_meas - TIO_DEV_MEASUREMENTS + * + * @length: Length in bytes of this command buffer + * @raw_bitstream: 0: Requests the digest form of the attestation report + * 1: Requests the raw bitstream form of the attestation r= eport + * @spdm_ctrl: SPDM control structure defined in Section 5.1. + * @dev_ctx_sla: Scatter list address of the device context buffer. + */ +struct sev_data_tio_dev_meas { + u32 length; + union { + u32 flags; + struct { + u32 raw_bitstream:1; + }; + }; + struct spdm_ctrl spdm_ctrl; + struct sla_addr_t dev_ctx_sla; + u8 meas_nonce[32]; +} __packed; + +/** + * struct sev_data_tio_dev_certs - TIO_DEV_CERTIFICATES + * + * @length: Length in bytes of this command buffer + * @spdm_ctrl: SPDM control structure defined in Section 5.1. + * @dev_ctx_sla: Scatter list address of the device context buffer. + */ +struct sev_data_tio_dev_certs { + u32 length; + u32 reserved; + struct spdm_ctrl spdm_ctrl; + struct sla_addr_t dev_ctx_sla; +} __packed; + +/** + * struct sev_data_tio_dev_reclaim - TIO_DEV_RECLAIM command + * + * @length: Length in bytes of this command buffer + * @dev_ctx_paddr: SPA of page donated by hypervisor + */ +struct sev_data_tio_dev_reclaim { + u32 length; + u32 reserved; + struct sla_addr_t dev_ctx_sla; +} __packed; + +/** + * struct sev_data_tio_asid_fence_clear - TIO_ASID_FENCE_CLEAR command + * + * @length: Length in bytes of this command buffer + * @dev_ctx_paddr: Scatter list address of device context + * @gctx_paddr: System physical address of guest context page + * + * This command clears the ASID fence for a TDI. + */ +struct sev_data_tio_asid_fence_clear { + u32 length; /* In */ + u32 reserved1; + struct sla_addr_t dev_ctx_paddr; /* In */ + u64 gctx_paddr; /* In */ + u8 reserved2[8]; +} __packed; + +/** + * struct sev_data_tio_asid_fence_status - TIO_ASID_FENCE_STATUS command + * + * @length: Length in bytes of this command buffer + * @dev_ctx_paddr: Scatter list address of device context + * @asid: Address Space Identifier to query + * @status_pa: System physical address where fence status will be written + * + * This command queries the fence status for a specific ASID. + */ +struct sev_data_tio_asid_fence_status { + u32 length; /* In */ + u8 reserved1[4]; + struct sla_addr_t dev_ctx_paddr; /* In */ + u32 asid; /* In */ + u64 status_pa; + u8 reserved2[4]; +} __packed; + +static struct sla_buffer_hdr *sla_buffer_map(struct sla_addr_t sla) +{ + struct sla_buffer_hdr *buf; + + BUILD_BUG_ON(sizeof(struct sla_buffer_hdr) !=3D 0x40); + if (IS_SLA_NULL(sla)) + return NULL; + + if (sla.page_type =3D=3D SLA_PAGE_TYPE_SCATTER) { + struct sla_addr_t *scatter =3D sla_to_va(sla); + unsigned int i, npages =3D 0; + struct page **pp; + + for (i =3D 0; i < SLA_SCATTER_LEN(sla); ++i) { + if (WARN_ON_ONCE(SLA_SZ(scatter[i]) > SZ_4K)) + return NULL; + + if (WARN_ON_ONCE(scatter[i].page_type =3D=3D SLA_PAGE_TYPE_SCATTER)) + return NULL; + + if (IS_SLA_EOL(scatter[i])) { + npages =3D i; + break; + } + } + if (WARN_ON_ONCE(!npages)) + return NULL; + + pp =3D kmalloc_array(npages, sizeof(pp[0]), GFP_KERNEL); + if (!pp) + return NULL; + + for (i =3D 0; i < npages; ++i) + pp[i] =3D sla_to_page(scatter[i]); + + buf =3D vm_map_ram(pp, npages, 0); + kfree(pp); + } else { + struct page *pg =3D sla_to_page(sla); + + buf =3D vm_map_ram(&pg, 1, 0); + } + + return buf; +} + +static void sla_buffer_unmap(struct sla_addr_t sla, struct sla_buffer_hdr = *buf) +{ + if (!buf) + return; + + if (sla.page_type =3D=3D SLA_PAGE_TYPE_SCATTER) { + struct sla_addr_t *scatter =3D sla_to_va(sla); + unsigned int i, npages =3D 0; + + for (i =3D 0; i < SLA_SCATTER_LEN(sla); ++i) { + if (IS_SLA_EOL(scatter[i])) { + npages =3D i; + break; + } + } + if (!npages) + return; + + vm_unmap_ram(buf, npages); + } else { + vm_unmap_ram(buf, 1); + } +} + +static void dobj_response_init(struct sla_buffer_hdr *buf) +{ + struct spdm_dobj_hdr *dobj =3D sla_to_dobj_hdr(buf); + + dobj->id =3D SPDM_DOBJ_ID_RESP; + dobj->version.major =3D 0x1; + dobj->version.minor =3D 0; + dobj->length =3D 0; + buf->payload_sz =3D sla_dobj_id_to_size(dobj->id) + dobj->length; +} + +static void sla_free(struct sla_addr_t sla, size_t len, bool firmware_stat= e) +{ + unsigned int npages =3D PAGE_ALIGN(len) >> PAGE_SHIFT; + struct sla_addr_t *scatter =3D NULL; + int ret =3D 0, i; + + if (IS_SLA_NULL(sla)) + return; + + if (firmware_state) { + if (sla.page_type =3D=3D SLA_PAGE_TYPE_SCATTER) { + scatter =3D sla_to_va(sla); + + for (i =3D 0; i < npages; ++i) { + if (IS_SLA_EOL(scatter[i])) + break; + + ret =3D snp_reclaim_pages(sla_to_pa(scatter[i]), 1, false); + if (ret) + break; + } + } else { + ret =3D snp_reclaim_pages(sla_to_pa(sla), 1, false); + } + } + + if (WARN_ON(ret)) + return; + + if (scatter) { + for (i =3D 0; i < npages; ++i) { + if (IS_SLA_EOL(scatter[i])) + break; + free_page((unsigned long)sla_to_va(scatter[i])); + } + } + + free_page((unsigned long)sla_to_va(sla)); +} + +static struct sla_addr_t sla_alloc(size_t len, bool firmware_state) +{ + unsigned long i, npages =3D PAGE_ALIGN(len) >> PAGE_SHIFT; + struct sla_addr_t *scatter =3D NULL; + struct sla_addr_t ret =3D SLA_NULL; + struct sla_buffer_hdr *buf; + struct page *pg; + + if (npages =3D=3D 0) + return ret; + + if (WARN_ON_ONCE(npages > ((PAGE_SIZE / sizeof(struct sla_addr_t)) + 1))) + return ret; + + BUILD_BUG_ON(PAGE_SIZE < SZ_4K); + + if (npages > 1) { + pg =3D alloc_page(GFP_KERNEL | __GFP_ZERO); + if (!pg) + return SLA_NULL; + + ret =3D make_sla(pg, true); + scatter =3D page_to_virt(pg); + for (i =3D 0; i < npages; ++i) { + pg =3D alloc_page(GFP_KERNEL | __GFP_ZERO); + if (!pg) + goto no_reclaim_exit; + + scatter[i] =3D make_sla(pg, false); + } + scatter[i] =3D SLA_EOL; + } else { + pg =3D alloc_page(GFP_KERNEL | __GFP_ZERO); + if (!pg) + return SLA_NULL; + + ret =3D make_sla(pg, false); + } + + buf =3D sla_buffer_map(ret); + if (!buf) + goto no_reclaim_exit; + + buf->capacity_sz =3D (npages << PAGE_SHIFT); + sla_buffer_unmap(ret, buf); + + if (firmware_state) { + if (scatter) { + for (i =3D 0; i < npages; ++i) { + if (rmp_make_private(sla_to_pfn(scatter[i]), 0, + PG_LEVEL_4K, 0, true)) + goto free_exit; + } + } else { + if (rmp_make_private(sla_to_pfn(ret), 0, PG_LEVEL_4K, 0, true)) + goto no_reclaim_exit; + } + } + + return ret; + +no_reclaim_exit: + firmware_state =3D false; +free_exit: + sla_free(ret, len, firmware_state); + return SLA_NULL; +} + +/* Expands a buffer, only firmware owned buffers allowed for now */ +static int sla_expand(struct sla_addr_t *sla, size_t *len) +{ + struct sla_buffer_hdr *oldbuf =3D sla_buffer_map(*sla), *newbuf; + struct sla_addr_t oldsla =3D *sla, newsla; + size_t oldlen =3D *len, newlen; + + if (!oldbuf) + return -EFAULT; + + newlen =3D oldbuf->capacity_sz; + if (oldbuf->capacity_sz =3D=3D oldlen) { + /* This buffer does not require expansion, must be another buffer */ + sla_buffer_unmap(oldsla, oldbuf); + return 1; + } + + pr_notice("Expanding BUFFER from %ld to %ld bytes\n", oldlen, newlen); + + newsla =3D sla_alloc(newlen, true); + if (IS_SLA_NULL(newsla)) + return -ENOMEM; + + newbuf =3D sla_buffer_map(newsla); + if (!newbuf) { + sla_free(newsla, newlen, true); + return -EFAULT; + } + + memcpy(newbuf, oldbuf, oldlen); + + sla_buffer_unmap(newsla, newbuf); + sla_free(oldsla, oldlen, true); + *sla =3D newsla; + *len =3D newlen; + + return 0; +} + +static int sev_tio_do_cmd(int cmd, void *data, size_t data_len, int *psp_r= et, + struct tsm_dsm_tio *dev_data, struct tsm_spdm *spdm) +{ + int rc; + + *psp_ret =3D 0; + rc =3D sev_do_cmd(cmd, data, psp_ret); + + if (WARN_ON(!spdm && !rc && *psp_ret =3D=3D SEV_RET_SPDM_REQUEST)) + return -EIO; + + if (rc =3D=3D 0 && *psp_ret =3D=3D SEV_RET_EXPAND_BUFFER_LENGTH_REQUEST) { + int rc1, rc2; + + rc1 =3D sla_expand(&dev_data->output, &dev_data->output_len); + if (rc1 < 0) + return rc1; + + rc2 =3D sla_expand(&dev_data->scratch, &dev_data->scratch_len); + if (rc2 < 0) + return rc2; + + if (!rc1 && !rc2) + /* Neither buffer requires expansion, this is wrong */ + return -EFAULT; + + *psp_ret =3D 0; + rc =3D sev_do_cmd(cmd, data, psp_ret); + } + + if (spdm && (rc =3D=3D 0 || rc =3D=3D -EIO) && *psp_ret =3D=3D SEV_RET_SP= DM_REQUEST) { + struct spdm_dobj_hdr_resp *resp_hdr; + struct spdm_dobj_hdr_req *req_hdr; + struct sev_tio_status *tio_status =3D to_tio_status(dev_data); + size_t resp_len =3D tio_status->spdm_req_size_max - + (sla_dobj_id_to_size(SPDM_DOBJ_ID_RESP) + sizeof(struct sla_buffer_hdr)= ); + + if (!dev_data->cmd) { + if (WARN_ON_ONCE(!data_len || (data_len !=3D *(u32 *) data))) + return -EINVAL; + if (WARN_ON(data_len > sizeof(dev_data->cmd_data))) + return -EFAULT; + memcpy(dev_data->cmd_data, data, data_len); + memset(&dev_data->cmd_data[data_len], 0xFF, + sizeof(dev_data->cmd_data) - data_len); + dev_data->cmd =3D cmd; + } + + req_hdr =3D sla_to_dobj_req_hdr(dev_data->reqbuf); + resp_hdr =3D sla_to_dobj_resp_hdr(dev_data->respbuf); + switch (req_hdr->data_type) { + case DOBJ_DATA_TYPE_SPDM: + rc =3D TSM_PROTO_CMA_SPDM; + break; + case DOBJ_DATA_TYPE_SECURE_SPDM: + rc =3D TSM_PROTO_SECURED_CMA_SPDM; + break; + default: + rc =3D -EINVAL; + return rc; + } + resp_hdr->data_type =3D req_hdr->data_type; + spdm->req_len =3D req_hdr->hdr.length - sla_dobj_id_to_size(SPDM_DOBJ_ID= _REQ); + spdm->rsp_len =3D resp_len; + } else if (dev_data && dev_data->cmd) { + /* For either error or success just stop the bouncing */ + memset(dev_data->cmd_data, 0, sizeof(dev_data->cmd_data)); + dev_data->cmd =3D 0; + } + + return rc; +} + +int sev_tio_continue(struct tsm_dsm_tio *dev_data, struct tsm_spdm *spdm) +{ + struct spdm_dobj_hdr_resp *resp_hdr; + int ret; + + if (!dev_data || !dev_data->cmd) + return -EINVAL; + + resp_hdr =3D sla_to_dobj_resp_hdr(dev_data->respbuf); + resp_hdr->hdr.length =3D ALIGN(sla_dobj_id_to_size(SPDM_DOBJ_ID_RESP) + s= pdm->rsp_len, 32); + dev_data->respbuf->payload_sz =3D resp_hdr->hdr.length; + + ret =3D sev_tio_do_cmd(dev_data->cmd, dev_data->cmd_data, 0, + &dev_data->psp_ret, dev_data, spdm); + + if (!ret && (dev_data->psp_ret !=3D SEV_RET_SUCCESS)) + return -EINVAL; + + return ret; +} + +static int spdm_ctrl_init(struct tsm_spdm *spdm, struct spdm_ctrl *ctrl, + struct tsm_dsm_tio *dev_data) +{ + ctrl->req =3D dev_data->req; + ctrl->resp =3D dev_data->resp; + ctrl->scratch =3D dev_data->scratch; + ctrl->output =3D dev_data->output; + + spdm->req =3D sla_to_data(dev_data->reqbuf, SPDM_DOBJ_ID_REQ); + spdm->rsp =3D sla_to_data(dev_data->respbuf, SPDM_DOBJ_ID_RESP); + if (!spdm->req || !spdm->rsp) + return -EFAULT; + + return 0; +} + +static void spdm_ctrl_free(struct tsm_dsm_tio *dev_data, struct tsm_spdm *= spdm) +{ + struct sev_tio_status *tio_status =3D to_tio_status(dev_data); + size_t len =3D tio_status->spdm_req_size_max - + (sla_dobj_id_to_size(SPDM_DOBJ_ID_RESP) + + sizeof(struct sla_buffer_hdr)); + + sla_buffer_unmap(dev_data->resp, dev_data->respbuf); + sla_buffer_unmap(dev_data->req, dev_data->reqbuf); + spdm->rsp =3D NULL; + spdm->req =3D NULL; + sla_free(dev_data->req, len, true); + sla_free(dev_data->resp, len, false); + sla_free(dev_data->scratch, tio_status->spdm_scratch_size_max, true); + + dev_data->req.sla =3D 0; + dev_data->resp.sla =3D 0; + dev_data->scratch.sla =3D 0; + dev_data->respbuf =3D NULL; + dev_data->reqbuf =3D NULL; + sla_free(dev_data->output, tio_status->spdm_out_size_max, true); +} + +static int spdm_ctrl_alloc(struct tsm_dsm_tio *dev_data, struct tsm_spdm *= spdm) +{ + struct sev_tio_status *tio_status =3D to_tio_status(dev_data); + int ret; + + dev_data->req =3D sla_alloc(tio_status->spdm_req_size_max, true); + dev_data->resp =3D sla_alloc(tio_status->spdm_req_size_max, false); + dev_data->scratch_len =3D tio_status->spdm_scratch_size_max; + dev_data->scratch =3D sla_alloc(dev_data->scratch_len, true); + dev_data->output_len =3D tio_status->spdm_out_size_max; + dev_data->output =3D sla_alloc(dev_data->output_len, true); + + if (IS_SLA_NULL(dev_data->req) || IS_SLA_NULL(dev_data->resp) || + IS_SLA_NULL(dev_data->scratch) || IS_SLA_NULL(dev_data->dev_ctx)) { + ret =3D -ENOMEM; + goto free_spdm_exit; + } + + dev_data->reqbuf =3D sla_buffer_map(dev_data->req); + dev_data->respbuf =3D sla_buffer_map(dev_data->resp); + if (!dev_data->reqbuf || !dev_data->respbuf) { + ret =3D -EFAULT; + goto free_spdm_exit; + } + + dobj_response_init(dev_data->respbuf); + + return 0; + +free_spdm_exit: + spdm_ctrl_free(dev_data, spdm); + return ret; +} + +int sev_tio_init_locked(void *tio_status_page) +{ + struct sev_tio_status *tio_status =3D tio_status_page; + struct sev_data_tio_status data_status =3D { + .length =3D sizeof(data_status), + }; + int ret =3D 0, psp_ret =3D 0; + + data_status.status_paddr =3D __psp_pa(tio_status_page); + ret =3D __sev_do_cmd_locked(SEV_CMD_TIO_STATUS, &data_status, &psp_ret); + if (ret) + return ret; + + if (tio_status->length < offsetofend(struct sev_tio_status, tdictx_size) = || + tio_status->flags & 0xFFFFFF00) + return -EFAULT; + + if (!tio_status->tio_en && !tio_status->tio_init_done) + return -ENOENT; + + if (tio_status->tio_init_done) + return -EBUSY; + + struct sev_data_tio_init ti =3D { .length =3D sizeof(ti) }; + + ret =3D __sev_do_cmd_locked(SEV_CMD_TIO_INIT, &ti, &psp_ret); + if (ret) + return ret; + + ret =3D __sev_do_cmd_locked(SEV_CMD_TIO_STATUS, &data_status, &psp_ret); + if (ret) + return ret; + + return 0; +} + +int sev_tio_dev_create(struct tsm_dsm_tio *dev_data, u16 device_id, + u16 root_port_id, u8 segment_id) +{ + struct sev_tio_status *tio_status =3D to_tio_status(dev_data); + struct sev_data_tio_dev_create create =3D { + .length =3D sizeof(create), + .device_id =3D device_id, + .root_port_id =3D root_port_id, + .segment_id =3D segment_id, + }; + void *data_pg; + int ret; + + dev_data->dev_ctx =3D sla_alloc(tio_status->devctx_size, true); + if (IS_SLA_NULL(dev_data->dev_ctx)) + return -ENOMEM; + + data_pg =3D snp_alloc_firmware_page(GFP_KERNEL_ACCOUNT); + if (!data_pg) { + ret =3D -ENOMEM; + goto free_ctx_exit; + } + + create.dev_ctx_sla =3D dev_data->dev_ctx; + ret =3D sev_tio_do_cmd(SEV_CMD_TIO_DEV_CREATE, &create, sizeof(create), + &dev_data->psp_ret, dev_data, NULL); + if (ret) + goto free_data_pg_exit; + + dev_data->data_pg =3D data_pg; + + return ret; + +free_data_pg_exit: + snp_free_firmware_page(data_pg); +free_ctx_exit: + sla_free(create.dev_ctx_sla, tio_status->devctx_size, true); + return ret; +} + +int sev_tio_dev_reclaim(struct tsm_dsm_tio *dev_data, struct tsm_spdm *spd= m) +{ + struct sev_tio_status *tio_status =3D to_tio_status(dev_data); + struct sev_data_tio_dev_reclaim r =3D { + .length =3D sizeof(r), + .dev_ctx_sla =3D dev_data->dev_ctx, + }; + int ret; + + if (dev_data->data_pg) { + snp_free_firmware_page(dev_data->data_pg); + dev_data->data_pg =3D NULL; + } + + if (IS_SLA_NULL(dev_data->dev_ctx)) + return 0; + + ret =3D sev_do_cmd(SEV_CMD_TIO_DEV_RECLAIM, &r, &dev_data->psp_ret); + + sla_free(dev_data->dev_ctx, tio_status->devctx_size, true); + dev_data->dev_ctx =3D SLA_NULL; + + spdm_ctrl_free(dev_data, spdm); + + return ret; +} + +int sev_tio_dev_connect(struct tsm_dsm_tio *dev_data, u8 tc_mask, u8 ids[8= ], u8 cert_slot, + struct tsm_spdm *spdm) +{ + struct sev_data_tio_dev_connect connect =3D { + .length =3D sizeof(connect), + .tc_mask =3D tc_mask, + .cert_slot =3D cert_slot, + .dev_ctx_sla =3D dev_data->dev_ctx, + .ide_stream_id =3D { + ids[0], ids[1], ids[2], ids[3], + ids[4], ids[5], ids[6], ids[7] + }, + }; + int ret; + + if (WARN_ON(IS_SLA_NULL(dev_data->dev_ctx))) + return -EFAULT; + if (!(tc_mask & 1)) + return -EINVAL; + + ret =3D spdm_ctrl_alloc(dev_data, spdm); + if (ret) + return ret; + ret =3D spdm_ctrl_init(spdm, &connect.spdm_ctrl, dev_data); + if (ret) + return ret; + + ret =3D sev_tio_do_cmd(SEV_CMD_TIO_DEV_CONNECT, &connect, sizeof(connect), + &dev_data->psp_ret, dev_data, spdm); + + return ret; +} + +int sev_tio_dev_disconnect(struct tsm_dsm_tio *dev_data, struct tsm_spdm *= spdm, bool force) +{ + struct sev_data_tio_dev_disconnect dc =3D { + .length =3D sizeof(dc), + .dev_ctx_sla =3D dev_data->dev_ctx, + .force =3D force, + }; + int ret; + + if (WARN_ON_ONCE(IS_SLA_NULL(dev_data->dev_ctx))) + return -EFAULT; + + ret =3D spdm_ctrl_init(spdm, &dc.spdm_ctrl, dev_data); + if (ret) + return ret; + + ret =3D sev_tio_do_cmd(SEV_CMD_TIO_DEV_DISCONNECT, &dc, sizeof(dc), + &dev_data->psp_ret, dev_data, spdm); + + return ret; +} + +int sev_tio_asid_fence_clear(struct sla_addr_t dev_ctx, u64 gctx_paddr, in= t *psp_ret) +{ + struct sev_data_tio_asid_fence_clear c =3D { + .length =3D sizeof(c), + .dev_ctx_paddr =3D dev_ctx, + .gctx_paddr =3D gctx_paddr, + }; + + return sev_do_cmd(SEV_CMD_TIO_ASID_FENCE_CLEAR, &c, psp_ret); +} + +int sev_tio_asid_fence_status(struct tsm_dsm_tio *dev_data, u16 device_id,= u8 segment_id, + u32 asid, bool *fenced) +{ + u64 *status =3D prep_data_pg(u64, dev_data); + struct sev_data_tio_asid_fence_status s =3D { + .length =3D sizeof(s), + .dev_ctx_paddr =3D dev_data->dev_ctx, + .asid =3D asid, + .status_pa =3D __psp_pa(status), + }; + int ret; + + ret =3D sev_do_cmd(SEV_CMD_TIO_ASID_FENCE_STATUS, &s, &dev_data->psp_ret); + + if (ret =3D=3D SEV_RET_SUCCESS) { + u8 dma_status =3D *status & 0x3; + u8 mmio_status =3D (*status >> 2) & 0x3; + + switch (dma_status) { + case 0: + *fenced =3D false; + break; + case 1: + case 3: + *fenced =3D true; + break; + default: + pr_err("%04x:%x:%x.%d: undefined DMA fence state %#llx\n", + segment_id, PCI_BUS_NUM(device_id), + PCI_SLOT(device_id), PCI_FUNC(device_id), *status); + *fenced =3D true; + break; + } + + switch (mmio_status) { + case 0: + *fenced =3D false; + break; + case 3: + *fenced =3D true; + break; + default: + pr_err("%04x:%x:%x.%d: undefined MMIO fence state %#llx\n", + segment_id, PCI_BUS_NUM(device_id), + PCI_SLOT(device_id), PCI_FUNC(device_id), *status); + *fenced =3D true; + break; + } + } + + return ret; +} + +int sev_tio_cmd_buffer_len(int cmd) +{ + switch (cmd) { + case SEV_CMD_TIO_STATUS: return sizeof(struct sev_data_tio_status); + case SEV_CMD_TIO_INIT: return sizeof(struct sev_data_tio_init); + case SEV_CMD_TIO_DEV_CREATE: return sizeof(struct sev_data_tio_dev_creat= e); + case SEV_CMD_TIO_DEV_RECLAIM: return sizeof(struct sev_data_tio_dev_recl= aim); + case SEV_CMD_TIO_DEV_CONNECT: return sizeof(struct sev_data_tio_dev_conn= ect); + case SEV_CMD_TIO_DEV_DISCONNECT: return sizeof(struct sev_data_tio_dev_di= sconnect); + case SEV_CMD_TIO_ASID_FENCE_CLEAR: return sizeof(struct sev_data_tio_asid= _fence_clear); + case SEV_CMD_TIO_ASID_FENCE_STATUS: return sizeof(struct sev_data_tio_asi= d_fence_status); + default: return 0; + } +} diff --git a/drivers/crypto/ccp/sev-dev-tsm.c b/drivers/crypto/ccp/sev-dev-= tsm.c new file mode 100644 index 000000000000..4702139185a2 --- /dev/null +++ b/drivers/crypto/ccp/sev-dev-tsm.c @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0-only + +// Interface to CCP/SEV-TIO for generic PCIe TDISP module + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "psp-dev.h" +#include "sev-dev.h" +#include "sev-dev-tio.h" + +MODULE_IMPORT_NS("PCI_IDE"); + +#define TIO_DEFAULT_NR_IDE_STREAMS 1 + +static uint nr_ide_streams =3D TIO_DEFAULT_NR_IDE_STREAMS; +module_param_named(ide_nr, nr_ide_streams, uint, 0644); +MODULE_PARM_DESC(ide_nr, "Set the maximum number of IDE streams per PHB"); + +#define dev_to_sp(dev) ((struct sp_device *)dev_get_drvdata(dev)) +#define dev_to_psp(dev) ((struct psp_device *)(dev_to_sp(dev)->psp_data)) +#define dev_to_sev(dev) ((struct sev_device *)(dev_to_psp(dev)->sev_data)) +#define tsm_dev_to_sev(tsmdev) dev_to_sev((tsmdev)->dev.parent) +#define tsm_pf0_to_sev(t) tsm_dev_to_sev((t)->base.owner) + +/*to_pci_tsm_pf0((pdev)->tsm)*/ +#define pdev_to_tsm_pf0(pdev) (((pdev)->tsm && (pdev)->tsm->dsm_dev) ? \ + ((struct pci_tsm_pf0 *)((pdev)->tsm->dsm_dev->tsm)) : \ + NULL) + +#define tsm_pf0_to_data(t) (&(container_of((t), struct tio_dsm, tsm)->data= )) + +static int sev_tio_spdm_cmd(struct pci_tsm_pf0 *dsm, int ret) +{ + struct tsm_dsm_tio *dev_data =3D tsm_pf0_to_data(dsm); + struct tsm_spdm *spdm =3D &dsm->spdm; + struct pci_doe_mb *doe_mb; + + /* Check the main command handler response before entering the loop */ + if (ret =3D=3D 0 && dev_data->psp_ret !=3D SEV_RET_SUCCESS) + return -EINVAL; + else if (ret <=3D 0) + return ret; + + /* ret > 0 means "SPDM requested" */ + while (ret > 0) { + /* The proto can change at any point */ + if (ret =3D=3D TSM_PROTO_CMA_SPDM) { + doe_mb =3D dsm->doe_mb; + } else if (ret =3D=3D TSM_PROTO_SECURED_CMA_SPDM) { + doe_mb =3D dsm->doe_mb_sec; + } else { + ret =3D -EFAULT; + break; + } + + ret =3D pci_doe(doe_mb, PCI_VENDOR_ID_PCI_SIG, ret, + spdm->req, spdm->req_len, spdm->rsp, spdm->rsp_len); + if (ret < 0) + break; + + WARN_ON_ONCE(ret =3D=3D 0); /* The response should never be empty */ + spdm->rsp_len =3D ret; + ret =3D sev_tio_continue(dev_data, &dsm->spdm); + } + + return ret; +} + +static int stream_enable(struct pci_ide *ide) +{ + struct pci_dev *rp =3D pcie_find_root_port(ide->pdev); + int ret; + + ret =3D pci_ide_stream_enable(rp, ide); + if (!ret) + ret =3D pci_ide_stream_enable(ide->pdev, ide); + + if (ret) + pci_ide_stream_disable(rp, ide); + + return ret; +} + +static int streams_enable(struct pci_ide **ide) +{ + int ret =3D 0; + + for (int i =3D 0; i < TIO_IDE_MAX_TC; ++i) { + if (ide[i]) { + ret =3D stream_enable(ide[i]); + if (ret) + break; + } + } + + return ret; +} + +static void stream_disable(struct pci_ide *ide) +{ + pci_ide_stream_disable(ide->pdev, ide); + pci_ide_stream_disable(pcie_find_root_port(ide->pdev), ide); +} + +static void streams_disable(struct pci_ide **ide) +{ + for (int i =3D 0; i < TIO_IDE_MAX_TC; ++i) + if (ide[i]) + stream_disable(ide[i]); +} + +static void stream_setup(struct pci_ide *ide) +{ + struct pci_dev *rp =3D pcie_find_root_port(ide->pdev); + + ide->partner[PCI_IDE_EP].rid_start =3D 0; + ide->partner[PCI_IDE_EP].rid_end =3D 0xffff; + ide->partner[PCI_IDE_RP].rid_start =3D 0; + ide->partner[PCI_IDE_RP].rid_end =3D 0xffff; + + ide->pdev->ide_cfg =3D 0; + ide->pdev->ide_tee_limit =3D 1; + rp->ide_cfg =3D 1; + rp->ide_tee_limit =3D 0; + + pci_warn(ide->pdev, "Forcing CFG/TEE for %s", pci_name(rp)); + pci_ide_stream_setup(ide->pdev, ide); + pci_ide_stream_setup(rp, ide); +} + +static u8 streams_setup(struct pci_ide **ide, u8 *ids) +{ + bool def =3D false; + u8 tc_mask =3D 0; + int i; + + for (i =3D 0; i < TIO_IDE_MAX_TC; ++i) { + if (!ide[i]) { + ids[i] =3D 0xFF; + continue; + } + + tc_mask |=3D 1 << i; + ids[i] =3D ide[i]->stream_id; + + if (!def) { + struct pci_ide_partner *settings; + + settings =3D pci_ide_to_settings(ide[i]->pdev, ide[i]); + settings->default_stream =3D 1; + def =3D true; + } + + stream_setup(ide[i]); + } + + return tc_mask; +} + +static int streams_register(struct pci_ide **ide) +{ + int ret =3D 0, i; + + for (i =3D 0; i < TIO_IDE_MAX_TC; ++i) { + if (!ide[i]) + continue; + + ret =3D pci_ide_stream_register(ide[i]); + if (ret) + break; + } + + return ret; +} + +static void streams_unregister(struct pci_ide **ide) +{ + for (int i =3D 0; i < TIO_IDE_MAX_TC; ++i) + if (ide[i]) + pci_ide_stream_unregister(ide[i]); +} + +static void stream_teardown(struct pci_ide *ide) +{ + pci_ide_stream_teardown(ide->pdev, ide); + pci_ide_stream_teardown(pcie_find_root_port(ide->pdev), ide); +} + +static void streams_teardown(struct pci_ide **ide) +{ + for (int i =3D 0; i < TIO_IDE_MAX_TC; ++i) { + if (ide[i]) { + stream_teardown(ide[i]); + pci_ide_stream_free(ide[i]); + ide[i] =3D NULL; + } + } +} + +static int stream_alloc(struct pci_dev *pdev, struct tsm_dsm_tio *dev_data, + unsigned int tc) +{ + struct pci_dev *rp =3D pcie_find_root_port(pdev); + struct pci_ide *ide; + + if (dev_data->ide[tc]) { + pci_err(pdev, "Stream for class=3D%d already registered", tc); + return -EBUSY; + } + + /* FIXME: find a better way */ + if (nr_ide_streams !=3D TIO_DEFAULT_NR_IDE_STREAMS) + pci_notice(pdev, "Enable non-default %d streams", nr_ide_streams); + pci_ide_set_nr_streams(to_pci_host_bridge(rp->bus->bridge), nr_ide_stream= s); + + ide =3D pci_ide_stream_alloc(pdev); + if (!ide) + return -EFAULT; + + /* Blindly assign streamid=3D0 to TC=3D0, and so on */ + ide->stream_id =3D tc; + + dev_data->ide[tc] =3D ide; + + return 0; +} + +static struct pci_tsm *tio_pf0_probe(struct pci_dev *pdev, struct sev_devi= ce *sev) +{ + struct tio_dsm *dsm __free(kfree) =3D kzalloc(sizeof(*dsm), GFP_KERNEL); + int rc; + + if (!dsm) + return NULL; + + rc =3D pci_tsm_pf0_constructor(pdev, &dsm->tsm, sev->tsmdev); + if (rc) + return NULL; + + pci_dbg(pdev, "TSM enabled\n"); + dsm->sev =3D sev; + return &no_free_ptr(dsm)->tsm.base_tsm; +} + +static struct pci_tsm *dsm_probe(struct tsm_dev *tsmdev, struct pci_dev *p= dev) +{ + struct sev_device *sev =3D tsm_dev_to_sev(tsmdev); + + if (is_pci_tsm_pf0(pdev)) + return tio_pf0_probe(pdev, sev); + return 0; +} + +static void dsm_remove(struct pci_tsm *tsm) +{ + struct pci_dev *pdev =3D tsm->pdev; + + pci_dbg(pdev, "TSM disabled\n"); + + if (is_pci_tsm_pf0(pdev)) { + struct tio_dsm *dsm =3D container_of(tsm, struct tio_dsm, tsm.base_tsm); + + pci_tsm_pf0_destructor(&dsm->tsm); + kfree(dsm); + } +} + +static int dsm_create(struct pci_tsm_pf0 *dsm) +{ + struct pci_dev *pdev =3D dsm->base_tsm.pdev; + u8 segment_id =3D pdev->bus ? pci_domain_nr(pdev->bus) : 0; + struct pci_dev *rootport =3D pcie_find_root_port(pdev); + u16 device_id =3D pci_dev_id(pdev); + struct tsm_dsm_tio *dev_data =3D tsm_pf0_to_data(dsm); + struct page *req_page; + u16 root_port_id; + u32 lnkcap =3D 0; + int ret; + + if (pci_read_config_dword(rootport, pci_pcie_cap(rootport) + PCI_EXP_LNKC= AP, + &lnkcap)) + return -ENODEV; + + root_port_id =3D FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); + + req_page =3D alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); + if (!req_page) + return -ENOMEM; + + ret =3D sev_tio_dev_create(dev_data, device_id, root_port_id, segment_id); + if (ret) + goto free_resp_exit; + + return 0; + +free_resp_exit: + __free_page(req_page); + return ret; +} + +static int dsm_connect(struct pci_dev *pdev) +{ + struct pci_tsm_pf0 *dsm =3D pdev_to_tsm_pf0(pdev); + struct tsm_dsm_tio *dev_data =3D tsm_pf0_to_data(dsm); + u8 ids[TIO_IDE_MAX_TC]; + u8 tc_mask; + int ret; + + ret =3D stream_alloc(pdev, dev_data, 0); + if (ret) + return ret; + + ret =3D dsm_create(dsm); + if (ret) + goto ide_free_exit; + + tc_mask =3D streams_setup(dev_data->ide, ids); + + ret =3D sev_tio_dev_connect(dev_data, tc_mask, ids, dsm->cert_slot, &dsm-= >spdm); + ret =3D sev_tio_spdm_cmd(dsm, ret); + if (ret) + goto free_exit; + + streams_enable(dev_data->ide); + + ret =3D streams_register(dev_data->ide); + if (ret) + goto free_exit; + + return 0; + +free_exit: + sev_tio_dev_reclaim(dev_data, &dsm->spdm); + + streams_disable(dev_data->ide); +ide_free_exit: + + streams_teardown(dev_data->ide); + + if (ret > 0) + ret =3D -EFAULT; + return ret; +} + +static void dsm_disconnect(struct pci_dev *pdev) +{ + bool force =3D SYSTEM_HALT <=3D system_state && system_state <=3D SYSTEM_= RESTART; + struct pci_tsm_pf0 *dsm =3D pdev_to_tsm_pf0(pdev); + struct tsm_dsm_tio *dev_data =3D tsm_pf0_to_data(dsm); + int ret; + + ret =3D sev_tio_dev_disconnect(dev_data, &dsm->spdm, force); + ret =3D sev_tio_spdm_cmd(dsm, ret); + if (ret && !force) { + ret =3D sev_tio_dev_disconnect(dev_data, &dsm->spdm, true); + sev_tio_spdm_cmd(dsm, ret); + } + + sev_tio_dev_reclaim(dev_data, &dsm->spdm); + + streams_disable(dev_data->ide); + streams_unregister(dev_data->ide); + streams_teardown(dev_data->ide); +} + +static struct pci_tsm_ops sev_tsm_ops =3D { + .probe =3D dsm_probe, + .remove =3D dsm_remove, + .connect =3D dsm_connect, + .disconnect =3D dsm_disconnect, +}; + +void sev_tsm_init_locked(struct sev_device *sev, void *tio_status_page) +{ + struct sev_tio_status *t __free(kfree) =3D kzalloc(sizeof(*t), GFP_KERNEL= ); + struct tsm_dev *tsmdev; + int ret; + + WARN_ON(sev->tio_status); + + if (!t) + return; + + ret =3D sev_tio_init_locked(tio_status_page); + if (ret) { + pr_warn("SEV-TIO STATUS failed with %d\n", ret); + goto error_exit; + } + + tsmdev =3D tsm_register(sev->dev, &sev_tsm_ops); + if (IS_ERR(tsmdev)) + goto error_exit; + + memcpy(t, tio_status_page, sizeof(*t)); + + pr_notice("SEV-TIO status: EN=3D%d INIT_DONE=3D%d rq=3D%d..%d rs=3D%d..%d= " + "scr=3D%d..%d out=3D%d..%d dev=3D%d tdi=3D%d algos=3D%x\n", + t->tio_en, t->tio_init_done, + t->spdm_req_size_min, t->spdm_req_size_max, + t->spdm_rsp_size_min, t->spdm_rsp_size_max, + t->spdm_scratch_size_min, t->spdm_scratch_size_max, + t->spdm_out_size_min, t->spdm_out_size_max, + t->devctx_size, t->tdictx_size, + t->tio_crypto_alg); + + sev->tsmdev =3D tsmdev; + sev->tio_status =3D no_free_ptr(t); + + return; + +error_exit: + pr_err("Failed to enable SEV-TIO: ret=3D%d en=3D%d initdone=3D%d SEV=3D%d= \n", + ret, t->tio_en, t->tio_init_done, + boot_cpu_has(X86_FEATURE_SEV)); + pr_err("Check BIOS for: SMEE, SEV Control, SEV-ES ASID Space Limit=3D99,\= n" + "SNP Memory (RMP Table) Coverage, RMP Coverage for 64Bit MMIO Rang= es\n" + "SEV-SNP Support, SEV-TIO Support, PCIE IDE Capability\n"); +} + +void sev_tsm_uninit(struct sev_device *sev) +{ + if (sev->tsmdev) + tsm_unregister(sev->tsmdev); + + sev->tsmdev =3D NULL; +} diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 2f1c9614d359..365867f381e9 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -38,6 +38,7 @@ =20 #include "psp-dev.h" #include "sev-dev.h" +#include "sev-dev-tio.h" =20 #define DEVICE_NAME "sev" #define SEV_FW_FILE "amd/sev.fw" @@ -75,6 +76,12 @@ static bool psp_init_on_probe =3D true; module_param(psp_init_on_probe, bool, 0444); MODULE_PARM_DESC(psp_init_on_probe, " if true, the PSP will be initialize= d on module init. Else the PSP will be initialized on the first command req= uiring it"); =20 +#if defined(CONFIG_PCI_TSM) +static bool sev_tio_enabled =3D true; +module_param_named(tio, sev_tio_enabled, bool, 0444); +MODULE_PARM_DESC(tio, "Enables TIO in SNP_INIT_EX"); +#endif + MODULE_FIRMWARE("amd/amd_sev_fam17h_model0xh.sbin"); /* 1st gen EPYC */ MODULE_FIRMWARE("amd/amd_sev_fam17h_model3xh.sbin"); /* 2nd gen EPYC */ MODULE_FIRMWARE("amd/amd_sev_fam19h_model0xh.sbin"); /* 3rd gen EPYC */ @@ -251,7 +258,7 @@ static int sev_cmd_buffer_len(int cmd) case SEV_CMD_SNP_COMMIT: return sizeof(struct sev_data_snp_commit); case SEV_CMD_SNP_FEATURE_INFO: return sizeof(struct sev_data_snp_feature= _info); case SEV_CMD_SNP_VLEK_LOAD: return sizeof(struct sev_user_data_snp_vlek_= load); - default: return 0; + default: return sev_tio_cmd_buffer_len(cmd); } =20 return 0; @@ -1439,8 +1446,14 @@ static int __sev_snp_init_locked(int *error, unsigne= d int max_snp_asid) data.init_rmp =3D 1; data.list_paddr_en =3D 1; data.list_paddr =3D __psp_pa(snp_range_list); + +#if defined(CONFIG_PCI_TSM) data.tio_en =3D sev_tio_present(sev) && + sev_tio_enabled && psp_init_on_probe && amd_iommu_sev_tio_supported(); + if (sev_tio_present(sev) && !psp_init_on_probe) + dev_warn(sev->dev, "SEV-TIO as incompatible with psp_init_on_probe=3D0\= n"); +#endif cmd =3D SEV_CMD_SNP_INIT_EX; } else { cmd =3D SEV_CMD_SNP_INIT; @@ -1487,6 +1500,24 @@ static int __sev_snp_init_locked(int *error, unsigne= d int max_snp_asid) atomic_notifier_chain_register(&panic_notifier_list, &snp_panic_notifier); =20 +#if defined(CONFIG_PCI_TSM) + if (data.tio_en) { + /* + * This executes with the sev_cmd_mutex held so down the stack + * snp_reclaim_pages(locked=3Dfalse) might be needed (which is extremely + * unlikely) but will cause a deadlock. + * Instead of exporting __snp_alloc_firmware_pages(), allocate a page + * for this one call here. + */ + void *tio_status =3D page_address(__snp_alloc_firmware_pages( + GFP_KERNEL_ACCOUNT | __GFP_ZERO, 0, true)); + + if (tio_status) { + sev_tsm_init_locked(sev, tio_status); + __snp_free_firmware_pages(virt_to_page(tio_status), 0, true); + } + } +#endif sev_es_tmr_size =3D SNP_TMR_SIZE; =20 return 0; @@ -2766,7 +2797,22 @@ static void __sev_firmware_shutdown(struct sev_devic= e *sev, bool panic) =20 static void sev_firmware_shutdown(struct sev_device *sev) { +#if defined(CONFIG_PCI_TSM) + /* + * Calling without sev_cmd_mutex held as TSM will likely try disconnecting + * IDE and this ends up calling sev_do_cmd() which locks sev_cmd_mutex. + */ + if (sev->tio_status) + sev_tsm_uninit(sev); +#endif + mutex_lock(&sev_cmd_mutex); + +#if defined(CONFIG_PCI_TSM) + kfree(sev->tio_status); + sev->tio_status =3D NULL; +#endif + __sev_firmware_shutdown(sev, false); mutex_unlock(&sev_cmd_mutex); } --=20 2.51.0