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Mon, 10 Nov 2025 12:42:00 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v6 RESEND 4/7] rust: io: factor common I/O helpers into Io trait Date: Mon, 10 Nov 2025 22:41:16 +0200 Message-ID: <20251110204119.18351-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251110204119.18351-1-zhiw@nvidia.com> References: <20251110204119.18351-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EB:EE_|IA0PR12MB8696:EE_ X-MS-Office365-Filtering-Correlation-Id: f22b7e33-63d1-46ec-7618-08de2099ab98 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DM7ypbq+YIikNocbPBfpbOONoHQo3BajZNQ38H4bv5l97Kn/aHtgVvt2+4BF?= =?us-ascii?Q?5l7HOv2Zj7ewHUT5E24IhnDp8E/XjSmBu+t0U7RPUfPlq5xTm/ghc7YusZPK?= =?us-ascii?Q?WNEUWK+dUUtiaxTy/XD697haFGZ1HqgmGOxFhQEcT6sg3D6NtMeH2y1Vk0UH?= =?us-ascii?Q?CVwHFFO9s2Zi7vyjiAMsvmp8FznomNUZnZihqFpenj2eWYCEifB/Ik97q9L6?= =?us-ascii?Q?VM6TnMw1d/0rPRJIXtonwVp84q5EUIxs15hrBXlAdkIynG6fB1AkqjJw7Zqz?= =?us-ascii?Q?INfPaK28pddp69s31wQUCt/0BEi1DANMLne092Qp/RyE5p4tiCiz1xT4fHFq?= =?us-ascii?Q?tGeMB5mwvUWEUuOr90DD32DNmgqakBEAqZprrtVCk/Ws9kCwuSSJkx6MPxEr?= =?us-ascii?Q?kAfP6tDXWA/XQplN0ZL/CTqwwVYtAzcuc5RcpIa0SA2naER1oa9pVrhPVuox?= =?us-ascii?Q?K7Ya4DzRcfXau0+fSa5r8MY1vHtpv6yMfQPMlmM9NeegQTe1bxaFTCtwDr3W?= =?us-ascii?Q?5FMkL3DGe5d5p2zIFP6gwwLLtyAz2cqoybRojRG1ahRZSemztJUJFhMH+Tep?= =?us-ascii?Q?gc611Pv+atCKVr0X169RBekNabB/A4W1XKpa9gsm07I1pN//xKi7LANRetpW?= =?us-ascii?Q?MhzSkn5SUMU0vlhWFcMKMcwNydbTJ0h9nr9tdcw1nrkxhoKAeEmYUrV0KEpu?= =?us-ascii?Q?qwySYE/BqWEjRE1smOc53evF3IGYeV7xuE3hkp6fv+v5rNXzNQNy4xCWebpq?= =?us-ascii?Q?ViIQVC4F4HlJh188IYHP9e1gSG++14aqxOWGXliWc/IVSPyMOYl13TwiJ5j1?= =?us-ascii?Q?Uqza0L9P26S5fgTpT4Bz44JDJ8ggONQGslMs2Wffsnu/xIwMXci3vs5IcXiw?= =?us-ascii?Q?d6T/WyPRLq7Tu8I98N98da13E/bQcMJyEVBptRUp6QofsNGfEN8voDNYn/p4?= =?us-ascii?Q?mrrnYtGKZC63ahkzLFTz0hERWmODUNXv9NmOuOddjdVJl6Ra2bcvojNT2O9t?= =?us-ascii?Q?2dG93AKU58MBdEs90Qmj29DGIX8IOh/0f4XW26Uzj7DJkwUwT8Agd1qITx8k?= =?us-ascii?Q?E2rc3l5BVASJ51Fuir6IddGvnNsXcq6H5pk00bK+yKhEX+Sgmr7GHFRIm/CY?= =?us-ascii?Q?1Jr0TCQx9hldz32rAyZgW7qANc/G0F0Ej07YS7BBc2vPHlO3WKLP4/k8E56g?= =?us-ascii?Q?Vv6vunLmZz3h9/2bwoiAlw2arPddA9lxuZSGo56hYmTogxOXeb1WFbKTU4EB?= =?us-ascii?Q?70dKUECFN8kl08QsfkQTgLrvYH0nRkP+oDCex7/XSE/eVXGOZtilpeHx/eL9?= =?us-ascii?Q?bk0OYN8DZI+CBVhOG9R0c/VKAmT+CjguoPi+zV2Pt4HSU1X17zSrbJXv1RWN?= =?us-ascii?Q?LrFgoX1wi36kdrsvI3kckIf0VGoTn64wcrDLZNhJelhbQrYfd24MofU7Vbk3?= =?us-ascii?Q?DpX1d5mKXxXvxfPZ84r7bTCheijvSoARWHXZfGIWWlh0t5TaPDarkONr3oLU?= =?us-ascii?Q?OJuY6aYxn3IM1WC6KPtkDD6B1Cjzw1bO4aeotYPEfxz60LMi/n1DwGGsTKI6?= =?us-ascii?Q?4bBWvVlWvm3wsw20Mac=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2025 20:42:31.3227 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f22b7e33-63d1-46ec-7618-08de2099ab98 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8696 Content-Type: text/plain; charset="utf-8" The previous Io type combined both the generic I/O access helpers and MMIO implementation details in a single struct. To establish a cleaner layering between the I/O interface and its concrete backends, paving the way for supporting additional I/O mechanisms in the future, Io need to be factored. Factor the common helpers into a new Io trait, and move the MMIO-specific logic into a dedicated Mmio type implementing that trait. Rename the IoRaw to MmioRaw and update the bus MMIO implementations to use MmioRaw. No functional change intended. Cc: Alexandre Courbot Cc: Bjorn Helgaas Cc: Danilo Krummrich Cc: John Hubbard Signed-off-by: Zhi Wang Reviewed-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 90 +++++---- drivers/gpu/nova-core/vbios.rs | 1 + rust/kernel/devres.rs | 14 +- rust/kernel/io.rs | 264 ++++++++++++++++++++------- rust/kernel/io/mem.rs | 16 +- rust/kernel/io/poll.rs | 8 +- rust/kernel/pci/io.rs | 12 +- samples/rust/rust_driver_pci.rs | 2 + 8 files changed, 277 insertions(+), 130 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 8058e1696df9..39b1069a3429 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -608,16 +608,18 @@ impl $name { =20 /// Read the register from its address in `io`. #[inline(always)] - pub(crate) fn read(io: &T) -> Self where - T: ::core::ops::Deref>, + pub(crate) fn read(io: &T) -> Self where + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { Self(io.read32($offset)) } =20 /// Write the value contained in `self` to the register addres= s in `io`. #[inline(always)] - pub(crate) fn write(self, io: &T) where - T: ::core::ops::Deref>, + pub(crate) fn write(self, io: &T) where + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { io.write32(self.0, $offset) } @@ -625,11 +627,12 @@ pub(crate) fn write(self, io: &= T) where /// Read the register from its address in `io` and run `f` on = its value to obtain a new /// value to write back. #[inline(always)] - pub(crate) fn alter( + pub(crate) fn alter( io: &T, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io)); @@ -647,12 +650,13 @@ impl $name { /// Read the register from `io`, using the base address provid= ed by `base` and adding /// the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, #[allow(unused_variables)] base: &B, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -667,13 +671,14 @@ pub(crate) fn read( /// Write the value contained in `self` to `io`, using the bas= e address provided by /// `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, #[allow(unused_variables)] base: &B, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -688,12 +693,13 @@ pub(crate) fn write( /// the register's offset to it, then run `f` on its value to = obtain a new value to /// write back. #[inline(always)] - pub(crate) fn alter( + pub(crate) fn alter( io: &T, base: &B, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -713,11 +719,12 @@ impl $name { =20 /// Read the array register at index `idx` from its address in= `io`. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { build_assert!(idx < Self::SIZE); =20 @@ -729,12 +736,13 @@ pub(crate) fn read( =20 /// Write the value contained in `self` to the array register = with index `idx` in `io`. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { build_assert!(idx < Self::SIZE); =20 @@ -746,12 +754,13 @@ pub(crate) fn write( /// Read the array register at index `idx` in `io` and run `f`= on its value to obtain a /// new value to write back. #[inline(always)] - pub(crate) fn alter( + pub(crate) fn alter( io: &T, idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io, idx)); @@ -763,11 +772,12 @@ pub(crate) fn alter( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_read( + pub(crate) fn try_read( io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { if idx < Self::SIZE { Ok(Self::read(io, idx)) @@ -781,12 +791,13 @@ pub(crate) fn try_read( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_write( + pub(crate) fn try_write( self, io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { if idx < Self::SIZE { Ok(self.write(io, idx)) @@ -801,12 +812,13 @@ pub(crate) fn try_write( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_alter( + pub(crate) fn try_alter( io: &T, idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, F: ::core::ops::FnOnce(Self) -> Self, { if idx < Self::SIZE { @@ -832,13 +844,14 @@ impl $name { /// Read the array register at index `idx` from `io`, using th= e base address provided /// by `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, #[allow(unused_variables)] base: &B, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -853,14 +866,15 @@ pub(crate) fn read( /// Write the value contained in `self` to `io`, using the bas= e address provided by /// `base` and adding the offset of array register `idx` to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, #[allow(unused_variables)] base: &B, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -875,13 +889,14 @@ pub(crate) fn write( /// by `base` and adding the register's offset to it, then run= `f` on its value to /// obtain a new value to write back. #[inline(always)] - pub(crate) fn alter( + pub(crate) fn alter( io: &T, base: &B, idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -895,12 +910,13 @@ pub(crate) fn alter( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_read( + pub(crate) fn try_read( io: &T, base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -916,13 +932,14 @@ pub(crate) fn try_read( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_write( + pub(crate) fn try_write( self, io: &T, base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -939,13 +956,14 @@ pub(crate) fn try_write( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_alter( + pub(crate) fn try_alter( io: &T, base: &B, idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs index 71fbe71b84db..7a0121ab9b09 100644 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@ -8,6 +8,7 @@ use core::convert::TryFrom; use kernel::device; use kernel::error::Result; +use kernel::io::IoFallible; use kernel::prelude::*; use kernel::ptr::{Alignable, Alignment}; use kernel::types::ARef; diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs index 3376c7090ccd..1dc7cb30d9f2 100644 --- a/rust/kernel/devres.rs +++ b/rust/kernel/devres.rs @@ -75,14 +75,15 @@ struct Inner { /// # }, /// # devres::Devres, /// # io::{ -/// # Io, -/// # IoRaw, // +/// # IoInfallible, +/// # Mmio, +/// # MmioRaw, // /// # }, // /// # }; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -97,7 +98,7 @@ struct Inner { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -109,11 +110,11 @@ struct Inner { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// # fn no_run(dev: &Device) -> Result<(), Error> { @@ -259,6 +260,7 @@ pub fn device(&self) -> &Device { /// # use kernel::{ /// # device::Core, /// # devres::Devres, + /// # io::IoInfallible, /// # pci, // /// # }; /// diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 5af04c3b807b..4d98d431b523 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -20,16 +20,16 @@ /// By itself, the existence of an instance of this structure does not pro= vide any guarantees that /// the represented MMIO region does exist or is properly mapped. /// -/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an `Io` -/// instance providing the actual memory accessors. Only by the conversion= into an `Io` structure -/// any guarantees are given. -pub struct IoRaw { +/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an +/// `Mmio` instance providing the actual memory accessors. Only by the con= version into an `Mmio` +/// structure any guarantees are given. +pub struct MmioRaw { addr: usize, maxsize: usize, } =20 -impl IoRaw { - /// Returns a new `IoRaw` instance on success, an error otherwise. +impl MmioRaw { + /// Returns a new `MmioRaw` instance on success, an error otherwise. pub fn new(addr: usize, maxsize: usize) -> Result { if maxsize < SIZE { return Err(EINVAL); @@ -68,14 +68,16 @@ pub fn maxsize(&self) -> usize { /// # bindings, /// # ffi::c_void, /// # io::{ -/// # Io, -/// # IoRaw, // +/// # IoFallible, +/// # IoInfallible, +/// # Mmio, +/// # MmioRaw, // /// # }, // /// # }; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -90,7 +92,7 @@ pub fn maxsize(&self) -> usize { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -102,11 +104,11 @@ pub fn maxsize(&self) -> usize { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// @@ -120,29 +122,31 @@ pub fn maxsize(&self) -> usize { /// # } /// ``` #[repr(transparent)] -pub struct Io(IoRaw); +pub struct Mmio(MmioRaw); =20 macro_rules! define_read { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_= name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident -> $t= ype_name:ty) =3D> { /// Read IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile /// time, the build will fail. $(#[$attr])* #[inline] - pub fn $name(&self, offset: usize) -> $type_name { + $vis fn $name(&self, offset: usize) -> $type_name { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. unsafe { bindings::$c_fn(addr as *const c_void) } } + }; =20 + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident -> = $type_name:ty) =3D> { /// Read IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is /// out of bounds. $(#[$attr])* - pub fn $try_name(&self, offset: usize) -> Result<$type_name> { + $vis fn $try_name(&self, offset: usize) -> Result<$type_name> { let addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. @@ -152,26 +156,28 @@ pub fn $try_name(&self, offset: usize) -> Result<$typ= e_name> { } =20 macro_rules! define_write { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_= name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident <- $t= ype_name:ty) =3D> { /// Write IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile /// time, the build will fail. $(#[$attr])* #[inline] - pub fn $name(&self, value: $type_name, offset: usize) { + $vis fn $name(&self, value: $type_name, offset: usize) { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. unsafe { bindings::$c_fn(value, addr as *mut c_void) } } + }; =20 + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident <- = $type_name:ty) =3D> { /// Write IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is /// out of bounds. $(#[$attr])* - pub fn $try_name(&self, value: $type_name, offset: usize) -> Resul= t { + $vis fn $try_name(&self, value: $type_name, offset: usize) -> Resu= lt { let addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. @@ -181,43 +187,38 @@ pub fn $try_name(&self, value: $type_name, offset: us= ize) -> Result { }; } =20 -impl Io { - /// Converts an `IoRaw` into an `Io` instance, providing the accessors= to the MMIO mapping. - /// - /// # Safety - /// - /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size - /// `maxsize`. - pub unsafe fn from_raw(raw: &IoRaw) -> &Self { - // SAFETY: `Io` is a transparent wrapper around `IoRaw`. - unsafe { &*core::ptr::from_ref(raw).cast() } +/// Checks whether an access of type `U` at the given `offset` +/// is valid within this region. +#[inline] +const fn offset_valid(offset: usize, size: usize) -> bool { + let type_size =3D core::mem::size_of::(); + if let Some(end) =3D offset.checked_add(type_size) { + end <=3D size && offset % type_size =3D=3D 0 + } else { + false } +} + +/// Represents a region of I/O space of a fixed size. +/// +/// Provides common helpers for offset validation and address +/// calculation on top of a base address and maximum size. +/// +pub trait Io { + /// Minimum usable size of this region. + const MIN_SIZE: usize; =20 /// Returns the base address of this mapping. - #[inline] - pub fn addr(&self) -> usize { - self.0.addr() - } + fn addr(&self) -> usize; =20 /// Returns the maximum size of this mapping. - #[inline] - pub fn maxsize(&self) -> usize { - self.0.maxsize() - } - - #[inline] - const fn offset_valid(offset: usize, size: usize) -> bool { - let type_size =3D core::mem::size_of::(); - if let Some(end) =3D offset.checked_add(type_size) { - end <=3D size && offset % type_size =3D=3D 0 - } else { - false - } - } + fn maxsize(&self) -> usize; =20 + /// Returns the absolute I/O address for a given `offset`, + /// performing runtime bound checks. #[inline] fn io_addr(&self, offset: usize) -> Result { - if !Self::offset_valid::(offset, self.maxsize()) { + if !offset_valid::(offset, self.maxsize()) { return Err(EINVAL); } =20 @@ -226,50 +227,173 @@ fn io_addr(&self, offset: usize) -> Result= { self.addr().checked_add(offset).ok_or(EINVAL) } =20 + /// Returns the absolute I/O address for a given `offset`, + /// performing compile-time bound checks. #[inline] fn io_addr_assert(&self, offset: usize) -> usize { - build_assert!(Self::offset_valid::(offset, SIZE)); + build_assert!(offset_valid::(offset, Self::MIN_SIZE)); =20 self.addr() + offset } +} + +/// Types implementing this trait (e.g. MMIO BARs or PCI config +/// regions) can share the same Infallible accessors. +pub trait IoInfallible: Io { + /// Infallible 8-bit read with compile-time bounds check. + fn read8(&self, offset: usize) -> u8; + + /// Infallible 16-bit read with compile-time bounds check. + fn read16(&self, offset: usize) -> u16; + + /// Infallible 32-bit read with compile-time bounds check. + fn read32(&self, offset: usize) -> u32; + + /// Infallible 8-bit write with compile-time bounds check. + fn write8(&self, value: u8, offset: usize); + + /// Infallible 16-bit write with compile-time bounds check. + fn write16(&self, value: u16, offset: usize); + + /// Infallible 32-bit write with compile-time bounds check. + fn write32(&self, value: u32, offset: usize); +} + +/// Types implementing this trait (e.g. MMIO BARs or PCI config +/// regions) can share the same Fallible accessors. +pub trait IoFallible: Io { + /// Fallible 8-bit read with runtime bounds check. + fn try_read8(&self, offset: usize) -> Result; + + /// Fallible 16-bit read with runtime bounds check. + fn try_read16(&self, offset: usize) -> Result; + + /// Fallible 32-bit read with runtime bounds check. + fn try_read32(&self, offset: usize) -> Result; + + /// Fallible 8-bit write with runtime bounds check. + fn try_write8(&self, value: u8, offset: usize) -> Result; + + /// Fallible 16-bit write with runtime bounds check. + fn try_write16(&self, value: u16, offset: usize) -> Result; + + /// Fallible 32-bit write with runtime bounds check. + fn try_write32(&self, value: u32, offset: usize) -> Result; +} + +impl Io for Mmio { + const MIN_SIZE: usize =3D SIZE; + + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + self.0.addr() + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.0.maxsize() + } +} + +impl IoInfallible for Mmio { + define_read!(infallible, read8, readb -> u8); + define_read!(infallible, read16, readw -> u16); + define_read!(infallible, read32, readl -> u32); + + define_write!(infallible, write8, writeb <- u8); + define_write!(infallible, write16, writew <- u16); + define_write!(infallible, write32, writel <- u32); +} + +impl IoFallible for Mmio { + define_read!(fallible, try_read8, readb -> u8); + define_read!(fallible, try_read16, readw -> u16); + define_read!(fallible, try_read32, readl -> u32); + + define_write!(fallible, try_write8, writeb <- u8); + define_write!(fallible, try_write16, writew <- u16); + define_write!(fallible, try_write32, writel <- u32); +} + +impl Mmio { + /// Converts an `MmioRaw` into an `Mmio` instance, providing the acces= sors to the MMIO mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size + /// `maxsize`. + pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { + // SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`. + unsafe { &*core::ptr::from_ref(raw).cast() } + } =20 - define_read!(read8, try_read8, readb -> u8); - define_read!(read16, try_read16, readw -> u16); - define_read!(read32, try_read32, readl -> u32); define_read!( + infallible, #[cfg(CONFIG_64BIT)] - read64, - try_read64, + pub read64, readq -> u64 ); =20 - define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8); - define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16); - define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32); + define_write!( + infallible, + #[cfg(CONFIG_64BIT)] + pub write64, + writeq <- u64 + ); + define_read!( + fallible, #[cfg(CONFIG_64BIT)] - read64_relaxed, - try_read64_relaxed, - readq_relaxed -> u64 + pub try_read64, + readq -> u64 ); =20 - define_write!(write8, try_write8, writeb <- u8); - define_write!(write16, try_write16, writew <- u16); - define_write!(write32, try_write32, writel <- u32); define_write!( + fallible, #[cfg(CONFIG_64BIT)] - write64, - try_write64, + pub try_write64, writeq <- u64 ); =20 - define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8= ); - define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- = u16); - define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- = u32); + define_read!(infallible, pub read8_relaxed, readb_relaxed -> u8); + define_read!(infallible, pub read16_relaxed, readw_relaxed -> u16); + define_read!(infallible, pub read32_relaxed, readl_relaxed -> u32); + define_read!( + infallible, + #[cfg(CONFIG_64BIT)] + pub read64_relaxed, + readq_relaxed -> u64 + ); + + define_read!(fallible, pub try_read8_relaxed, readb_relaxed -> u8); + define_read!(fallible, pub try_read16_relaxed, readw_relaxed -> u16); + define_read!(fallible, pub try_read32_relaxed, readl_relaxed -> u32); + define_read!( + fallible, + #[cfg(CONFIG_64BIT)] + pub try_read64_relaxed, + readq_relaxed -> u64 + ); + + define_write!(infallible, pub write8_relaxed, writeb_relaxed <- u8); + define_write!(infallible, pub write16_relaxed, writew_relaxed <- u16); + define_write!(infallible, pub write32_relaxed, writel_relaxed <- u32); + define_write!( + infallible, + #[cfg(CONFIG_64BIT)] + pub write64_relaxed, + writeq_relaxed <- u64 + ); + + define_write!(fallible, pub try_write8_relaxed, writeb_relaxed <- u8); + define_write!(fallible, pub try_write16_relaxed, writew_relaxed <- u16= ); + define_write!(fallible, pub try_write32_relaxed, writel_relaxed <- u32= ); define_write!( + fallible, #[cfg(CONFIG_64BIT)] - write64_relaxed, - try_write64_relaxed, + pub try_write64_relaxed, writeq_relaxed <- u64 ); } diff --git a/rust/kernel/io/mem.rs b/rust/kernel/io/mem.rs index b03b82cd531b..5dcd7c901427 100644 --- a/rust/kernel/io/mem.rs +++ b/rust/kernel/io/mem.rs @@ -17,8 +17,8 @@ Region, Resource, // }, - Io, - IoRaw, // + Mmio, + MmioRaw, // }, prelude::*, }; @@ -203,7 +203,7 @@ pub fn new<'a>(io_request: IoRequest<'a>) -> impl PinIn= it, Error> + } =20 impl Deref for ExclusiveIoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { &self.iomem @@ -217,10 +217,10 @@ fn deref(&self) -> &Self::Target { /// /// # Invariants /// -/// [`IoMem`] always holds an [`IoRaw`] instance that holds a valid pointe= r to the +/// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid poin= ter to the /// start of the I/O memory mapped region. pub struct IoMem { - io: IoRaw, + io: MmioRaw, } =20 impl IoMem { @@ -255,7 +255,7 @@ fn ioremap(resource: &Resource) -> Result { return Err(ENOMEM); } =20 - let io =3D IoRaw::new(addr as usize, size)?; + let io =3D MmioRaw::new(addr as usize, size)?; let io =3D IoMem { io }; =20 Ok(io) @@ -278,10 +278,10 @@ fn drop(&mut self) { } =20 impl Deref for IoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { // SAFETY: Safe as by the invariant of `IoMem`. - unsafe { Io::from_raw(&self.io) } + unsafe { Mmio::from_raw(&self.io) } } } diff --git a/rust/kernel/io/poll.rs b/rust/kernel/io/poll.rs index b1a2570364f4..543a4b7cea0d 100644 --- a/rust/kernel/io/poll.rs +++ b/rust/kernel/io/poll.rs @@ -45,12 +45,12 @@ /// # Examples /// /// ```no_run -/// use kernel::io::{Io, poll::read_poll_timeout}; +/// use kernel::io::{IoFallible, Mmio, poll::read_poll_timeout}; /// use kernel::time::Delta; /// /// const HW_READY: u16 =3D 0x01; /// -/// fn wait_for_hardware(io: &Io) -> Result { +/// fn wait_for_hardware(io: &Mmio) -> Result { /// read_poll_timeout( /// // The `op` closure reads the value of a specific status regis= ter. /// || io.try_read16(0x1000), @@ -128,12 +128,12 @@ pub fn read_poll_timeout( /// # Examples /// /// ```no_run -/// use kernel::io::{poll::read_poll_timeout_atomic, Io}; +/// use kernel::io::{poll::read_poll_timeout_atomic, IoFallible, Mmio}; /// use kernel::time::Delta; /// /// const HW_READY: u16 =3D 0x01; /// -/// fn wait_for_hardware(io: &Io) -> Result { +/// fn wait_for_hardware(io: &Mmio) -> Result { /// read_poll_timeout_atomic( /// // The `op` closure reads the value of a specific status regis= ter. /// || io.try_read16(0x1000), diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index 0d55c3139b6f..2bbb3261198d 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -8,8 +8,8 @@ device, devres::Devres, io::{ - Io, - IoRaw, // + Mmio, + MmioRaw, // }, prelude::*, sync::aref::ARef, // @@ -24,7 +24,7 @@ /// memory mapped PCI BAR and its size. pub struct Bar { pdev: ARef, - io: IoRaw, + io: MmioRaw, num: i32, } =20 @@ -60,7 +60,7 @@ pub(super) fn new(pdev: &Device, num: u32, name: &CStr) -= > Result { return Err(ENOMEM); } =20 - let io =3D match IoRaw::new(ioptr, len as usize) { + let io =3D match MmioRaw::new(ioptr, len as usize) { Ok(io) =3D> io, Err(err) =3D> { // SAFETY: @@ -114,11 +114,11 @@ fn drop(&mut self) { } =20 impl Deref for Bar { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { // SAFETY: By the type invariant of `Self`, the MMIO range in `sel= f.io` is properly mapped. - unsafe { Io::from_raw(&self.io) } + unsafe { Mmio::from_raw(&self.io) } } } =20 diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci= .rs index ee6248b8cda5..74b93ca7c338 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -8,6 +8,8 @@ c_str, device::Core, devres::Devres, + io::IoFallible, + io::IoInfallible, pci, prelude::*, sync::aref::ARef, // --=20 2.51.0