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([2401:4900:1c06:79c0:4ab7:69ea:ca5e:a64f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-341a67e2f82sm18855643a91.0.2025.11.10.12.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 12:39:39 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support Date: Mon, 10 Nov 2025 20:39:26 +0000 Message-ID: <20251110203926.692242-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs. Configure the MIIC converter in mode 0x6: Port 0 <-> ETHSW Port 0 Port 1 <-> ETHSW Port 1 Port 2 <-> GMAC2 Port 3 <-> GMAC1 Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added once the switch driver is available. Configure the MIIC converters to map ports according to the selected switching mode, with converters 0 and 1 mapped to switch ports and converters 2 and 3 mapped to GMAC ports. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- Note, as rest of the patches of series [0] has been already reviewed and queued sending this lone patch for v3 review. [0] https://lore.kernel.org/all/20251028175458.1037397-1-prabhakar.mahadev-= lad.rj@bp.renesas.com/ v2->v3: - Split comments - Renamed ETHX_{MDC,MDIO} to GMACX_{MDC,MDIO} - Updated commnet for SW2[8] to drop P27_2 and P35_3-P35_5 as they are not used for GMAC1 - Renamed eth2 to gmac2 and eth3 to gmac1 in pinctrl nodes - Corrected pin for ETH2_RXER - Corrected the aliases to match the board schematics - For led0 switched to use VSC8531_ACTIVITY instead of VSC8531_LINK_ACTIVITY. - Renamed phy3 to mdio1_phy and phy2 to mdio2_phy v1->v2: - Dropped *skew-psec properties which are not needed for VSC8541 PHYs. --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 70 +++++++++++++++++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 78 +++++++++++++++++++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 70 +++++++++++++++++ 3 files changed, 218 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 799c58afd6fe..b7706d0bc3aa 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -149,7 +149,77 @@ &i2c1 { status =3D "okay"; }; =20 +&mdio1_phy { + reset-gpios =3D <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>; +}; + +&mdio2_phy { + /* + * PHY2 Reset Configuration: + * + * SW6[1] OFF; SW6[2] ON; SW6[3] OFF - use pin P17_5 for GMAC_RESETOUT2# + */ + reset-gpios =3D <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>; +}; + &pinctrl { + /* + * GMAC2 Pin Configuration: + * + * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 + * SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 + * for Ethernet port 2 + */ + gmac2_pins: gmac2-pins { + pinmux =3D , /* ETH2_TXCLK */ + , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + , /* ETH2_TXEN */ + , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + , /* ETH2_RXDV */ + , /* ETH2_TXER */ + , /* ETH2_RXER */ + , /* ETH2_CRS */ + , /* ETH2_COL */ + , /* GMAC2_MDC */ + , /* GMAC2_MDIO */ + ; /* ETH2_REFCLK */ + }; + + /* + * GMAC1 Pin Configuration: + * + * SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and + * P35_0-P35_2 for Ethernet port 3 + */ + gmac1_pins: gmac1-pins { + pinmux =3D , /* ETH3_TXCLK */ + , /* ETH3_TXD0 */ + , /* ETH3_TXD1 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + , /* ETH3_TXEN */ + , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + , /* ETH3_RXDV */ + , /* ETH3_TXER */ + , /* ETH3_RXER */ + , /* ETH3_CRS */ + , /* ETH3_COL */ + , /* GMAC1_MDC */ + , /* GMAC1_MDIO */ + ; /* ETH3_REFCLK */ + }; + /* * I2C0 Pin Configuration: * ------------------------ diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index d698b6368ee7..17c0c79fbd96 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -186,7 +186,85 @@ &i2c1 { status =3D "okay"; }; =20 +&mdio1_phy { + /* + * PHY3 Reset Configuration: + * + * DSW12[5] OFF; DSW12[6] ON - use pin P03_2 for GMAC_RESETOUT3# + */ + reset-gpios =3D <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>; +}; + +&mdio2_phy { + /* + * PHY2 Reset Configuration: + * + * DSW8[1] ON; DSW8[2] OFF; DSW12[7] OFF; DSW12[8] ON - use pin + * P03_1 for GMAC_RESETOUT2# + */ + reset-gpios =3D <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>; +}; + &pinctrl { + /* + * GMAC2 Pin Configuration: + * + * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 + * DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7, + * P31_2, P31_4 and P31_5 are used for Ethernet port 2 + */ + gmac2_pins: gmac2-pins { + pinmux =3D , /* ETH2_TXCLK */ + , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + , /* ETH2_TXEN */ + , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + , /* ETH2_RXDV */ + , /* ETH2_TXER */ + , /* ETH2_RXER */ + , /* ETH2_CRS */ + , /* ETH2_COL */ + , /* GMAC2_MDC */ + , /* GMAC2_MDIO */ + ; /* ETH2_REFCLK */ + + }; + + /* + * GMAC2 Pin Configuration: + * + * DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6 + * for Ethernet port 3 + * DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3 + */ + gmac1_pins: gmac1-pins { + pinmux =3D , /* ETH3_TXCLK */ + , /* ETH3_TXD0 */ + , /* ETH3_TXD0 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + , /* ETH3_TXEN */ + , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + , /* ETH3_RXDV */ + , /* ETH3_TXER */ + , /* ETH3_RXER */ + , /* ETH3_CRS */ + , /* ETH3_COL */ + , /* GMAC1_MDC */ + , /* GMAC1_MDIO */ + ; /* ETH3_REFCLK */ + }; + /* * I2C0 Pin Configuration: * ------------------------ diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/a= rm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 924a38c6cb0f..3eed1f3948e8 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -7,10 +7,14 @@ =20 #include #include +#include +#include #include =20 / { aliases { + ethernet3 =3D &gmac1; + ethernet2 =3D &gmac2; i2c0 =3D &i2c0; i2c1 =3D &i2c1; mmc0 =3D &sdhi0; @@ -70,10 +74,34 @@ &ehci { status =3D "okay"; }; =20 +ðss { + status =3D "okay"; + + renesas,miic-switch-portin =3D ; +}; + &extal_clk { clock-frequency =3D <25000000>; }; =20 +&gmac1 { + pinctrl-0 =3D <&gmac1_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&mdio1_phy>; + phy-mode =3D "rgmii-id"; + pcs-handle =3D <&mii_conv3>; + status =3D "okay"; +}; + +&gmac2 { + pinctrl-0 =3D <&gmac2_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&mdio2_phy>; + phy-mode =3D "rgmii-id"; + pcs-handle =3D <&mii_conv2>; + status =3D "okay"; +}; + &hsusb { dr_mode =3D "otg"; status =3D "okay"; @@ -87,6 +115,48 @@ eeprom: eeprom@50 { }; }; =20 +&mdio1 { + mdio1_phy: ethernet-phy@3 { + compatible =3D "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + vsc8531,led-0-mode =3D ; + vsc8531,led-1-mode =3D ; + reset-assert-us =3D <2000>; + reset-deassert-us =3D <15000>; + }; +}; + +&mdio2 { + mdio2_phy: ethernet-phy@2 { + compatible =3D "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22"; + reg =3D <2>; + vsc8531,led-0-mode =3D ; + vsc8531,led-1-mode =3D ; + reset-assert-us =3D <2000>; + reset-deassert-us =3D <15000>; + }; +}; + +&mii_conv0 { + renesas,miic-input =3D ; + status =3D "okay"; +}; + +&mii_conv1 { + renesas,miic-input =3D ; + status =3D "okay"; +}; + +&mii_conv2 { + renesas,miic-input =3D ; + status =3D "okay"; +}; + +&mii_conv3 { + renesas,miic-input =3D ; + status =3D "okay"; +}; + &ohci { dr_mode =3D "otg"; status =3D "okay"; --=20 2.43.0