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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Balsam CHIHI CC: , , , , , , , , Subject: [PATCH 1/2] arm64: dts: mediatek: mt8189: Add thermal controller node Date: Mon, 10 Nov 2025 17:40:38 +0800 Message-ID: <20251110094113.3965182-2-hanchien.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251110094113.3965182-1-hanchien.lin@mediatek.com> References: <20251110094113.3965182-1-hanchien.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree node for the thermal controller on MediaTek MT8189 SoC. Signed-off-by: Hanchien Lin --- .../thermal/mediatek,lvts-thermal.yaml | 27 +++++++++++++++++-- .../thermal/mediatek,lvts-thermal.h | 20 ++++++++++++++ 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-therma= l.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.ya= ml index 0259cd3ce9c5..0f7fd69f5fdf 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -22,6 +22,8 @@ properties: - mediatek,mt8186-lvts - mediatek,mt8188-lvts-ap - mediatek,mt8188-lvts-mcu + - mediatek,mt8189-lvts-ap + - mediatek,mt8189-lvts-mcu - mediatek,mt8192-lvts-ap - mediatek,mt8192-lvts-mcu - mediatek,mt8195-lvts-ap @@ -58,6 +60,21 @@ properties: allOf: - $ref: thermal-sensor.yaml# =20 + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8189-lvts-ap + - mediatek,mt8189-lvts-mcu + then: + properties: + nvmem-cells: + minItems: 2 + + nvmem-cell-names: + minItems: 2 + - if: properties: compatible: @@ -75,6 +92,10 @@ allOf: nvmem-cell-names: maxItems: 1 =20 + required: + - clocks + - resets + - if: properties: compatible: @@ -91,12 +112,14 @@ allOf: nvmem-cell-names: minItems: 2 =20 + required: + - clocks + - resets + required: - compatible - reg - interrupts - - clocks - - resets - nvmem-cells - nvmem-cell-names =20 diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index ddc7302a510a..6c9103dfdc2d 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -42,6 +42,26 @@ #define MT8188_AP_CAM1 6 #define MT8188_AP_CAM2 7 =20 +#define MT8189_MCU_BIG_CPU1 0 +#define MT8189_MCU_BIG_CPU2 1 +#define MT8189_MCU_BIG_CPU3 2 +#define MT8189_MCU_BIG_CPU4 3 +#define MT8189_MCU_LITTLE_CPU1 4 +#define MT8189_MCU_LITTLE_CPU2 5 +#define MT8189_MCU_LITTLE_CPU3 6 +#define MT8189_MCU_LITTLE_CPU4 7 +#define MT8189_MCU_LITTLE_CPU5 8 +#define MT8189_MCU_LITTLE_CPU6 9 +#define MT8189_MCU_LITTLE_CPU7 10 +#define MT8189_MCU_LITTLE_CPU8 11 + +#define MT8189_AP_SOC1 12 +#define MT8189_AP_SOC2 13 +#define MT8189_AP_SOC3 14 +#define MT8189_AP_APU 15 +#define MT8189_AP_GPU1 16 +#define MT8189_AP_GPU2 17 + #define MT8195_MCU_BIG_CPU0 0 #define MT8195_MCU_BIG_CPU1 1 #define MT8195_MCU_BIG_CPU2 2 --=20 2.45.2 From nobody Fri Dec 19 21:53:40 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92B342FF16C; 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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Balsam CHIHI CC: , , , , , , , , Subject: [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Add MT8189 support Date: Mon, 10 Nov 2025 17:40:39 +0800 Message-ID: <20251110094113.3965182-3-hanchien.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251110094113.3965182-1-hanchien.lin@mediatek.com> References: <20251110094113.3965182-1-hanchien.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the MediaTek MT8189 SoC to the LVTS thermal driver. Signed-off-by: Hanchien Lin --- drivers/thermal/mediatek/lvts_thermal.c | 155 ++++++++++++++++++++++-- 1 file changed, 144 insertions(+), 11 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index ab55b20cda47..8c15fdaac48c 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -65,6 +65,7 @@ #define LVTS_HW_FILTER 0x0 #define LVTS_TSSEL_CONF 0x13121110 #define LVTS_CALSCALE_CONF 0x300 +#define LVTS_MONINT_CONF_STAGE3 BIT(31) =20 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0 BIT(3) #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1 BIT(8) @@ -107,6 +108,7 @@ struct lvts_sensor_data { struct lvts_ctrl_data { struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; u8 valid_sensor_mask; + int hw_tshut_temp; int offset; int mode; }; @@ -134,6 +136,9 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + bool clock_gate_no_need; + bool reset_no_need; + bool conf_stage3_need; }; =20 struct lvts_sensor { @@ -150,6 +155,7 @@ struct lvts_ctrl { struct lvts_sensor sensors[LVTS_SENSOR_MAX]; const struct lvts_data *lvts_data; u32 calibration[LVTS_SENSOR_MAX]; + u32 hw_tshut_raw_temp; u8 valid_sensor_mask; int mode; void __iomem *base; @@ -859,6 +865,14 @@ static int lvts_ctrl_init(struct device *dev, struct l= vts_domain *lvts_td, */ lvts_ctrl[i].mode =3D lvts_data->lvts_ctrl[i].mode; =20 + /* + * The temperature to raw temperature must be done + * after initializing the calibration. + */ + lvts_ctrl[i].hw_tshut_raw_temp =3D + lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp, + lvts_data->temp_factor); + lvts_ctrl[i].low_thresh =3D INT_MIN; lvts_ctrl[i].high_thresh =3D INT_MIN; } @@ -919,7 +933,7 @@ static void lvts_write_config(struct lvts_ctrl *lvts_ct= rl, const u32 *cmds, int } } =20 -static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) +static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl, const struct lvts_da= ta *lvts_data) { /* * LVTS_PROTCTL : Thermal Protection Sensor Selection @@ -947,6 +961,7 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); * writel(0x0, LVTS_PROTTC(lvts_ctrl->base)); */ + writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); =20 /* * LVTS_MONINT : Interrupt configuration register @@ -954,7 +969,10 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS * register, except we set the bits to enable the interrupt. */ - writel(0, LVTS_MONINT(lvts_ctrl->base)); + if (lvts_data->conf_stage3_need) + writel(LVTS_MONINT_CONF_STAGE3, LVTS_MONINT(lvts_ctrl->base)); + else + writel(0, LVTS_MONINT(lvts_ctrl->base)); =20 return 0; } @@ -1041,7 +1059,8 @@ static int lvts_ctrl_calibrate(struct device *dev, st= ruct lvts_ctrl *lvts_ctrl) return 0; } =20 -static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_= ctrl) +static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_= ctrl, + const struct lvts_data *lvts_data) { u32 value; =20 @@ -1143,7 +1162,7 @@ static int lvts_ctrl_configure(struct device *dev, st= ruct lvts_ctrl *lvts_ctrl) value =3D LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; writel(value, LVTS_MONCTL2(lvts_ctrl->base)); =20 - return lvts_irq_init(lvts_ctrl); + return lvts_irq_init(lvts_ctrl, lvts_data); } =20 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) @@ -1290,7 +1309,7 @@ static int lvts_domain_init(struct device *dev, struc= t lvts_domain *lvts_td, return ret; } =20 - ret =3D lvts_ctrl_configure(dev, lvts_ctrl); + ret =3D lvts_ctrl_configure(dev, lvts_ctrl, lvts_data); if (ret) { dev_dbg(dev, "Failed to configure controller"); return ret; @@ -1322,9 +1341,15 @@ static int lvts_probe(struct platform_device *pdev) if (!lvts_data) return -ENODEV; =20 - lvts_td->clk =3D devm_clk_get_enabled(dev, NULL); - if (IS_ERR(lvts_td->clk)) - return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clo= ck\n"); + if (!lvts_data->clock_gate_no_need) { + lvts_td->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(lvts_td->clk)) + return dev_err_probe( + dev, + PTR_ERR(lvts_td->clk), + "Failed to retrieve clock\n" + ); + } =20 res =3D platform_get_mem_or_io(pdev, 0); if (!res) @@ -1334,9 +1359,15 @@ static int lvts_probe(struct platform_device *pdev) if (IS_ERR(lvts_td->base)) return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io reso= urce\n"); =20 - lvts_td->reset =3D devm_reset_control_get_by_index(dev, 0); - if (IS_ERR(lvts_td->reset)) - return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset = control\n"); + if (!lvts_data->reset_no_need) { + lvts_td->reset =3D devm_reset_control_get_by_index(dev, 0); + if (IS_ERR(lvts_td->reset)) + return dev_err_probe( + dev, + PTR_ERR(lvts_td->reset), + "Failed to get reset control\n" + ); + } =20 irq =3D platform_get_irq(pdev, 0); if (irq < 0) @@ -1586,6 +1617,78 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_da= ta_ctrl[] =3D { } }; =20 +static const struct lvts_ctrl_data mt8189_lvts_mcu_data_ctrl[] =3D { + { + .lvts_sensor =3D { + { .dt_id =3D MT8189_MCU_LITTLE_CPU1, + .cal_offsets =3D { 4, 5, 6 } }, + { .dt_id =3D MT8189_MCU_LITTLE_CPU2, + .cal_offsets =3D { 8, 9, 10 } }, + { .dt_id =3D MT8189_MCU_LITTLE_CPU3, + .cal_offsets =3D { 12, 13, 14 } }, + { .dt_id =3D MT8189_MCU_LITTLE_CPU4, + .cal_offsets =3D { 16, 17, 18 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x0, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8189_MCU_LITTLE_CPU5, + .cal_offsets =3D { 24, 25, 26 } }, + { .dt_id =3D MT8189_MCU_LITTLE_CPU6, + .cal_offsets =3D { 28, 29, 30 } }, + { .dt_id =3D MT8189_MCU_LITTLE_CPU7, + .cal_offsets =3D { 32, 33, 34 } }, + { .dt_id =3D MT8189_MCU_LITTLE_CPU8, + .cal_offsets =3D { 36, 37, 38 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x100, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8189_MCU_BIG_CPU1, + .cal_offsets =3D { 44, 45, 46 } }, + { .dt_id =3D MT8189_MCU_BIG_CPU2, + .cal_offsets =3D { 48, 49, 50 } }, + { .dt_id =3D MT8189_MCU_BIG_CPU3, + .cal_offsets =3D { 52, 53, 54 } }, + { .dt_id =3D MT8189_MCU_BIG_CPU4, + .cal_offsets =3D { 56, 57, 58 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x200, + } +}; + +static const struct lvts_ctrl_data mt8189_lvts_ap_data_ctrl[] =3D { + { + .lvts_sensor =3D { + { .dt_id =3D MT8189_AP_SOC1, + .cal_offsets =3D { 64, 65, 66 } }, + { .dt_id =3D MT8189_AP_SOC2, + .cal_offsets =3D { 68, 69, 70 } }, + { .dt_id =3D MT8189_AP_SOC3, + .cal_offsets =3D { 72, 73, 74 } }, + { .dt_id =3D MT8189_AP_APU, + .cal_offsets =3D { 76, 77, 78 } } + }, + VALID_SENSOR_MAP(1, 1, 1, 1), + .offset =3D 0x0, + }, + { + .lvts_sensor =3D { + { .dt_id =3D MT8189_AP_GPU1, + .cal_offsets =3D { 84, 85, 86 } }, + { .dt_id =3D MT8189_AP_GPU2, + .cal_offsets =3D { 88, 89, 90 } } + }, + VALID_SENSOR_MAP(1, 1, 0, 0), + .offset =3D 0x100, + } +}; + static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] =3D { { .lvts_sensor =3D { @@ -1804,6 +1907,34 @@ static const struct lvts_data mt8188_lvts_ap_data = =3D { .def_calibration =3D 35000, }; =20 +static const struct lvts_data mt8189_lvts_ap_data =3D { + .lvts_ctrl =3D mt8189_lvts_ap_data_ctrl, + .conn_cmd =3D default_conn_cmds, + .init_cmd =3D default_init_cmds, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8189_lvts_ap_data_ctrl), + .num_conn_cmd =3D ARRAY_SIZE(default_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), + .temp_factor =3D LVTS_COEFF_A_MT8195, + .temp_offset =3D LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset =3D 0, + .def_calibration =3D 35000, + .clock_gate_no_need =3D true, + .reset_no_need =3D true, + .conf_stage3_need =3D true, +}; + +static const struct lvts_data mt8189_lvts_mcu_data =3D { + .lvts_ctrl =3D mt8189_lvts_mcu_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8189_lvts_mcu_data_ctrl), + .temp_factor =3D LVTS_COEFF_A_MT8195, + .temp_offset =3D LVTS_COEFF_B_MT8195, + .gt_calib_bit_offset =3D 0, + .def_calibration =3D 35000, + .clock_gate_no_need =3D true, + .reset_no_need =3D true, + .conf_stage3_need =3D true, +}; + static const struct lvts_data mt8192_lvts_mcu_data =3D { .lvts_ctrl =3D mt8192_lvts_mcu_data_ctrl, .conn_cmd =3D default_conn_cmds, @@ -1861,6 +1992,8 @@ static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt8186-lvts", .data =3D &mt8186_lvts_data }, { .compatible =3D "mediatek,mt8188-lvts-mcu", .data =3D &mt8188_lvts_mcu_= data }, { .compatible =3D "mediatek,mt8188-lvts-ap", .data =3D &mt8188_lvts_ap_da= ta }, + { .compatible =3D "mediatek,mt8189-lvts-mcu", .data =3D &mt8189_lvts_mcu_= data }, + { .compatible =3D "mediatek,mt8189-lvts-ap", .data =3D &mt8189_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt8192-lvts-mcu", .data =3D &mt8192_lvts_mcu_= data }, { .compatible =3D "mediatek,mt8192-lvts-ap", .data =3D &mt8192_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_lvts_mcu_= data }, --=20 2.45.2