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Sun, 09 Nov 2025 22:38:09 -0800 (PST) Received: from hu-sartgarg-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-baa3c2d92a9sm10729797a12.20.2025.11.09.22.38.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Nov 2025 22:38:09 -0800 (PST) From: Sarthak Garg To: Adrian Hunter , Ulf Hansson Cc: linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com, Sarthak Garg Subject: [PATCH V1] mmc: sdhci-msm: Avoid early clock doubling during HS400 transition Date: Mon, 10 Nov 2025 12:08:01 +0530 Message-Id: <20251110063801.641866-1-sarthak.garg@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEwMDA1NiBTYWx0ZWRfXy+La2CKZVdUP SbG9YvmPoSdaa+45agbzJGtyJqE6KTFmS/6g00EWN57fGh0ngTY7Oqqf4KZJigCgA3JtNEBLIFW 4RCSESfsG+ioybXTeQG+rLMq4crrSMF4kBIvNR2aM30hSs0d9jiwkMCXQI7wK7plYAEffPWBqok qwJ4JOl6RXnsPcM8vumFp2vF2S2RtDJAgkpDF732yMl6xxnbs/EWjPlh/eeu4K2bC8FU5h5gL4J GkCxTdp0TshHcuYklZYtUFUGMDs+Nmx5hBDXtUAJByFyK8p9WxRmwbCnRRA092/SPvMlbCILu/R tBCnpjeLiMP0X4xXOKzKbTWl0EEh4sVxU42uZ/7ydfmBdvhvnPYZoXhJ2zaMynvWrj31UtpHAa0 ZJSkdhIdl5vaQ0/8xXE9yBVP6uMFHg== X-Authority-Analysis: v=2.4 cv=TsXrRTXh c=1 sm=1 tr=0 ts=69118852 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=hZQ1MXfSydDMrBGxCwYA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: fnklCaxh_7LUJ1GOFspG0dV73_I_MVdN X-Proofpoint-GUID: fnklCaxh_7LUJ1GOFspG0dV73_I_MVdN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-10_02,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511100056 Content-Type: text/plain; charset="utf-8" According to the hardware programming guide, the clock frequency must remain below 52MHz during the transition to HS400 mode. However,in the current implementation, the timing is set to HS400 (a DDR mode) before adjusting the clock. This causes the clock to double prematurely to 104MHz during the transition phase, violating the specification and potentially resulting in CRC errors or CMD timeouts. This change ensures that clock doubling is avoided during intermediate transitions and is applied only when the card requires a 200MHz clock for HS400 operation. Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4e5edbf2fc9b..eca6a09a4547 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -355,7 +355,8 @@ static unsigned int msm_get_clock_mult_for_bus_mode(str= uct sdhci_host *host) */ if (ios.timing =3D=3D MMC_TIMING_UHS_DDR50 || ios.timing =3D=3D MMC_TIMING_MMC_DDR52 || - ios.timing =3D=3D MMC_TIMING_MMC_HS400 || + (ios.timing =3D=3D MMC_TIMING_MMC_HS400 && + ios.clock =3D=3D MMC_HS200_MAX_DTR) || host->flags & SDHCI_HS400_TUNING) return 2; return 1; --=20 2.34.1