From nobody Wed Dec 17 14:22:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2409309F07; Mon, 10 Nov 2025 11:24:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762773846; cv=none; b=KEfkxN2gBpZgazOXUjA7Ca5ayLVvk2h+dMTXZgYUocySQdd+nPnbfb4b+uLQuYYQ1dnYOgAeKl6TgPp+OsKgrrgc45NatKROrkE/VAlq0xZEF54RmmSDMH6GeyZxFgYQBxGnsrjFhPLDGuIArKY8ocCtGIadoCkjYzGRmWQXYSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762773846; c=relaxed/simple; bh=CmXoBLuxUJoBzrxKmX5dd5XpWc+0xXD7kEShU5FrSRg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sSY+vvkYkqYraTVAlvmHxm9tDIV2Qny+uQkNzSJb6EglVU/HF3RE+RUVxVxa41vX/28gP1ejXq31EdsPdg/OpkJw1w19cWFD739iRUBt1mKm3wDMDEi/mz4JBB3Z5Q5lwpIrQ1vZjSYmr7NkatxpVopMcscjw1ilFMDX0499BnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IOcmLUC3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IOcmLUC3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D840C19421; Mon, 10 Nov 2025 11:24:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762773846; bh=CmXoBLuxUJoBzrxKmX5dd5XpWc+0xXD7kEShU5FrSRg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IOcmLUC3TrceYQ9JL7asupXpkrb/756TEH+Xu73myypmYEpbqoPLK3ZbmgBwO6aYT N+39PJS2+9c7p3RrBu5cbxO9Xo7AxPGAQGMcU5gXMOwdaDgeEmcN9WM6VEL8KK9eo9 ubzxGpHxR0rsRhOziFnSM13Nfc919qqhAHBBKRoMGMF0BmOcj6VYJsAMEZqDabD1oL fIeqX3662wW0GdADVAn8WPI13+IRnEFcAlvlERk4XchZjLo4mV2LS7vNWdyalFX2qX rUOANWMairTSFYfZtka8Ptejx5RvcEIs+68F6fE3Bmst7PHjsNXLuBd3EeqCFyS0O2 KVNV+9pV414EQ== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 1/5] reset: mpfs: add non-auxiliary bus probing Date: Mon, 10 Nov 2025 11:23:50 +0000 Message-ID: <20251110-evict-gratified-bb816e2799a2@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251110-zookeeper-femur-68a0ae346397@spud> References: <20251110-zookeeper-femur-68a0ae346397@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8983; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=clSSL3dc+HDx0t1TsHPtxBl7W72R564AkCTNoIHCzak=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJmCp93nVaacL9yoH7+CO8mVPXGmY8sNDXaVn9WfLYr86 7Qfij3uKGVhEONikBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwEQuHmT4wxHiXbZgk2ftxMYf 3gxR1vdW5r9Rj79ep6e+56E078dN2xn+aTh9kg9a8HDWY4edhaohIlqsvbMMu0seeQqfLq06lvq VGwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley While the auxiliary bus was a nice bandaid, and meant that re-writing the representation of the clock regions in devicetree was not required, it has run its course. The "mss_top_sysreg" region that contains the clock and reset regions, also contains pinctrl and an interrupt controller, so the time has come rewrite the devicetree and probe the reset controller from an mfd devicetree node, rather than implement those drivers using the auxiliary bus. Wanting to avoid propagating this naive/incorrect description of the hardware to the new pic64gx SoC is a major motivating factor here. Signed-off-by: Conor Dooley Acked-by: Philipp Zabel Reviewed-by: Philipp Zabel --- v7: - move entirely to regmap - use clear/set instead of update v6: - depend on MFD_SYSCON - return regmap_update_bits() result directly instead of an additional return 0 v4: - Only use driver specific lock for non-regmap writes v2: - Implement the request to use regmap_update_bits(). I found that I then hated the read/write helpers since they were just bloat, so I ripped them out. I replaced the regular spin_lock_irqsave() stuff with a guard(spinlock_irqsave), since that's a simpler way of handling the two different paths through such a trivial pair of functions. --- drivers/clk/microchip/clk-mpfs.c | 4 +- drivers/reset/Kconfig | 1 + drivers/reset/reset-mpfs.c | 92 +++++++++++++++++++------------- include/soc/microchip/mpfs.h | 3 +- 4 files changed, 61 insertions(+), 39 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index 484893e68b67..ee58304913ef 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -38,7 +38,7 @@ static const struct regmap_config mpfs_clk_regmap_config = =3D { .reg_stride =3D 4, .val_bits =3D 32, .val_format_endian =3D REGMAP_ENDIAN_LITTLE, - .max_register =3D REG_SUBBLK_CLOCK_CR, + .max_register =3D REG_SUBBLK_RESET_CR, }; =20 /* @@ -502,7 +502,7 @@ static inline int mpfs_clk_old_format_probe(struct mpfs= _clock_data *clk_data, if (IS_ERR(clk_data->regmap)) return PTR_ERR(clk_data->regmap); =20 - return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RE= SET_CR); + return mpfs_reset_controller_register(dev, clk_data->regmap); } =20 static int mpfs_clk_probe(struct platform_device *pdev) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 78b7078478d4..0ec4b7cd08d6 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -200,6 +200,7 @@ config RESET_PISTACHIO config RESET_POLARFIRE_SOC bool "Microchip PolarFire SoC (MPFS) Reset Driver" depends on MCHP_CLK_MPFS + depends on MFD_SYSCON select AUXILIARY_BUS default MCHP_CLK_MPFS help diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index f6fa10e03ea8..d00212450990 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -7,13 +7,16 @@ * */ #include +#include #include #include +#include #include #include #include -#include +#include #include +#include #include #include =20 @@ -27,11 +30,10 @@ #define MPFS_SLEEP_MIN_US 100 #define MPFS_SLEEP_MAX_US 200 =20 -/* block concurrent access to the soft reset register */ -static DEFINE_SPINLOCK(mpfs_reset_lock); +#define REG_SUBBLK_RESET_CR 0x88u =20 struct mpfs_reset { - void __iomem *base; + struct regmap *regmap; struct reset_controller_dev rcdev; }; =20 @@ -46,41 +48,25 @@ static inline struct mpfs_reset *to_mpfs_reset(struct r= eset_controller_dev *rcde static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; - u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + return regmap_set_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id)); =20 - reg =3D readl(rst->base); - reg |=3D BIT(id); - writel(reg, rst->base); - - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - - return 0; } =20 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; - u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + return regmap_clear_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id)); =20 - reg =3D readl(rst->base); - reg &=3D ~BIT(id); - writel(reg, rst->base); - - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - - return 0; } =20 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - u32 reg =3D readl(rst->base); + u32 reg; + + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®); =20 /* * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit @@ -130,23 +116,58 @@ static int mpfs_reset_xlate(struct reset_controller_d= ev *rcdev, return index - MPFS_PERIPH_OFFSET; } =20 -static int mpfs_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) +static int mpfs_reset_mfd_probe(struct platform_device *pdev) { - struct device *dev =3D &adev->dev; struct reset_controller_dev *rcdev; + struct device *dev =3D &pdev->dev; struct mpfs_reset *rst; =20 rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); if (!rst) return -ENOMEM; =20 - rst->base =3D (void __iomem *)adev->dev.platform_data; + rcdev =3D &rst->rcdev; + rcdev->dev =3D dev; + rcdev->ops =3D &mpfs_reset_ops; + + rcdev->of_node =3D pdev->dev.parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + rst->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rst->regmap)) + return dev_err_probe(dev, PTR_ERR(rst->regmap), + "Failed to find syscon regmap\n"); + + return devm_reset_controller_register(dev, rcdev); +} + +static struct platform_driver mpfs_reset_mfd_driver =3D { + .probe =3D mpfs_reset_mfd_probe, + .driver =3D { + .name =3D "mpfs-reset", + }, +}; +module_platform_driver(mpfs_reset_mfd_driver); + +static int mpfs_reset_adev_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct reset_controller_dev *rcdev; + struct device *dev =3D &adev->dev; + struct mpfs_reset *rst; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rst->regmap =3D (struct regmap *)adev->dev.platform_data; =20 rcdev =3D &rst->rcdev; rcdev->dev =3D dev; - rcdev->dev->parent =3D dev->parent; rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; rcdev->of_reset_n_cells =3D 1; rcdev->of_xlate =3D mpfs_reset_xlate; @@ -155,12 +176,11 @@ static int mpfs_reset_probe(struct auxiliary_device *= adev, return devm_reset_controller_register(dev, rcdev); } =20 -int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *b= ase) +int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *= map) { struct auxiliary_device *adev; =20 - adev =3D devm_auxiliary_device_create(clk_dev, "reset-mpfs", - (__force void *)base); + adev =3D devm_auxiliary_device_create(clk_dev, "reset-mpfs", (void *)map); if (!adev) return -ENODEV; =20 @@ -176,12 +196,12 @@ static const struct auxiliary_device_id mpfs_reset_id= s[] =3D { }; MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); =20 -static struct auxiliary_driver mpfs_reset_driver =3D { - .probe =3D mpfs_reset_probe, +static struct auxiliary_driver mpfs_reset_aux_driver =3D { + .probe =3D mpfs_reset_adev_probe, .id_table =3D mpfs_reset_ids, }; =20 -module_auxiliary_driver(mpfs_reset_driver); +module_auxiliary_driver(mpfs_reset_aux_driver); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); MODULE_AUTHOR("Conor Dooley "); diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h index 0bd67e10b704..ec04c98a8b63 100644 --- a/include/soc/microchip/mpfs.h +++ b/include/soc/microchip/mpfs.h @@ -14,6 +14,7 @@ =20 #include #include +#include =20 struct mpfs_sys_controller; =20 @@ -44,7 +45,7 @@ struct mtd_info *mpfs_sys_controller_get_flash(struct mpf= s_sys_controller *mpfs_ =20 #if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) #if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC) -int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *b= ase); +int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *= map); #else static inline int mpfs_reset_controller_register(struct device *clk_dev, v= oid __iomem *base) { return 0; } #endif /* if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC) */ --=20 2.51.0 From nobody Wed Dec 17 14:22:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D591F30ACFA; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F59LTQtQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8FA67C4CEFB; Mon, 10 Nov 2025 11:24:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762773849; bh=yx40n6aW+7axlHFIv+/k4z1XcQ+4QDorszZ6b/jKM44=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F59LTQtQ/T46ZHPhSBD6fAl/2N80oWK7OmmcQRc9LG6mbzvxSs/Wxjg5BBaqiXr7j 4UO4qcU2x7S+N+5lhfigGP1Pt6tzqhuLxTEuV+qcwNwjQcumnCPndDp7lDzBJP3N7c sM8dZJPvNPGA8XTxsDGknW8hKbQfBIoY3Wr5uDUxjfjf/5kBfrYbTmF7Nl6xjQqgy+ rwDZfw1AosKhCT92iKWFPYMJfVfWfhKvG9ZLXV4Fvbm0IC14CxQ5+3B7b6Va0F2LJr nUNeKwVJMe8gfSiuBpfG10S8CqgWHZd9Y1yNvbrdKyUH1wTaylH6MuQaR8ZWRdaC8T D7DrVCbh/VoYg== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/5] riscv: dts: microchip: fix mailbox description Date: Mon, 10 Nov 2025 11:23:51 +0000 Message-ID: <20251110-rockiness-sank-c22fa8a3bafb@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251110-zookeeper-femur-68a0ae346397@spud> References: <20251110-zookeeper-femur-68a0ae346397@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2048; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=CJ93zZ/gwT2VF26tXat2Gljwq2Roq9NVUZwBFI4dODQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJmCp92P6z3eFjfpFded7KLe80fbPaf6daxL2FJwXkZit sLlCdMedpSyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAi/PcY/qkoHKi4fah5gljy sQkTIzUWyhq+DRfdqSlcNf9lxkP3jA0M/1Sf9KYyzH0zq6rp1tq5jpJsr8/F9RlUxP3u/Rjx8FB WIz8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 9883ca3554c5..f9d6bf08e717 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -259,6 +259,11 @@ clkcfg: clkcfg@20002000 { #reset-cells =3D <1>; }; =20 + sysreg_scb: syscon@20003000 { + compatible =3D "microchip,mpfs-sysreg-scb", "syscon"; + reg =3D <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible =3D "microchip,mpfs-ccc"; reg =3D <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -521,10 +526,14 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon"; + reg =3D <0x0 0x37020000 0x0 0x100>; + }; + + mbox: mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x0 0x37020800 0x0 0x1000>; interrupt-parent =3D <&plic>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.51.0 From nobody Wed Dec 17 14:22:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 499AF30BF4F; Mon, 10 Nov 2025 11:24:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762773853; cv=none; b=P4maDDwYKYgR6kvfHTSen/XiZNMf3KG+maM9empNFXoN58GdxhgG+lIAyBL5A42ulzsBN0cTyQnObR1KJRJYuHEGmYIMYfiqwEGSlOQq86DkJsIAQp8A3+Mv6Me05jDh7goIbUjSPidGzWzmgdVKkmY/2LMbdlbdqd5vq5oaEVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762773853; c=relaxed/simple; bh=o06pwj8GQhduMpl8X9PMCjFDAGlLMLElJucB88tSCYo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FuqdFbCHBYrUZqMKX5r1Xp7ITyjvoXFob1f0u59BzpmhjbykTLyQqQlh0DQ9U3MGzOxmCBdxKF2IX1zULEsawZUv1xOc/h/UyMV4J3yikOb1ged9QELU/3h4ItvCIK4S18Z4QU8KWyYyZEisKKmu2QRi91eJAhjxEbHH1SG0OTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Galcd/L1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Galcd/L1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D160DC2BC87; Mon, 10 Nov 2025 11:24:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762773852; bh=o06pwj8GQhduMpl8X9PMCjFDAGlLMLElJucB88tSCYo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Galcd/L10+CvJOyC2hB+L/6sEPakTPxv6oq5pEbYX100syMbpTcxaQKXxF4UIFfpw Nqn8Mfe5bWKVI5e0PiGO+ZId+qQQx71UAaiP/4nIqTTENORb4bWFk7taghyyQgtpYM QNrqj0tS6a9BK5IXgUnoBFQEZ0QYGFojppOHr0uMJ1Klyvb4D5KY57odrVfHHeRVbg 7ESqQ7kKyO+a4i2JMC8vHMLvxO3BwihzlLBpKPjAAzGcC0/A+Ex5bFDWBCI2a1+gzn wfan6ikC5Qg8xo9uZDGWRl6wLXf/V/oNwYrI8jOJdmZiz72YZJtXbvMtA6/zKGV5c3 s9OYl5W7IlkJQ== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 3/5] riscv: dts: microchip: convert clock and reset to use syscon Date: Mon, 10 Nov 2025 11:23:52 +0000 Message-ID: <20251110-vicinity-stream-b6954d17e01c@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251110-zookeeper-femur-68a0ae346397@spud> References: <20251110-zookeeper-femur-68a0ae346397@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2216; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=+zR8fbMXO9YW4YzwKnjp5SrmA8iRht4FGjwYBRXJ6yY=; b=kA0DAAoWeLQxh6CCYtIByyZiAGkRy0ei3kWAlDeH5mIUl4g8elSv50NtiF0eZr8sfY+ix+Wzx Yh1BAAWCgAdFiEEYduOhBqv/ES4Q4zteLQxh6CCYtIFAmkRy0cACgkQeLQxh6CCYtJ/tgD9FM5J TeDenWu0gbF67ZshvF6KSC/NO3RzRieteMYGyzoBAMmQ9BwHCizv+5ziMGu8PtoqmynJl+SVbnc awI51JWYD X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index f9d6bf08e717..5c2963e269b8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ pdma: dma-controller@3000000 { #dma-cells =3D <1>; }; =20 - clkcfg: clkcfg@20002000 { - compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks =3D <&refclk>; - #clock-cells =3D <1>; + mss_top_sysreg: syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; #reset-cells =3D <1>; }; =20 @@ -452,7 +450,7 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC0>; + resets =3D <&mss_top_sysreg CLK_MAC0>; status =3D "disabled"; }; =20 @@ -466,7 +464,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC1>; + resets =3D <&mss_top_sysreg CLK_MAC1>; status =3D "disabled"; }; =20 @@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 { clocks =3D <&scbclk>; status =3D "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; }; }; --=20 2.51.0 From nobody Wed Dec 17 14:22:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78552309DA0; Mon, 10 Nov 2025 11:24:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 10 Nov 2025 11:24:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762773856; bh=E43Z5Y8tSJqRgamwuiELwt0g0OSF4ium8fxWSOTU1R0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mAA72F0Rq4I2u6jvTdEFPVqAmJ7fTvOkaDGoyA/T7bzy/+LP2SlPPIPQ9a0yDj04s kdMhf90x5TnvmpJRA93dQRQY1IGTHDzwpY5qhYkX+YbVCQvxgOCumd9t+tqUtKmTZu b1PyelrqW3CmiYorwAMIyl0FZKMxGuMX/Ow75V1KWvpLRPYhORymNlhVfTXWW9ju3j FHgYaJ1bOHxF+iyju63WO/R9ciqfNZBxu8VP/Pr5DB0YBE2CFIE9jWTjGzMWS6w11L USyZUa+6+1nsEb+2mX2sxkY83iJjvQAwpqfFAm5IQ8e5Dl6BfKSXxmS/xEvw2BVufL WPpOiSzjE13Uw== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 4/5] MAINTAINERS: add new soc drivers to Microchip RISC-V entry Date: Mon, 10 Nov 2025 11:23:53 +0000 Message-ID: <20251110-creature-spousal-213edfea02ce@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251110-zookeeper-femur-68a0ae346397@spud> References: <20251110-zookeeper-femur-68a0ae346397@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=733; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=gmAo0f4txEXEqIJYVzrDbfZIGVrUbtgonOlTrrMh7lQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJmCpz3O3zCWCLXNS8qzqw1exiS5dfOJP57dfbHNTYF8/ Eau+1Q7SlkYxLgYZMUUWRJv97VIrf/jssO55y3MHFYmkCEMXJwCMJEtKxj+mZvsF6rd3xnnrcAj sf3ZZvZ1goV63F6s//rs203dWhh+MPzPrT/Fbbdj4/u0YreLy5duf77+8abHN99YfP7Y/TP8/5Z IdgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add the two new syscon drivers to the RISC-V entry for Microchip platforms. Signed-off-by: Conor Dooley --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..a28740a7d87a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22105,6 +22105,8 @@ F: drivers/pci/controller/plda/pcie-microchip-host.c F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c +F: drivers/soc/microchip/mpfs-control-scb.c +F: drivers/soc/microchip/mpfs-mss-top-sysreg.c F: drivers/soc/microchip/mpfs-sys-controller.c F: drivers/spi/spi-microchip-core-qspi.c F: drivers/spi/spi-microchip-core.c --=20 2.51.0 From nobody Wed Dec 17 14:22:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C24B230E0F8; Mon, 10 Nov 2025 11:24:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762773859; cv=none; b=PJuoXhUFlGjJOYqfJYeDRduQN6LkPR5FL7J+NSz+HQfesBpUmGSYXxWcX+ya21hh5XnsSgOFZMfbRgtiDUh2fBfNmxhE04XvjTZuBOLzUajlOCChNZOucVIE8Ru0BMyZlMTrmEM/n/Nx76u0zZt5StqK6teY0kHDubN2UNB+kG0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762773859; c=relaxed/simple; bh=4tliw4UQndH1N9g1/up84eMEVp/xYC+YCAsm2JdOf3U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iPzXRfbXEgNCVMsDp9JsY1VasG9oar5vnwyjIEs2gl7BNRbBaEtfeIMcRnCQ97Un86aWwletG9o1wI8Iv5JgNxoU9Mp19jL5J6Y6CzFcBPc0P2F8pAFk8+DC0+O4dyAA2jhblyz6BNkQXwe4voAljY1KUp2zQPrxbLwxK8IyhBQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AEC6dCRf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AEC6dCRf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83A71C16AAE; Mon, 10 Nov 2025 11:24:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762773859; bh=4tliw4UQndH1N9g1/up84eMEVp/xYC+YCAsm2JdOf3U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AEC6dCRfddyR78ZZ50BzzVGaRNGXHaxZrETUuQwVxhO+HJhud69ea51CVKnRUxMz1 GkYETkcs1qyjvHqbzVQnaccSKcsgHLpOu8A4unYLmdJfrccm+zzs9Fd2gg/JCe1b0b 0jxz8FGWkV3NEmKP/Vz08cmF05jtfFa8nSzacnmUY0wFiUq8e4Se4yoIK6kHfoJxW2 WfQe9imOiTgRIHZmHFHahtkc4Rus2qbkqE+VbekKx7ugMMTSqmOKPOnaE5+QypO54F TA8jaWXfw8Qj/lJ5nRiNoGzGWVxUIUylYTalhLY+aUPkcC1or2skdYFgIcEO2XCz0l r8WFyroMh9h+g== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 5/5] MAINTAINERS: rename Microchip RISC-V entry Date: Mon, 10 Nov 2025 11:23:54 +0000 Message-ID: <20251110-feminine-aware-9a4b62e8ac0a@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251110-zookeeper-femur-68a0ae346397@spud> References: <20251110-zookeeper-femur-68a0ae346397@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=735; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=WjqbuqvJbBVUVn1s3EoLv4wSnU+jVPnRC0yZy4Sseq4=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJmCpz1OVp1fejhP4cflksK2aancMk4fN3f39M9yestio yrgUFjfUcrCIMbFICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIms28XIcEbsr/syZxWtFdOu NfFYqm5X5GxWm7d4du0bhavJywI4lzP8r0ix2SIm8uz6PqkoJ+MXWi9EfJ0+6UZEW84QVYywfze dDQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley There's now non-FPGA RISC-V SoCs from Microchip, so rename the entry to reflect that. Signed-off-by: Conor Dooley --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a28740a7d87a..24efae3df425 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22079,7 +22079,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/gi= t/iommu/linux.git F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml F: drivers/iommu/riscv/ =20 -RISC-V MICROCHIP FPGA SUPPORT +RISC-V MICROCHIP SUPPORT M: Conor Dooley M: Daire McNamara L: linux-riscv@lists.infradead.org --=20 2.51.0