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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:28:59 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:44 +0000 Subject: [PATCH v4 01/20] dt-bindings: firmware: google,gs101-acpm-ipc: convert regulators to lowercase Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-1-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Using lowercase for the buck and ldo nodenames is preferred, as evidenced e.g. in [1]. Convert the example here to lowercase before we add any bindings describing the s2mpg1x regulators that will enforce the spelling. Link: https://lore.kernel.org/all/20250223-mysterious-infrared-civet-e5bcbf= @krzk-bin/ [1] Acked-by: Rob Herring (Arm) Signed-off-by: Andr=C3=A9 Draszik --- Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml | 4 = ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-i= pc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.= yaml index d3bca6088d128485618bb2b538ed8596b4ba14f0..4a1e3e3c0505aad6669cadf9b7b= 58aa4c7f284cb 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -75,7 +75,7 @@ examples: interrupts-extended =3D <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; =20 regulators { - LDO1 { + ldo1m { regulator-name =3D "vdd_ldo1"; regulator-min-microvolt =3D <700000>; regulator-max-microvolt =3D <1300000>; @@ -84,7 +84,7 @@ examples: =20 // ... =20 - BUCK1 { + buck8m { regulator-name =3D "vdd_mif"; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:00 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:45 +0000 Subject: [PATCH v4 02/20] regulator: dt-bindings: add s2mpg10-pmic regulators Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-2-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The S2MPG10 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, RTC, clock outputs, and additional GPIO interfaces. It has 10 buck and 31 LDO rails. Several of these can either be controlled via software (register writes) or via external signals, in particular by: * one out of several input pins connected to a main processor's: * GPIO pins * other pins that are e.g. firmware- or power-domain-controlled without explicit driver intervention * a combination of input pins and register writes. Control via input pins allows PMIC rails to be controlled by firmware, e.g. during standby/suspend, or as part of power domain handling where otherwise that would not be possible. Additionally toggling a pin is faster than register writes, and it also allows the PMIC to ensure that any necessary timing requirements between rails are respected automatically if multiple rails are to be enabled or disabled quasi simultaneously. While external control via input pins appears to exist on other versions of this PMIC, there is more flexibility in this version, in particular there is a selection of input pins to choose from for each rail (which must therefore be configured accordingly if in use), whereas other versions don't have this flexibility. Add documentation related to the regulator (buck & ldo) parts like devicetree definitions, regulator naming patterns, and additional properties. S2MPG10 is typically used as the main-PMIC together with an S2MPG11 PMIC in a main/sub configuration, hence the datasheet and the binding both suffix the rails with an 'm'. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Krzysztof Kozlowski --- v4: - Krzysztof: - move additionalProperties to after allOf - use $defs, not definitions v3: - drop PCTRLSEL values that can be described using standard properties (Krzysztof), drop useless ones, rename the remaining ones - drop maxItems:1 where not needed (Krzysztof) - samsung,ext-control-gpios -> enable-gpios (Krzysztof) - fix LDO20M_EN pin name -> VLDO20M_EN v2: - drop | (literal style mark) from samsung,ext-control-gpios description --- .../regulator/samsung,s2mpg10-regulator.yaml | 158 +++++++++++++++++= ++++ MAINTAINERS | 1 + .../regulator/samsung,s2mpg10-regulator.h | 39 +++++ 3 files changed, 198 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mpg10-re= gulator.yaml b/Documentation/devicetree/bindings/regulator/samsung,s2mpg10-= regulator.yaml new file mode 100644 index 0000000000000000000000000000000000000000..7252f94b3a8f3ae339ff6cf3080= 786ba88d44f7e --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/samsung,s2mpg10-regulator= .yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mpg10-regulator.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPG10 Power Management IC regulators + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This is part of the device tree bindings for the S2MG10 Power Management= IC + (PMIC). + + The S2MPG10 PMIC provides 10 buck and 31 LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + # 1 LDO with possible (but limited) external control + ldo20m: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + allOf: + - $ref: "#/$defs/s2mpg10-ext-control" + + properties: + regulator-ramp-delay: false + + samsung,ext-control: + minimum: 11 + +patternProperties: + # 10 bucks + "^buck([1-9]|10)m$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single buck regulator. + + allOf: + - $ref: "#/$defs/s2mpg10-ext-control" + + properties: + regulator-ramp-delay: + enum: [6250, 12500, 25000] + default: 6250 + + samsung,ext-control: + maximum: 10 + + # 12 standard LDOs + "^ldo(2[1-9]?|3[0-1])m$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + properties: + regulator-ramp-delay: false + + # 12 LDOs with possible external control + "^ldo([3-689]|1[046-9])m$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + allOf: + - $ref: "#/$defs/s2mpg10-ext-control" + + properties: + regulator-ramp-delay: false + + samsung,ext-control: + maximum: 10 + + # 6 LDOs with ramp support, 5 out of those with possible external control + "^ldo(1[1235]?|7)m$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + allOf: + - $ref: "#/$defs/s2mpg10-ext-control" + + properties: + regulator-ramp-delay: + enum: [6250, 12500] + default: 6250 + + samsung,ext-control: + maximum: 10 + +$defs: + s2mpg10-ext-control: + properties: + samsung,ext-control: + description: | + These rails can be controlled via one of several possible extern= al + (hardware) signals. If so, this property configures the signal t= he PMIC + should monitor. For S2MPG10 rails where external control is poss= ible other + than ldo20m, the following values generally corresponding to the + respective on-chip pin are valid: + - 0 # S2MPG10_EXTCTRL_PWREN - PWREN pin + - 1 # S2MPG10_EXTCTRL_PWREN_MIF - PWREN_MIF pin + - 2 # S2MPG10_EXTCTRL_AP_ACTIVE_N - ~AP_ACTIVE_N pin + - 3 # S2MPG10_EXTCTRL_CPUCL1_EN - CPUCL1_EN pin + - 4 # S2MPG10_EXTCTRL_CPUCL1_EN2 - CPUCL1_EN & PWREN pins + - 5 # S2MPG10_EXTCTRL_CPUCL2_EN - CPUCL2_EN pin + - 6 # S2MPG10_EXTCTRL_CPUCL2_EN2 - CPUCL2_E2 & PWREN pins + - 7 # S2MPG10_EXTCTRL_TPU_EN - TPU_EN pin + - 8 # S2MPG10_EXTCTRL_TPU_EN2 - TPU_EN & ~AP_ACTIVE_N pins + - 9 # S2MPG10_EXTCTRL_TCXO_ON - TCXO_ON pin + - 10 # S2MPG10_EXTCTRL_TCXO_ON2 - TCXO_ON & ~AP_ACTIVE_N pins + + For S2MPG10 ldo20m, the following values are valid + - 11 # S2MPG10_EXTCTRL_LDO20M_EN2 - VLDO20M_EN & LDO20M_SFR + - 12 # S2MPG10_EXTCTRL_LDO20M_EN - VLDO20M_EN pin + + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 12 + + enable-gpios: + description: + For rails where external control is done via a GPIO, this option= al + property describes the GPIO line used. + + dependentRequired: + enable-gpios: [ "samsung,ext-control" ] + +allOf: + # Bucks 8, 9, and LDO 1 can not be controlled externally - above definit= ion + # allows it and we deny it here. This approach reduces repetition. + - if: + anyOf: + - required: [buck8m] + - required: [buck9m] + - required: [ldo1m] + then: + patternProperties: + "^(buck[8-9]|ldo1)m$": + properties: + samsung,ext-control: false + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 982998ec11346d1c11fcdae5885ba6429fd79ff6..ec675cf240cec5982b044cba583= e0f307990f60a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23051,6 +23051,7 @@ F: drivers/mfd/sec*.[ch] F: drivers/regulator/s2*.c F: drivers/regulator/s5m*.c F: drivers/rtc/rtc-s5m.c +F: include/dt-bindings/regulator/samsung,s2m*.h F: include/linux/mfd/samsung/ =20 SAMSUNG S3C24XX/S3C64XX SOC SERIES CAMIF DRIVER diff --git a/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h b/in= clude/dt-bindings/regulator/samsung,s2mpg10-regulator.h new file mode 100644 index 0000000000000000000000000000000000000000..4a6bf13442f50bb1c475728722e= aebd0ec3dcbfa --- /dev/null +++ b/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2021 Google LLC + * Copyright 2025 Linaro Ltd. + * + * Device Tree binding constants for the Samsung S2MPG1x PMIC regulators + */ + +#ifndef _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H +#define _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H + +/* + * Several regulators may be controlled via external signals instead of via + * software. These constants describe the possible signals for such regula= tors + * and generally correspond to the respecitve on-chip pins. + * + * S2MPG10 regulators supporting these are: + * - buck1m .. buck7m buck10m + * - ldo3m .. ldo19m + * + * ldo20m supports external control, but using a different set of control + * signals. + */ +#define S2MPG10_EXTCTRL_PWREN 0 /* PWREN pin */ +#define S2MPG10_EXTCTRL_PWREN_MIF 1 /* PWREN_MIF pin */ +#define S2MPG10_EXTCTRL_AP_ACTIVE_N 2 /* ~AP_ACTIVE_N pin */ +#define S2MPG10_EXTCTRL_CPUCL1_EN 3 /* CPUCL1_EN pin */ +#define S2MPG10_EXTCTRL_CPUCL1_EN2 4 /* CPUCL1_EN & PWREN pins */ +#define S2MPG10_EXTCTRL_CPUCL2_EN 5 /* CPUCL2_EN pin */ +#define S2MPG10_EXTCTRL_CPUCL2_EN2 6 /* CPUCL2_E2 & PWREN pins */ +#define S2MPG10_EXTCTRL_TPU_EN 7 /* TPU_EN pin */ +#define S2MPG10_EXTCTRL_TPU_EN2 8 /* TPU_EN & ~AP_ACTIVE_N pins */ +#define S2MPG10_EXTCTRL_TCXO_ON 9 /* TCXO_ON pin */ +#define S2MPG10_EXTCTRL_TCXO_ON2 10 /* TCXO_ON & ~AP_ACTIVE_N pins */ + +#define S2MPG10_EXTCTRL_LDO20M_EN2 11 /* VLDO20M_EN & LDO20M_SFR */ +#define S2MPG10_EXTCTRL_LDO20M_EN 12 /* VLDO20M_EN pin */ + +#endif /* _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H */ --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDC1A3358CC for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:00 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:46 +0000 Subject: [PATCH v4 03/20] regulator: dt-bindings: add s2mpg11-pmic regulators Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-3-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The S2MPG11 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, NTC thermistor inputs, and additional GPIO interfaces. It typically complements an S2MPG10 PMIC in a main/sub configuration as the sub-PMIC. S2MPG11 has 12 buck, 1 buck-boost, and 15 LDO rails. Several of these can either be controlled via software (register writes) or via external signals, in particular by: * one out of several input pins connected to a main processor's: * GPIO pins * other pins that are e.g. firmware- or power-domain-controlled without explicit driver intervention * a combination of input pins and register writes. Control via input pins allows PMIC rails to be controlled by firmware, e.g. during standby/suspend, or as part of power domain handling where otherwise that would not be possible. Additionally toggling a pin is faster than register writes, and it also allows the PMIC to ensure that any necessary timing requirements between rails are respected automatically if multiple rails are to be enabled or disabled quasi simultaneously. While external control via input pins appears to exist on other versions of this PMIC, there is more flexibility in this version, in particular there is a selection of input pins to choose from for each rail (which must therefore be configured accordingly if in use), whereas other versions don't have this flexibility. Add documentation related to the regulator (buck & ldo) parts like devicetree definitions, regulator naming patterns, and additional properties. Since S2MPG11 is typically used as the sub-PMIC together with an S2MPG10 as the main-PMIC, the datasheet and the binding both suffix the rails with an 's'. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Krzysztof Kozlowski --- Note: checkpatch suggests to update MAINTAINERS, but the new file is covered already due to using a wildcard. v4: - Krzysztof: - move additionalProperties to after allOf - use $defs, not definitions - update samsung,ext-control: description v3: - mention NTC thermistor inputs in commit message - drop PCTRLSEL values that can be described using standard properties (Krzysztof), drop useless ones, rename the remaining ones - drop maxItems:1 where not needed (Krzysztof) - samsung,ext-control-gpios -> enable-gpios (Krzysztof) - drop buckboost from 'allOf' limitation - not needed as it has its own specific description v2: - fix commit message typos: s2mp1 -> s2mpg1 - mention GPIOs in commit message --- .../regulator/samsung,s2mpg11-regulator.yaml | 136 +++++++++++++++++= ++++ .../regulator/samsung,s2mpg10-regulator.h | 14 +++ 2 files changed, 150 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mpg11-re= gulator.yaml b/Documentation/devicetree/bindings/regulator/samsung,s2mpg11-= regulator.yaml new file mode 100644 index 0000000000000000000000000000000000000000..119386325d1b5b6b0fe35c1f17d= 86e3671fe0fc4 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/samsung,s2mpg11-regulator= .yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mpg11-regulator.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPG11 Power Management IC regulators + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This is part of the device tree bindings for the S2MG11 Power Management= IC + (PMIC). + + The S2MPG11 PMIC provides 12 buck, 1 buck-boost, and 15 LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + buckboost: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for the buck-boost regulator. + + properties: + regulator-ramp-delay: false + +patternProperties: + # 12 bucks + "^buck(([1-9]|10)s|[ad])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single buck regulator. + + allOf: + - $ref: "#/$defs/s2mpg11-ext-control" + + properties: + regulator-ramp-delay: + enum: [6250, 12500, 25000] + default: 6250 + + # 11 standard LDOs + "^ldo([3-79]|1[01245])s$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + properties: + regulator-ramp-delay: false + + # 2 LDOs with possible external control + "^ldo(8|13)s$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + allOf: + - $ref: "#/$defs/s2mpg11-ext-control" + + properties: + regulator-ramp-delay: false + + # 2 LDOs with ramp support and possible external control + "^ldo[12]s$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + allOf: + - $ref: "#/$defs/s2mpg11-ext-control" + + properties: + regulator-ramp-delay: + enum: [6250, 12500] + default: 6250 + +$defs: + s2mpg11-ext-control: + properties: + samsung,ext-control: + description: | + These rails can be controlled via one of several possible extern= al + (hardware) signals. If so, this property configures the signal t= he PMIC + should monitor. The following values generally corresponding to = the + respective on-chip pin are valid: + - 0 # S2MPG11_EXTCTRL_PWREN - PWREN pin + - 1 # S2MPG11_EXTCTRL_PWREN_MIF - PWREN_MIF pin + - 2 # S2MPG11_EXTCTRL_AP_ACTIVE_N - ~AP_ACTIVE_N pin + - 3 # S2MPG11_EXTCTRL_G3D_EN - G3D_EN pin + - 4 # S2MPG11_EXTCTRL_G3D_EN2 - G3D_EN & ~AP_ACTIVE_N pins + - 5 # S2MPG11_EXTCTRL_AOC_VDD - AOC_VDD pin + - 6 # S2MPG11_EXTCTRL_AOC_RET - AOC_RET pin + - 7 # S2MPG11_EXTCTRL_UFS_EN - UFS_EN pin + - 8 # S2MPG11_EXTCTRL_LDO13S_EN - VLDO13S_EN pin + + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 8 + + enable-gpios: + description: + For rails where external control is done via a GPIO, this option= al + property describes the GPIO line used. + + dependentRequired: + enable-gpios: [ "samsung,ext-control" ] + +allOf: + # Bucks 4, 6, 7 and 10 can not be controlled externally - above definiti= on + # allows it and we deny it here. This approach reduces repetition. + - if: + anyOf: + - required: [buck4s] + - required: [buck6s] + - required: [buck7s] + - required: [buck10s] + then: + patternProperties: + "^buck([467]|10)s$": + properties: + samsung,ext-control: false + +additionalProperties: false diff --git a/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h b/in= clude/dt-bindings/regulator/samsung,s2mpg10-regulator.h index 4a6bf13442f50bb1c475728722eaebd0ec3dcbfa..d9c16bba4d85809df99c2887b8d= c61ea1bea5ad1 100644 --- a/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h +++ b/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h @@ -20,6 +20,10 @@ * * ldo20m supports external control, but using a different set of control * signals. + * + * S2MPG11 regulators supporting these are: + * - buck1s .. buck3s buck5s buck8s buck9s bucka buckd + * - ldo1s ldo2s ldo8s ldo13s */ #define S2MPG10_EXTCTRL_PWREN 0 /* PWREN pin */ #define S2MPG10_EXTCTRL_PWREN_MIF 1 /* PWREN_MIF pin */ @@ -36,4 +40,14 @@ #define S2MPG10_EXTCTRL_LDO20M_EN2 11 /* VLDO20M_EN & LDO20M_SFR */ #define S2MPG10_EXTCTRL_LDO20M_EN 12 /* VLDO20M_EN pin */ =20 +#define S2MPG11_EXTCTRL_PWREN 0 /* PWREN pin */ +#define S2MPG11_EXTCTRL_PWREN_MIF 1 /* PWREN_MIF pin */ +#define S2MPG11_EXTCTRL_AP_ACTIVE_N 2 /* ~AP_ACTIVE_N pin */ +#define S2MPG11_EXTCTRL_G3D_EN 3 /* G3D_EN pin */ +#define S2MPG11_EXTCTRL_G3D_EN2 4 /* G3D_EN & ~AP_ACTIVE_N pins */ +#define S2MPG11_EXTCTRL_AOC_VDD 5 /* AOC_VDD pin */ +#define S2MPG11_EXTCTRL_AOC_RET 6 /* AOC_RET pin */ +#define S2MPG11_EXTCTRL_UFS_EN 7 /* UFS_EN pin */ +#define S2MPG11_EXTCTRL_LDO13S_EN 8 /* VLDO13S_EN pin */ + #endif /* _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H */ --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D980A335BC1 for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:01 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:47 +0000 Subject: [PATCH v4 04/20] dt-bindings: mfd: samsung,s2mps11: Split s2mpg10-pmic into separate file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-4-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The samsung,s2mpg10-pmic binding is going to acquire various additional properties. To avoid making the common samsung,s2mps11 binding file too complicateddue to additional nesting, split s2mpg10 out into its own file. As a side-effect, the oneOf for the interrupts is not required anymore, as the required: node is at the top-level now. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Krzysztof Kozlowski --- Note: checkpatch suggests to update MAINTAINERS, but the new file is covered already due to using a wildcard. v4: - make yaml file name match compatible - add example (Krzysztof) v3: - new patch (Krzysztof) --- .../bindings/mfd/samsung,s2mpg10-pmic.yaml | 69 ++++++++++++++++++= ++++ .../devicetree/bindings/mfd/samsung,s2mps11.yaml | 29 +-------- 2 files changed, 70 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yam= l b/Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6475cd1d2d15e07d953c8b302c9= 0c785835985e5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mpg10-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPG10 Power Management IC + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This is part of the device tree bindings for the S2MPG family of Power + Management IC (PMIC). + + The Samsung S2MPG10 is a Power Management IC for mobile applications wit= h buck + converters, various LDOs, power meters, RTC, clock outputs, and addition= al + GPIO interfaces. + +properties: + compatible: + const: samsung,s2mpg10-pmic + + clocks: + $ref: /schemas/clock/samsung,s2mps11.yaml + description: + Child node describing clock provider. + + interrupts: + maxItems: 1 + + regulators: + type: object + description: + List of child nodes that specify the regulators. + + system-power-controller: true + + wakeup-source: true + +required: + - compatible + - interrupts + - regulators + +additionalProperties: false + +examples: + - | + #include + #include + + pmic { + compatible =3D "samsung,s2mpg10-pmic"; + interrupts-extended =3D <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + system-power-controller; + wakeup-source; + + clocks { + compatible =3D "samsung,s2mpg10-clk"; + #clock-cells =3D <1>; + clock-output-names =3D "rtc32k_ap", "peri32k1", "peri32k2"; + }; + + regulators { + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml b/D= ocumentation/devicetree/bindings/mfd/samsung,s2mps11.yaml index 31d544a9c05cad878d10a0ae9b99631f08eb04a8..ac5d0c149796b6a4034b5d4245b= fa8be0433cfab 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml @@ -20,7 +20,6 @@ description: | properties: compatible: enum: - - samsung,s2mpg10-pmic - samsung,s2mps11-pmic - samsung,s2mps13-pmic - samsung,s2mps14-pmic @@ -59,42 +58,16 @@ properties: reset (setting buck voltages to default values). type: boolean =20 - system-power-controller: true - wakeup-source: true =20 required: - compatible + - reg - regulators =20 additionalProperties: false =20 allOf: - - if: - properties: - compatible: - contains: - const: samsung,s2mpg10-pmic - then: - properties: - reg: false - samsung,s2mps11-acokb-ground: false - samsung,s2mps11-wrstbi-ground: false - - # oneOf is required, because dtschema's fixups.py doesn't handle this - # nesting here. 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:01 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:48 +0000 Subject: [PATCH v4 05/20] dt-bindings: mfd: samsung,s2mpg10-pmic: Link to its regulators Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-5-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Update the regulators node to link to the correct and expected samsung,s2mpg10-regulators binding, in order to describe the regulators available on this PMIC. Additionally, describe the supply inputs of the regulator rails, with the supply names matching the datasheet. While at it, update the description and example slightly. Note: S2MPG10 is typically used as the main-PMIC together with an S2MPG11 PMIC in a main/sub configuration, hence the datasheet and the binding both suffix the supplies with an 'm'. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Krzysztof Kozlowski --- v4: - separate bindings for s2mpg10-pmic and s2mpg11-pmic (Krzysztof) v3: - move to new samsung,s2mpg10.yaml file - move all patternProperties to top-level --- .../bindings/mfd/samsung,s2mpg10-pmic.yaml | 57 ++++++++++++++++++= ++-- 1 file changed, 54 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yam= l b/Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yaml index 6475cd1d2d15e07d953c8b302c90c785835985e5..0ea1a440b983a47a55fc86d6251= b89056ba51172 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yaml @@ -10,12 +10,13 @@ maintainers: - Andr=C3=A9 Draszik =20 description: | - This is part of the device tree bindings for the S2MPG family of Power - Management IC (PMIC). + This is part of the device tree bindings for the S2MPG10 Power Managemen= t IC + (PMIC). =20 The Samsung S2MPG10 is a Power Management IC for mobile applications wit= h buck converters, various LDOs, power meters, RTC, clock outputs, and addition= al - GPIO interfaces. + GPIO interfaces and is typically complemented by S2MPG10 PMIC in a main/= sub + configuration as the main PMIC. =20 properties: compatible: @@ -31,6 +32,7 @@ properties: =20 regulators: type: object + $ref: /schemas/regulator/samsung,s2mpg10-regulator.yaml description: List of child nodes that specify the regulators. =20 @@ -38,6 +40,32 @@ properties: =20 wakeup-source: true =20 +patternProperties: + "^vinb([1-9]|10)m-supply$": + description: + Phandle to the power supply for each buck rail of this PMIC. There i= s a + 1:1 mapping of supply to rail, e.g. vinb1m-supply supplies buck1m. + + "^vinl([1-9]|1[0-5])m-supply$": + description: | + Phandle to the power supply for one or multiple LDO rails of this PM= IC. + The mapping of supply to rail(s) is as follows: + vinl1m - ldo13m + vinl2m - ldo15m + vinl3m - ldo1m, ldo5m, ldo7m + vinl4m - ldo3m, ldo8m + vinl5m - ldo16m + vinl6m - ldo17m + vinl7m - ldo6m, ldo11m, ldo24m, ldo28m + vinl8m - ldo12m + vinl9m - ldo2m, ldo4m + vinl10m - ldo9m, ldo14m, ldo18m, 19m, ldo20m, ldo25m + vinl11m - ldo23m, ldo31m + vinl12m - ldo29m + vinl13m - ldo30m + vinl14m - ldo21m + vinl15m - ldo10m, ldo22m, ldo26m, ldo27m + required: - compatible - interrupts @@ -49,6 +77,7 @@ examples: - | #include #include + #include =20 pmic { compatible =3D "samsung,s2mpg10-pmic"; @@ -58,6 +87,8 @@ examples: system-power-controller; wakeup-source; =20 + vinl3m-supply =3D <&buck8m>; + clocks { compatible =3D "samsung,s2mpg10-clk"; #clock-cells =3D <1>; @@ -65,5 +96,25 @@ examples: }; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:02 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:49 +0000 Subject: [PATCH v4 06/20] dt-bindings: mfd: Add samsung,s2mpg11-pmic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-6-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The Samsung S2MPG11 PMIC is similar to the existing S2MPG10 PMIC supported by this binding, but still differs enough from it to justify a separate binding. It is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, NTC thermistor inputs, and additional GPIO interfaces and typically complements an S2MPG10 PMIC in a main/sub configuration as the sub-PMIC. Like S2MPG10, communication is via the Samsung ACPM firmware and it therefore needs to be a child of the ACPM firmware node. Add the PMIC, the regulators node, and the supply inputs of the regulator rails, with the supply names matching the datasheet. Note: S2MPG11 is typically used as the sub-PMIC together with an S2MPG10 PMIC in a main/sub configuration, hence the datasheet and the binding both suffix the supplies with an 's'. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Krzysztof Kozlowski --- v4: - Krzysztof: - move to new separate binding samsung,s2mpg11-pmic.yaml - add example v3: - move to new samsung,s2mpg10.yaml file - deny 'clocks' property - mention NTC thermistor inputs in commit message - move all patternProperties to top-level v2: - add | to vinb*-supply description for better formatting to mark as literal style - mention GPIOs in commit message --- .../bindings/mfd/samsung,s2mpg11-pmic.yaml | 88 ++++++++++++++++++= ++++ 1 file changed, 88 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mpg11-pmic.yam= l b/Documentation/devicetree/bindings/mfd/samsung,s2mpg11-pmic.yaml new file mode 100644 index 0000000000000000000000000000000000000000..62cedbbd9d8c4cb7e9dfc039c1c= 747e334903b20 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mpg11-pmic.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mpg11-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPG11 Power Management IC + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This is part of the device tree bindings for the S2MPG11 Power Managemen= t IC + (PMIC). + + The Samsung S2MPG11 is a Power Management IC for mobile applications wit= h buck + converters, various LDOs, power meters, NTC thermistor inputs, and addit= ional + GPIO interfaces and typically complements an S2MPG10 PMIC in a main/sub + configuration as the sub-PMIC. + +properties: + compatible: + const: samsung,s2mpg11-pmic + + interrupts: + maxItems: 1 + + regulators: + type: object + $ref: /schemas/regulator/samsung,s2mpg11-regulator.yaml + description: + List of child nodes that specify the regulators. + + wakeup-source: true + +patternProperties: + "^vinb(([1-9]|10)s|[abd])-supply$": + description: + Phandle to the power supply for each buck rail of this PMIC. There i= s a + 1:1 mapping of numbered supply to rail, e.g. vinb1s-supply supplies + buck1s. The remaining mapping is as follows + vinba - bucka + vinbb - buck boost + vinbd - buckd + + "^vinl[1-6]s-supply$": + description: | + Phandle to the power supply for one or multiple LDO rails of this PM= IC. + The mapping of supply to rail(s) is as follows + vinl1s - ldo1s, ldo2s + vinl2s - ldo8s, ldo9s + vinl3s - ldo3s, ldo5s, ldo7s, ldo15s + vinl4s - ldo10s, ldo11s, ldo12s, ldo14s + vinl5s - ldo4s, ldo6s + vinl6s - ldo13s + +required: + - compatible + - interrupts + - regulators + +additionalProperties: false + +examples: + - | + #include + #include + #include + + pmic { + compatible =3D "samsung,s2mpg11-pmic"; + interrupts-extended =3D <&gpa0 7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + wakeup-source; + + vinl1s-supply =3D <&buck8m>; + vinl2s-supply =3D <&buck6s>; + + regulators { + buckd { + regulator-name =3D "vcc_ufs"; + regulator-ramp-delay =3D <6250>; + enable-gpios =3D <&gpp0 1 GPIO_ACTIVE_HIGH>; + samsung,ext-control =3D ; + }; + }; + }; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:02 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:50 +0000 Subject: [PATCH v4 07/20] dt-bindings: firmware: google,gs101-acpm-ipc: add S2MPG11 secondary PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-7-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 In a typical system using the Samsung S2MPG10 PMIC, an S2MPG11 is used as a sub-PMIC. The interface for both is the ACPM firmware protocol, so update the binding to allow the relevant node and update the example here to describe the connection for both PMICs. Since we have two PMICs here, but can not use the 'reg' property (as the addressing is based on software, i.e. the ACPM firmware), the node names reflect that with their respective suffix. The existing 'pmic' therefore becomes deprecated in favour of 'pmic-1'. While at it, update the example. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Krzysztof Kozlowski --- v4: - Krzysztof: - update commit message / subject - pmic -> pmic-1, pmic2 -> pmic-2 --- .../bindings/firmware/google,gs101-acpm-ipc.yaml | 50 ++++++++++++++++++= +++- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-i= pc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.= yaml index 4a1e3e3c0505aad6669cadf9b7b58aa4c7f284cb..e68f9c3ca5e2619bacc0c8d843e= c4984c0947fd8 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -37,6 +37,7 @@ properties: maxItems: 1 =20 pmic: + deprecated: true description: Child node describing the main PMIC. type: object additionalProperties: true @@ -45,6 +46,24 @@ properties: compatible: const: samsung,s2mpg10-pmic =20 + pmic-1: + description: Child node describing the main PMIC. + type: object + additionalProperties: true + + properties: + compatible: + const: samsung,s2mpg10-pmic + + pmic-2: + description: Child node describing the sub PMIC. + type: object + additionalProperties: true + + properties: + compatible: + const: samsung,s2mpg11-pmic + shmem: description: List of phandle pointing to the shared memory (SHM) area. The memory @@ -62,7 +81,9 @@ additionalProperties: false =20 examples: - | + #include #include + #include =20 power-management { compatible =3D "google,gs101-acpm-ipc"; @@ -70,10 +91,12 @@ examples: mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; =20 - pmic { + pmic-1 { compatible =3D "samsung,s2mpg10-pmic"; interrupts-extended =3D <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; =20 + vinl3m-supply =3D <&buck8m>; + regulators { ldo1m { regulator-name =3D "vdd_ldo1"; @@ -82,7 +105,13 @@ examples: regulator-always-on; }; =20 - // ... + ldo20m { + regulator-name =3D "vdd_dmics"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1300000>; + regulator-always-on; + samsung,ext-control =3D ; + }; =20 buck8m { regulator-name =3D "vdd_mif"; @@ -93,4 +122,21 @@ examples: }; }; }; + + pmic-2 { + compatible =3D "samsung,s2mpg11-pmic"; + interrupts-extended =3D <&gpa0 7 IRQ_TYPE_LEVEL_LOW>; + + vinl1s-supply =3D <&buck8m>; + vinl2s-supply =3D <&buck6s>; + + regulators { + buckd { + regulator-name =3D "vcc_ufs"; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:03 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:51 +0000 Subject: [PATCH v4 08/20] mfd: sec-common: Instantiate s2mpg10 bucks and ldos separately Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-8-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Bucks can conceivably be used as supplies for LDOs, but currently it can be impossible to mark BUCKs as LDO supplies. This becomes particularly an issue with the upcoming support for the S2MPG11 PMIC. The typical use of the S2MPG10 PMIC is in combination with an S2MPG11 PMIC in a main/sub configuration. Bucks of one are usually used as supplies for LDOs of either itself or of the other: several S2MPG10 LDOs are consumers of various S2MPG10 bucks & S2MPG11 bucks, and several S2MPG11 LDOs are supplied by various S2MPG10 bucks & S2MPG11 bucks. So we have a circular dependency here - LDOs (and potentially also bucks) of one PMIC depend on bucks of the other. This means that if all S2MPG10 rails are handled by the same instance of the S2MPG10 regulator driver, probe of all rails will defer, because the supplies to the LDOs can not be resolved during probe. The same goes for S2MPG11. The result is that neither driver can probe successfully and probe will ultimately fail. In other words it's currently impossible to mark BUCKs as LDO supplies. Additionally, multiple (LDO-) rails may share the same (buck) supply rail and some of these LDOs might supply important consumers, e.g. RAM. To stay with RAM, if one of those consumers needs to defer probe before the rail supplying RAM has probed, the shared (buck) supply gets disabled and the whole system comes to a halt, since Linux hasn't seen the DDR-supplying rail yet, and hasn't had a chance to mark the buck rail as having another consumer. By splitting all rails into separate driver instances, the circular dependency is gone, each individual instance can probe when its supplies are ready. This approach also solves the multiple-consumers-on-one-rail issue during probe. The mfd_cell's ::id field is used to inform the regulator driver which regulator to instantiate. Signed-off-by: Andr=C3=A9 Draszik --- v3: - one instance per actual rail, not per rail type (LDO or buck) - more descriptive commit message v2: - fix commit message typos: s2mp1 -> s2mpg1 --- drivers/mfd/sec-common.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index 42d55e70e34c8d7cd68cddaecc88017e259365b4..b722481594801e545d24014af6a= fd5e1e39d7522 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -35,7 +36,47 @@ static const struct mfd_cell s2dos05_devs[] =3D { =20 static const struct mfd_cell s2mpg10_devs[] =3D { MFD_CELL_NAME("s2mpg10-meter"), - MFD_CELL_NAME("s2mpg10-regulator"), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK1), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK2), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK3), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK4), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK5), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK6), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK7), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK8), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK9), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_BUCK10), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO1), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO2), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO3), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO4), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO5), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO6), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO7), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO8), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO9), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO10), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO11), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO12), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO13), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO14), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO15), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO16), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO17), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO18), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO19), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO20), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO21), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO22), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO23), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO24), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO25), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO26), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO27), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO28), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO29), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO30), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_LDO31), MFD_CELL_NAME("s2mpg10-rtc"), MFD_CELL_OF("s2mpg10-clk", NULL, NULL, 0, 0, "samsung,s2mpg10-clk"), MFD_CELL_OF("s2mpg10-gpio", NULL, NULL, 0, 0, "samsung,s2mpg10-gpio"), --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6917B33557D for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:03 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:52 +0000 Subject: [PATCH v4 09/20] mfd: sec: Add support for S2MPG11 PMIC via ACPM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-9-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Add support for Samsung's S2MPG11 PMIC, which is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, NTC thermistor inputs, and additional GPIO interfaces. It typically complements an S2MPG10 PMIC in a main/sub configuration as the sub-PMIC. Like S2MPG10, communication is not via I2C, but via the Samsung ACPM firmware. Also like S2MPG10, the regulator rails will need to be instantiated individually to allow probe to succeed due to rails being used as supplies for S2MPG10, and to avoid supply rails from being disabled unexpectedly due to probe deferral. Note: The firmware uses the ACPM channel ID and the Speedy channel ID to select the PMIC address. Since these are firmware properties, they can not be retrieved from DT, but instead are deducted from the compatible for now. Signed-off-by: Andr=C3=A9 Draszik --- Note: checkpatch suggests to update MAINTAINERS, but the new file is covered already due to using a wildcard. v3: - mention NTC thermistor inputs in commit message - one instance per actual rail, not per rail type (LDO or buck) v2: - mention GPIOs in commit message --- drivers/mfd/sec-acpm.c | 213 +++++++++++++++++- drivers/mfd/sec-common.c | 45 +++- drivers/mfd/sec-irq.c | 67 +++++- include/linux/mfd/samsung/core.h | 1 + include/linux/mfd/samsung/irq.h | 99 ++++++++ include/linux/mfd/samsung/s2mpg11.h | 434 ++++++++++++++++++++++++++++++++= ++++ 6 files changed, 848 insertions(+), 11 deletions(-) diff --git a/drivers/mfd/sec-acpm.c b/drivers/mfd/sec-acpm.c index 8b31c816d65b86c54a108fa994384abfac0e7da4..b44af6f8b1cdfcb75cf9d4c55c9= d973a88fd510c 100644 --- a/drivers/mfd/sec-acpm.c +++ b/drivers/mfd/sec-acpm.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -216,6 +217,155 @@ static const struct regmap_config s2mpg10_regmap_conf= ig_meter =3D { .cache_type =3D REGCACHE_FLAT, }; =20 +static const struct regmap_range s2mpg11_common_registers[] =3D { + regmap_reg_range(0x00, 0x02), /* CHIP_ID_S, INT, INT_MASK */ + regmap_reg_range(0x0a, 0x0c), /* Speedy control */ + regmap_reg_range(0x1a, 0x27), /* Debug */ +}; + +static const struct regmap_range s2mpg11_common_ro_registers[] =3D { + regmap_reg_range(0x00, 0x01), /* CHIP_ID_S, INT */ + regmap_reg_range(0x25, 0x27), /* Debug */ +}; + +static const struct regmap_range s2mpg11_common_nonvolatile_registers[] = =3D { + regmap_reg_range(0x00, 0x00), /* CHIP_ID_S */ + regmap_reg_range(0x02, 0x02), /* INT_MASK */ + regmap_reg_range(0x0a, 0x0c), /* Speedy control */ +}; + +static const struct regmap_range s2mpg11_common_precious_registers[] =3D { + regmap_reg_range(0x01, 0x01), /* INT */ +}; + +static const struct regmap_access_table s2mpg11_common_wr_table =3D { + .yes_ranges =3D s2mpg11_common_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_common_registers), + .no_ranges =3D s2mpg11_common_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_common_ro_registers), +}; + +static const struct regmap_access_table s2mpg11_common_rd_table =3D { + .yes_ranges =3D s2mpg11_common_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_common_registers), +}; + +static const struct regmap_access_table s2mpg11_common_volatile_table =3D { + .no_ranges =3D s2mpg11_common_nonvolatile_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_common_nonvolatile_registers), +}; + +static const struct regmap_access_table s2mpg11_common_precious_table =3D { + .yes_ranges =3D s2mpg11_common_precious_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_common_precious_registers), +}; + +static const struct regmap_config s2mpg11_regmap_config_common =3D { + .name =3D "common", + .reg_bits =3D ACPM_ADDR_BITS, + .val_bits =3D 8, + .max_register =3D S2MPG11_COMMON_SPD_DEBUG4, + .wr_table =3D &s2mpg11_common_wr_table, + .rd_table =3D &s2mpg11_common_rd_table, + .volatile_table =3D &s2mpg11_common_volatile_table, + .precious_table =3D &s2mpg11_common_precious_table, + .num_reg_defaults_raw =3D S2MPG11_COMMON_SPD_DEBUG4 + 1, + .cache_type =3D REGCACHE_FLAT, +}; + +static const struct regmap_range s2mpg11_pmic_registers[] =3D { + regmap_reg_range(0x00, 0x5a), /* All PMIC registers */ + regmap_reg_range(0x5c, 0xb7), /* All PMIC registers */ +}; + +static const struct regmap_range s2mpg11_pmic_ro_registers[] =3D { + regmap_reg_range(0x00, 0x05), /* INTx */ + regmap_reg_range(0x0c, 0x0d), /* STATUS OFFSRC */ + regmap_reg_range(0x98, 0x98), /* GPIO input */ +}; + +static const struct regmap_range s2mpg11_pmic_nonvolatile_registers[] =3D { + regmap_reg_range(0x06, 0x0b), /* INTxM */ +}; + +static const struct regmap_range s2mpg11_pmic_precious_registers[] =3D { + regmap_reg_range(0x00, 0x05), /* INTx */ +}; + +static const struct regmap_access_table s2mpg11_pmic_wr_table =3D { + .yes_ranges =3D s2mpg11_pmic_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_pmic_registers), + .no_ranges =3D s2mpg11_pmic_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_pmic_ro_registers), +}; + +static const struct regmap_access_table s2mpg11_pmic_rd_table =3D { + .yes_ranges =3D s2mpg11_pmic_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_pmic_registers), +}; + +static const struct regmap_access_table s2mpg11_pmic_volatile_table =3D { + .no_ranges =3D s2mpg11_pmic_nonvolatile_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_pmic_nonvolatile_registers), +}; + +static const struct regmap_access_table s2mpg11_pmic_precious_table =3D { + .yes_ranges =3D s2mpg11_pmic_precious_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_pmic_precious_registers), +}; + +static const struct regmap_config s2mpg11_regmap_config_pmic =3D { + .name =3D "pmic", + .reg_bits =3D ACPM_ADDR_BITS, + .val_bits =3D 8, + .max_register =3D S2MPG11_PMIC_LDO_SENSE2, + .wr_table =3D &s2mpg11_pmic_wr_table, + .rd_table =3D &s2mpg11_pmic_rd_table, + .volatile_table =3D &s2mpg11_pmic_volatile_table, + .precious_table =3D &s2mpg11_pmic_precious_table, + .num_reg_defaults_raw =3D S2MPG11_PMIC_LDO_SENSE2 + 1, + .cache_type =3D REGCACHE_FLAT, +}; + +static const struct regmap_range s2mpg11_meter_registers[] =3D { + regmap_reg_range(0x00, 0x3e), /* Meter config */ + regmap_reg_range(0x40, 0x8a), /* Meter data */ + regmap_reg_range(0x8d, 0x9c), /* Meter data */ +}; + +static const struct regmap_range s2mpg11_meter_ro_registers[] =3D { + regmap_reg_range(0x40, 0x9c), /* Meter data */ +}; + +static const struct regmap_access_table s2mpg11_meter_wr_table =3D { + .yes_ranges =3D s2mpg11_meter_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_meter_registers), + .no_ranges =3D s2mpg11_meter_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_meter_ro_registers), +}; + +static const struct regmap_access_table s2mpg11_meter_rd_table =3D { + .yes_ranges =3D s2mpg11_meter_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_meter_registers), +}; + +static const struct regmap_access_table s2mpg11_meter_volatile_table =3D { + .yes_ranges =3D s2mpg11_meter_ro_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_meter_ro_registers), +}; + +static const struct regmap_config s2mpg11_regmap_config_meter =3D { + .name =3D "meter", + .reg_bits =3D ACPM_ADDR_BITS, + .val_bits =3D 8, + .max_register =3D S2MPG11_METER_LPF_DATA_NTC7_2, + .wr_table =3D &s2mpg11_meter_wr_table, + .rd_table =3D &s2mpg11_meter_rd_table, + .volatile_table =3D &s2mpg11_meter_volatile_table, + .num_reg_defaults_raw =3D S2MPG11_METER_LPF_DATA_NTC7_2 + 1, + .cache_type =3D REGCACHE_FLAT, +}; + struct sec_pmic_acpm_shared_bus_context { const struct acpm_handle *acpm; unsigned int acpm_chan_id; @@ -325,16 +475,22 @@ static struct regmap *sec_pmic_acpm_regmap_init(struc= t device *dev, return regmap; } =20 -static void sec_pmic_acpm_mask_common_irqs(void *regmap_common) +static void sec_pmic_acpm_mask_common_s2mpg10_irqs(void *regmap_common) { regmap_write(regmap_common, S2MPG10_COMMON_INT_MASK, S2MPG10_COMMON_INT_S= RC); } =20 +static void sec_pmic_acpm_mask_common_s2mpg11_irqs(void *regmap_common) +{ + regmap_write(regmap_common, S2MPG11_COMMON_INT_MASK, S2MPG11_COMMON_INT_S= RC); +} + static int sec_pmic_acpm_probe(struct platform_device *pdev) { struct regmap *regmap_common, *regmap_pmic, *regmap; const struct sec_pmic_acpm_platform_data *pdata; struct sec_pmic_acpm_shared_bus_context *shared_ctx; + void (*masq_irqs_handler)(void *data); const struct acpm_handle *acpm; struct device *dev =3D &pdev->dev; int ret, irq; @@ -365,7 +521,19 @@ static int sec_pmic_acpm_probe(struct platform_device = *pdev) return PTR_ERR(regmap_common); =20 /* Mask all interrupts from 'common' block, until successful init */ - ret =3D regmap_write(regmap_common, S2MPG10_COMMON_INT_MASK, S2MPG10_COMM= ON_INT_SRC); + switch (pdata->device_type) { + case S2MPG10: + ret =3D regmap_write(regmap_common, S2MPG10_COMMON_INT_MASK, S2MPG10_COM= MON_INT_SRC); + break; + + case S2MPG11: + ret =3D regmap_write(regmap_common, S2MPG11_COMMON_INT_MASK, S2MPG11_COM= MON_INT_SRC); + break; + + default: + return dev_err_probe(dev, -EINVAL, "Unsupported device type %d\n", + pdata->device_type); + } if (ret) return dev_err_probe(dev, ret, "failed to mask common block interrupts\n= "); =20 @@ -374,10 +542,12 @@ static int sec_pmic_acpm_probe(struct platform_device= *pdev) if (IS_ERR(regmap_pmic)) return PTR_ERR(regmap_pmic); =20 - regmap =3D sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCES= STYPE_RTC, - pdata->regmap_cfg_rtc, true); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); + if (pdata->regmap_cfg_rtc) { + regmap =3D sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCE= SSTYPE_RTC, + pdata->regmap_cfg_rtc, true); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + } =20 regmap =3D sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCES= STYPE_METER, pdata->regmap_cfg_meter, true); @@ -392,13 +562,28 @@ static int sec_pmic_acpm_probe(struct platform_device= *pdev) devm_device_init_wakeup(dev); =20 /* Unmask PMIC interrupt from 'common' block, now that everything is in p= lace. */ - ret =3D regmap_clear_bits(regmap_common, S2MPG10_COMMON_INT_MASK, - S2MPG10_COMMON_INT_SRC_PMIC); + switch (pdata->device_type) { + case S2MPG10: + ret =3D regmap_clear_bits(regmap_common, S2MPG10_COMMON_INT_MASK, + S2MPG10_COMMON_INT_SRC_PMIC); + masq_irqs_handler =3D sec_pmic_acpm_mask_common_s2mpg10_irqs; + break; + + case S2MPG11: + ret =3D regmap_clear_bits(regmap_common, S2MPG11_COMMON_INT_MASK, + S2MPG11_COMMON_INT_SRC_PMIC); + masq_irqs_handler =3D sec_pmic_acpm_mask_common_s2mpg11_irqs; + break; + + default: + return dev_err_probe(dev, -EINVAL, "Unsupported device type %d\n", + pdata->device_type); + } if (ret) return dev_err_probe(dev, ret, "failed to unmask PMIC interrupt\n"); =20 /* Mask all interrupts from 'common' block on shutdown */ - ret =3D devm_add_action_or_reset(dev, sec_pmic_acpm_mask_common_irqs, reg= map_common); + ret =3D devm_add_action_or_reset(dev, masq_irqs_handler, regmap_common); if (ret) return ret; =20 @@ -420,8 +605,18 @@ static const struct sec_pmic_acpm_platform_data s2mpg1= 0_data =3D { .regmap_cfg_meter =3D &s2mpg10_regmap_config_meter, }; =20 +static const struct sec_pmic_acpm_platform_data s2mpg11_data =3D { + .device_type =3D S2MPG11, + .acpm_chan_id =3D 2, + .speedy_channel =3D 1, + .regmap_cfg_common =3D &s2mpg11_regmap_config_common, + .regmap_cfg_pmic =3D &s2mpg11_regmap_config_pmic, + .regmap_cfg_meter =3D &s2mpg11_regmap_config_meter, +}; + static const struct of_device_id sec_pmic_acpm_of_match[] =3D { { .compatible =3D "samsung,s2mpg10-pmic", .data =3D &s2mpg10_data, }, + { .compatible =3D "samsung,s2mpg11-pmic", .data =3D &s2mpg11_data, }, { }, }; MODULE_DEVICE_TABLE(of, sec_pmic_acpm_of_match); diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index b722481594801e545d24014af6afd5e1e39d7522..4daa0ece91dc783560dfad499f1= 1193b689c2fd1 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -82,6 +83,39 @@ static const struct mfd_cell s2mpg10_devs[] =3D { MFD_CELL_OF("s2mpg10-gpio", NULL, NULL, 0, 0, "samsung,s2mpg10-gpio"), }; =20 +static const struct mfd_cell s2mpg11_devs[] =3D { + MFD_CELL_NAME("s2mpg11-meter"), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCKBOOST), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK1), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK2), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK3), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK4), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK5), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK6), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK7), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK8), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK9), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCK10), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCKD), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_BUCKA), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO1), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO2), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO3), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO4), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO5), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO6), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO7), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO8), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO9), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO10), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO11), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO12), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO13), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO14), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG11_LDO15), + MFD_CELL_OF("s2mpg11-gpio", NULL, NULL, 0, 0, "samsung,s2mpg11-gpio"), +}; + static const struct mfd_cell s2mps11_devs[] =3D { MFD_CELL_NAME("s2mps11-regulator"), MFD_CELL_NAME("s2mps14-rtc"), @@ -125,8 +159,13 @@ static void sec_pmic_dump_rev(struct sec_pmic_dev *sec= _pmic) unsigned int val; =20 /* For s2mpg1x, the revision is in a different regmap */ - if (sec_pmic->device_type =3D=3D S2MPG10) + switch (sec_pmic->device_type) { + case S2MPG10: + case S2MPG11: return; + default: + break; + } =20 /* For each device type, the REG_ID is always the first register */ if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val)) @@ -231,6 +270,10 @@ int sec_pmic_probe(struct device *dev, int device_type= , unsigned int irq, sec_devs =3D s2mpg10_devs; num_sec_devs =3D ARRAY_SIZE(s2mpg10_devs); break; + case S2MPG11: + sec_devs =3D s2mpg11_devs; + num_sec_devs =3D ARRAY_SIZE(s2mpg11_devs); + break; case S2MPS11X: sec_devs =3D s2mps11_devs; num_sec_devs =3D ARRAY_SIZE(s2mps11_devs); diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index c5c80b1ba104e6c5a55b442d2f10a8554201a961..a04e46144baae6a195a84df56c5= 3e399e3875e3d 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -73,6 +74,58 @@ static const struct regmap_irq s2mpg10_irqs[] =3D { REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK= ), }; =20 +static const struct regmap_irq s2mpg11_irqs[] =3D { + REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONF, 0, S2MPG11_IRQ_PWRONF_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONR, 0, S2MPG11_IRQ_PWRONR_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUT_MIF, 0, S2MPG11_IRQ_PIF_TIMEOUT_MI= F_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUTS, 0, S2MPG11_IRQ_PIF_TIMEOUTS_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_WTSR, 0, S2MPG11_IRQ_WTSR_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_ABNORMAL_STOP, 0, S2MPG11_IRQ_SPD_ABNORMAL= _STOP_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_PARITY_ERR, 0, S2MPG11_IRQ_SPD_PARITY_ERR_= MASK), + + REGMAP_IRQ_REG(S2MPG11_IRQ_140C, 1, S2MPG11_IRQ_INT140C_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_120C, 1, S2MPG11_IRQ_INT120C_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_TSD, 1, S2MPG11_IRQ_TSD_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_WRST, 1, S2MPG11_IRQ_WRST_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_CYCLE_DONE, 1, S2MPG11_IRQ_NTC_CYCLE_DONE_= MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_PMETER_OVERF, 1, S2MPG11_IRQ_PMETER_OVERF_MASK= ), + + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B1S, 2, S2MPG11_IRQ_OCP_B1S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B2S, 2, S2MPG11_IRQ_OCP_B2S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B3S, 2, S2MPG11_IRQ_OCP_B3S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B4S, 2, S2MPG11_IRQ_OCP_B4S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B5S, 2, S2MPG11_IRQ_OCP_B5S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B6S, 2, S2MPG11_IRQ_OCP_B6S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B7S, 2, S2MPG11_IRQ_OCP_B7S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B8S, 2, S2MPG11_IRQ_OCP_B8S_MASK), + + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B9S, 3, S2MPG11_IRQ_OCP_B9S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B10S, 3, S2MPG11_IRQ_OCP_B10S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BDS, 3, S2MPG11_IRQ_OCP_BDS_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BAS, 3, S2MPG11_IRQ_OCP_BAS_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BBS, 3, S2MPG11_IRQ_OCP_BBS_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_WLWP_ACC, 3, S2MPG11_IRQ_WLWP_ACC_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_SRP_PKT_RST, 3, S2MPG11_IRQ_SPD_SRP_PKT_RS= T_MASK), + + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH0, 4, S2MPG11_IRQ_PWR_WARN_CH0_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH1, 4, S2MPG11_IRQ_PWR_WARN_CH1_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH2, 4, S2MPG11_IRQ_PWR_WARN_CH2_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH3, 4, S2MPG11_IRQ_PWR_WARN_CH3_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH4, 4, S2MPG11_IRQ_PWR_WARN_CH4_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH5, 4, S2MPG11_IRQ_PWR_WARN_CH5_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH6, 4, S2MPG11_IRQ_PWR_WARN_CH6_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH7, 4, S2MPG11_IRQ_PWR_WARN_CH7_MASK= ), + + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH0, 5, S2MPG11_IRQ_NTC_WARN_CH0_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH1, 5, S2MPG11_IRQ_NTC_WARN_CH1_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH2, 5, S2MPG11_IRQ_NTC_WARN_CH2_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH3, 5, S2MPG11_IRQ_NTC_WARN_CH3_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH4, 5, S2MPG11_IRQ_NTC_WARN_CH4_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH5, 5, S2MPG11_IRQ_NTC_WARN_CH5_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH6, 5, S2MPG11_IRQ_NTC_WARN_CH6_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH7, 5, S2MPG11_IRQ_NTC_WARN_CH7_MASK= ), +}; + static const struct regmap_irq s2mps11_irqs[] =3D { REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), @@ -180,7 +233,7 @@ static const struct regmap_irq s5m8767_irqs[] =3D { REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK), }; =20 -/* All S2MPG10 interrupt sources are read-only and don't require clearing = */ +/* All S2MPG1x interrupt sources are read-only and don't require clearing = */ static const struct regmap_irq_chip s2mpg10_irq_chip =3D { .name =3D "s2mpg10", .irqs =3D s2mpg10_irqs, @@ -190,6 +243,15 @@ static const struct regmap_irq_chip s2mpg10_irq_chip = =3D { .mask_base =3D S2MPG10_PMIC_INT1M, }; =20 +static const struct regmap_irq_chip s2mpg11_irq_chip =3D { + .name =3D "s2mpg11", + .irqs =3D s2mpg11_irqs, + .num_irqs =3D ARRAY_SIZE(s2mpg11_irqs), + .num_regs =3D 6, + .status_base =3D S2MPG11_PMIC_INT1, + .mask_base =3D S2MPG11_PMIC_INT1M, +}; + static const struct regmap_irq_chip s2mps11_irq_chip =3D { .name =3D "s2mps11", .irqs =3D s2mps11_irqs, @@ -270,6 +332,9 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic) case S2MPG10: sec_irq_chip =3D &s2mpg10_irq_chip; break; + case S2MPG11: + sec_irq_chip =3D &s2mpg11_irq_chip; + break; case S2MPS11X: sec_irq_chip =3D &s2mps11_irq_chip; break; diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/c= ore.h index d785e101fe795a5d8f9cccf4ccc4232437e89416..f5fba117bea61b3e3fb308759dc= 2748f6dd01dfb 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -40,6 +40,7 @@ enum sec_device_type { S2DOS05, S2MPA01, S2MPG10, + S2MPG11, S2MPS11X, S2MPS13X, S2MPS14X, diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/ir= q.h index b4805cbd949bd605004bd88cf361109d1cbbc3bf..08b1ab33bad48194491fef88d48= d5d0027e06a7c 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h @@ -160,6 +160,105 @@ enum s2mpg10_irq { S2MPG10_IRQ_NR, }; =20 +enum s2mpg11_irq { + /* PMIC */ + S2MPG11_IRQ_PWRONF, + S2MPG11_IRQ_PWRONR, + S2MPG11_IRQ_PIF_TIMEOUT_MIF, + S2MPG11_IRQ_PIF_TIMEOUTS, + S2MPG11_IRQ_WTSR, + S2MPG11_IRQ_SPD_ABNORMAL_STOP, + S2MPG11_IRQ_SPD_PARITY_ERR, +#define S2MPG11_IRQ_PWRONF_MASK BIT(0) +#define S2MPG11_IRQ_PWRONR_MASK BIT(1) +#define S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK BIT(3) +#define S2MPG11_IRQ_PIF_TIMEOUTS_MASK BIT(4) +#define S2MPG11_IRQ_WTSR_MASK BIT(5) +#define S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6) +#define S2MPG11_IRQ_SPD_PARITY_ERR_MASK BIT(7) + + S2MPG11_IRQ_140C, + S2MPG11_IRQ_120C, + S2MPG11_IRQ_TSD, + S2MPG11_IRQ_WRST, + S2MPG11_IRQ_NTC_CYCLE_DONE, + S2MPG11_IRQ_PMETER_OVERF, +#define S2MPG11_IRQ_INT140C_MASK BIT(0) +#define S2MPG11_IRQ_INT120C_MASK BIT(1) +#define S2MPG11_IRQ_TSD_MASK BIT(2) +#define S2MPG11_IRQ_WRST_MASK BIT(5) +#define S2MPG11_IRQ_NTC_CYCLE_DONE_MASK BIT(6) +#define S2MPG11_IRQ_PMETER_OVERF_MASK BIT(7) + + S2MPG11_IRQ_OCP_B1S, + S2MPG11_IRQ_OCP_B2S, + S2MPG11_IRQ_OCP_B3S, + S2MPG11_IRQ_OCP_B4S, + S2MPG11_IRQ_OCP_B5S, + S2MPG11_IRQ_OCP_B6S, + S2MPG11_IRQ_OCP_B7S, + S2MPG11_IRQ_OCP_B8S, +#define S2MPG11_IRQ_OCP_B1S_MASK BIT(0) +#define S2MPG11_IRQ_OCP_B2S_MASK BIT(1) +#define S2MPG11_IRQ_OCP_B3S_MASK BIT(2) +#define S2MPG11_IRQ_OCP_B4S_MASK BIT(3) +#define S2MPG11_IRQ_OCP_B5S_MASK BIT(4) +#define S2MPG11_IRQ_OCP_B6S_MASK BIT(5) +#define S2MPG11_IRQ_OCP_B7S_MASK BIT(6) +#define S2MPG11_IRQ_OCP_B8S_MASK BIT(7) + + S2MPG11_IRQ_OCP_B9S, + S2MPG11_IRQ_OCP_B10S, + S2MPG11_IRQ_OCP_BDS, + S2MPG11_IRQ_OCP_BAS, + S2MPG11_IRQ_OCP_BBS, + S2MPG11_IRQ_WLWP_ACC, + S2MPG11_IRQ_SPD_SRP_PKT_RST, +#define S2MPG11_IRQ_OCP_B9S_MASK BIT(0) +#define S2MPG11_IRQ_OCP_B10S_MASK BIT(1) +#define S2MPG11_IRQ_OCP_BDS_MASK BIT(2) +#define S2MPG11_IRQ_OCP_BAS_MASK BIT(3) +#define S2MPG11_IRQ_OCP_BBS_MASK BIT(4) +#define S2MPG11_IRQ_WLWP_ACC_MASK BIT(5) +#define S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK BIT(7) + + S2MPG11_IRQ_PWR_WARN_CH0, + S2MPG11_IRQ_PWR_WARN_CH1, + S2MPG11_IRQ_PWR_WARN_CH2, + S2MPG11_IRQ_PWR_WARN_CH3, + S2MPG11_IRQ_PWR_WARN_CH4, + S2MPG11_IRQ_PWR_WARN_CH5, + S2MPG11_IRQ_PWR_WARN_CH6, + S2MPG11_IRQ_PWR_WARN_CH7, +#define S2MPG11_IRQ_PWR_WARN_CH0_MASK BIT(0) +#define S2MPG11_IRQ_PWR_WARN_CH1_MASK BIT(1) +#define S2MPG11_IRQ_PWR_WARN_CH2_MASK BIT(2) +#define S2MPG11_IRQ_PWR_WARN_CH3_MASK BIT(3) +#define S2MPG11_IRQ_PWR_WARN_CH4_MASK BIT(4) +#define S2MPG11_IRQ_PWR_WARN_CH5_MASK BIT(5) +#define S2MPG11_IRQ_PWR_WARN_CH6_MASK BIT(6) +#define S2MPG11_IRQ_PWR_WARN_CH7_MASK BIT(7) + + S2MPG11_IRQ_NTC_WARN_CH0, + S2MPG11_IRQ_NTC_WARN_CH1, + S2MPG11_IRQ_NTC_WARN_CH2, + S2MPG11_IRQ_NTC_WARN_CH3, + S2MPG11_IRQ_NTC_WARN_CH4, + S2MPG11_IRQ_NTC_WARN_CH5, + S2MPG11_IRQ_NTC_WARN_CH6, + S2MPG11_IRQ_NTC_WARN_CH7, +#define S2MPG11_IRQ_NTC_WARN_CH0_MASK BIT(0) +#define S2MPG11_IRQ_NTC_WARN_CH1_MASK BIT(1) +#define S2MPG11_IRQ_NTC_WARN_CH2_MASK BIT(2) +#define S2MPG11_IRQ_NTC_WARN_CH3_MASK BIT(3) +#define S2MPG11_IRQ_NTC_WARN_CH4_MASK BIT(4) +#define S2MPG11_IRQ_NTC_WARN_CH5_MASK BIT(5) +#define S2MPG11_IRQ_NTC_WARN_CH6_MASK BIT(6) +#define S2MPG11_IRQ_NTC_WARN_CH7_MASK BIT(7) + + S2MPG11_IRQ_NR, +}; + enum s2mps11_irq { S2MPS11_IRQ_PWRONF, S2MPS11_IRQ_PWRONR, diff --git a/include/linux/mfd/samsung/s2mpg11.h b/include/linux/mfd/samsun= g/s2mpg11.h new file mode 100644 index 0000000000000000000000000000000000000000..db300cb3bcef1b5b8630e189c58= dbb92df8e6cb4 --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg11.h @@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Samsung Electronics + * Copyright 2020 Google Inc + * Copyright 2025 Linaro Ltd. + */ + +#ifndef __LINUX_MFD_S2MPG11_H +#define __LINUX_MFD_S2MPG11_H + +/* Common registers (type 0x000) */ +enum s2mpg11_common_reg { + S2MPG11_COMMON_CHIPID, + S2MPG11_COMMON_INT, + S2MPG11_COMMON_INT_MASK, + S2MPG11_COMMON_SPD_CTRL1 =3D 0x0a, + S2MPG11_COMMON_SPD_CTRL2, + S2MPG11_COMMON_SPD_CTRL3, + S2MPG11_COMMON_MON1SEL =3D 0x1a, + S2MPG11_COMMON_MON2SEL, + S2MPG11_COMMON_MONR, + S2MPG11_COMMON_DEBUG_CTRL1, + S2MPG11_COMMON_DEBUG_CTRL2, + S2MPG11_COMMON_DEBUG_CTRL3, + S2MPG11_COMMON_DEBUG_CTRL4, + S2MPG11_COMMON_DEBUG_CTRL5, + S2MPG11_COMMON_DEBUG_CTRL6, + S2MPG11_COMMON_TEST_MODE1, + S2MPG11_COMMON_SPD_DEBUG1, + S2MPG11_COMMON_SPD_DEBUG2, + S2MPG11_COMMON_SPD_DEBUG3, + S2MPG11_COMMON_SPD_DEBUG4, +}; + +/* For S2MPG11_COMMON_INT and S2MPG11_COMMON_INT_MASK */ +#define S2MPG11_COMMON_INT_SRC GENMASK(2, 0) +#define S2MPG11_COMMON_INT_SRC_PMIC BIT(0) + +/* PMIC registers (type 0x100) */ +enum s2mpg11_pmic_reg { + S2MPG11_PMIC_INT1, + S2MPG11_PMIC_INT2, + S2MPG11_PMIC_INT3, + S2MPG11_PMIC_INT4, + S2MPG11_PMIC_INT5, + S2MPG11_PMIC_INT6, + S2MPG11_PMIC_INT1M, + S2MPG11_PMIC_INT2M, + S2MPG11_PMIC_INT3M, + S2MPG11_PMIC_INT4M, + S2MPG11_PMIC_INT5M, + S2MPG11_PMIC_INT6M, + S2MPG11_PMIC_STATUS1, + S2MPG11_PMIC_OFFSRC, + S2MPG11_PMIC_COMMON_CTRL1, + S2MPG11_PMIC_COMMON_CTRL2, + S2MPG11_PMIC_COMMON_CTRL3, + S2MPG11_PMIC_MIMICKING_CTRL, + S2MPG11_PMIC_B1S_CTRL, + S2MPG11_PMIC_B1S_OUT1, + S2MPG11_PMIC_B1S_OUT2, + S2MPG11_PMIC_B2S_CTRL, + S2MPG11_PMIC_B2S_OUT1, + S2MPG11_PMIC_B2S_OUT2, + S2MPG11_PMIC_B3S_CTRL, + S2MPG11_PMIC_B3S_OUT1, + S2MPG11_PMIC_B3S_OUT2, + S2MPG11_PMIC_B4S_CTRL, + S2MPG11_PMIC_B4S_OUT, + S2MPG11_PMIC_B5S_CTRL, + S2MPG11_PMIC_B5S_OUT, + S2MPG11_PMIC_B6S_CTRL, + S2MPG11_PMIC_B6S_OUT1, + S2MPG11_PMIC_B6S_OUT2, + S2MPG11_PMIC_B7S_CTRL, + S2MPG11_PMIC_B7S_OUT1, + S2MPG11_PMIC_B7S_OUT2, + S2MPG11_PMIC_B8S_CTRL, + S2MPG11_PMIC_B8S_OUT1, + S2MPG11_PMIC_B8S_OUT2, + S2MPG11_PMIC_B9S_CTRL, + S2MPG11_PMIC_B9S_OUT1, + S2MPG11_PMIC_B9S_OUT2, + S2MPG11_PMIC_B10S_CTRL, + S2MPG11_PMIC_B10S_OUT, + S2MPG11_PMIC_BUCKD_CTRL, + S2MPG11_PMIC_BUCKD_OUT, + S2MPG11_PMIC_BUCKA_CTRL, + S2MPG11_PMIC_BUCKA_OUT, + S2MPG11_PMIC_BB_CTRL, + S2MPG11_PMIC_BB_OUT1, + S2MPG11_PMIC_BB_OUT2, + S2MPG11_PMIC_BUCK1S_USONIC, + S2MPG11_PMIC_BUCK2S_USONIC, + S2MPG11_PMIC_BUCK3S_USONIC, + S2MPG11_PMIC_BUCK4S_USONIC, + S2MPG11_PMIC_BUCK5S_USONIC, + S2MPG11_PMIC_BUCK6S_USONIC, + S2MPG11_PMIC_BUCK7S_USONIC, + S2MPG11_PMIC_BUCK8S_USONIC, + S2MPG11_PMIC_BUCK9S_USONIC, + S2MPG11_PMIC_BUCK10S_USONIC, + S2MPG11_PMIC_BUCKD_USONIC, + S2MPG11_PMIC_BUCKA_USONIC, + S2MPG11_PMIC_BB_USONIC, + S2MPG11_PMIC_L1S_CTRL1, + S2MPG11_PMIC_L1S_CTRL2, + S2MPG11_PMIC_L2S_CTRL1, + S2MPG11_PMIC_L2S_CTRL2, + S2MPG11_PMIC_L3S_CTRL, + S2MPG11_PMIC_L4S_CTRL, + S2MPG11_PMIC_L5S_CTRL, + S2MPG11_PMIC_L6S_CTRL, + S2MPG11_PMIC_L7S_CTRL, + S2MPG11_PMIC_L8S_CTRL, + S2MPG11_PMIC_L9S_CTRL, + S2MPG11_PMIC_L10S_CTRL, + S2MPG11_PMIC_L11S_CTRL, + S2MPG11_PMIC_L12S_CTRL, + S2MPG11_PMIC_L13S_CTRL, + S2MPG11_PMIC_L14S_CTRL, + S2MPG11_PMIC_L15S_CTRL, + S2MPG11_PMIC_LDO_CTRL1, + S2MPG11_PMIC_LDO_DSCH1, + S2MPG11_PMIC_LDO_DSCH2, + S2MPG11_PMIC_DVS_RAMP1, + S2MPG11_PMIC_DVS_RAMP2, + S2MPG11_PMIC_DVS_RAMP3, + S2MPG11_PMIC_DVS_RAMP4, + S2MPG11_PMIC_DVS_RAMP5, + S2MPG11_PMIC_DVS_RAMP6, + /* Nothing @ 0x5a */ + S2MPG11_PMIC_DVS_SYNC_CTRL1 =3D 0x5c, + S2MPG11_PMIC_DVS_SYNC_CTRL2, + S2MPG11_PMIC_OFF_CTRL1, + S2MPG11_PMIC_OFF_CTRL2, + S2MPG11_PMIC_OFF_CTRL3, + S2MPG11_PMIC_SEQ_CTRL1, + S2MPG11_PMIC_SEQ_CTRL2, + S2MPG11_PMIC_SEQ_CTRL3, + S2MPG11_PMIC_SEQ_CTRL4, + S2MPG11_PMIC_SEQ_CTRL5, + S2MPG11_PMIC_SEQ_CTRL6, + S2MPG11_PMIC_SEQ_CTRL7, + S2MPG11_PMIC_SEQ_CTRL8, + S2MPG11_PMIC_SEQ_CTRL9, + S2MPG11_PMIC_SEQ_CTRL10, + S2MPG11_PMIC_SEQ_CTRL11, + S2MPG11_PMIC_SEQ_CTRL12, + S2MPG11_PMIC_SEQ_CTRL13, + S2MPG11_PMIC_SEQ_CTRL14, + S2MPG11_PMIC_SEQ_CTRL15, + S2MPG11_PMIC_SEQ_CTRL16, + S2MPG11_PMIC_SEQ_CTRL17, + S2MPG11_PMIC_SEQ_CTRL18, + S2MPG11_PMIC_SEQ_CTRL19, + S2MPG11_PMIC_SEQ_CTRL20, + S2MPG11_PMIC_SEQ_CTRL21, + S2MPG11_PMIC_SEQ_CTRL22, + S2MPG11_PMIC_SEQ_CTRL23, + S2MPG11_PMIC_SEQ_CTRL24, + S2MPG11_PMIC_SEQ_CTRL25, + S2MPG11_PMIC_SEQ_CTRL26, + S2MPG11_PMIC_SEQ_CTRL27, + S2MPG11_PMIC_OFF_SEQ_CTRL1, + S2MPG11_PMIC_OFF_SEQ_CTRL2, + S2MPG11_PMIC_OFF_SEQ_CTRL3, + S2MPG11_PMIC_OFF_SEQ_CTRL4, + S2MPG11_PMIC_OFF_SEQ_CTRL5, + S2MPG11_PMIC_OFF_SEQ_CTRL6, + S2MPG11_PMIC_OFF_SEQ_CTRL7, + S2MPG11_PMIC_OFF_SEQ_CTRL8, + S2MPG11_PMIC_OFF_SEQ_CTRL9, + S2MPG11_PMIC_OFF_SEQ_CTRL10, + S2MPG11_PMIC_OFF_SEQ_CTRL11, + S2MPG11_PMIC_OFF_SEQ_CTRL12, + S2MPG11_PMIC_OFF_SEQ_CTRL13, + S2MPG11_PMIC_OFF_SEQ_CTRL14, + S2MPG11_PMIC_OFF_SEQ_CTRL15, + S2MPG11_PMIC_OFF_SEQ_CTRL16, + S2MPG11_PMIC_OFF_SEQ_CTRL17, + S2MPG11_PMIC_PCTRLSEL1, + S2MPG11_PMIC_PCTRLSEL2, + S2MPG11_PMIC_PCTRLSEL3, + S2MPG11_PMIC_PCTRLSEL4, + S2MPG11_PMIC_PCTRLSEL5, + S2MPG11_PMIC_PCTRLSEL6, + S2MPG11_PMIC_DCTRLSEL1, + S2MPG11_PMIC_DCTRLSEL2, + S2MPG11_PMIC_DCTRLSEL3, + S2MPG11_PMIC_DCTRLSEL4, + S2MPG11_PMIC_DCTRLSEL5, + S2MPG11_PMIC_GPIO_CTRL1, + S2MPG11_PMIC_GPIO_CTRL2, + S2MPG11_PMIC_GPIO_CTRL3, + S2MPG11_PMIC_GPIO_CTRL4, + S2MPG11_PMIC_GPIO_CTRL5, + S2MPG11_PMIC_GPIO_CTRL6, + S2MPG11_PMIC_GPIO_CTRL7, + S2MPG11_PMIC_B2S_OCP_WARN, + S2MPG11_PMIC_B2S_OCP_WARN_X, + S2MPG11_PMIC_B2S_OCP_WARN_Y, + S2MPG11_PMIC_B2S_OCP_WARN_Z, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_X, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Y, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Z, + S2MPG11_PMIC_BUCK_OCP_EN1, + S2MPG11_PMIC_BUCK_OCP_EN2, + S2MPG11_PMIC_BUCK_OCP_PD_EN1, + S2MPG11_PMIC_BUCK_OCP_PD_EN2, + S2MPG11_PMIC_BUCK_OCP_CTRL1, + S2MPG11_PMIC_BUCK_OCP_CTRL2, + S2MPG11_PMIC_BUCK_OCP_CTRL3, + S2MPG11_PMIC_BUCK_OCP_CTRL4, + S2MPG11_PMIC_BUCK_OCP_CTRL5, + S2MPG11_PMIC_BUCK_OCP_CTRL6, + S2MPG11_PMIC_BUCK_OCP_CTRL7, + S2MPG11_PMIC_PIF_CTRL, + S2MPG11_PMIC_BUCK_HR_MODE1, + S2MPG11_PMIC_BUCK_HR_MODE2, + S2MPG11_PMIC_FAULTOUT_CTRL, + S2MPG11_PMIC_LDO_SENSE1, + S2MPG11_PMIC_LDO_SENSE2, +}; + +/* For S2MPG11_PMIC_PCTRLSELx */ +#define S2MPG11_PCTRLSEL_PWREN 0x1 /* PWREN pin */ +#define S2MPG11_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING= _CTRL */ +#define S2MPG11_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */ +#define S2MPG11_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMIC= KING_CTRL */ +#define S2MPG11_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */ +#define S2MPG11_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MI= MICKING_CTRL */ +#define S2MPG11_PCTRLSEL_G3D_EN 0x7 /* G3D_EN pin */ +#define S2MPG11_PCTRLSEL_G3D_EN2 0x8 /* G3D_EN & ~AP_ACTIVE_N pins= */ +#define S2MPG11_PCTRLSEL_AOC_VDD 0x9 /* AOC_VDD pin */ +#define S2MPG11_PCTRLSEL_AOC_RET 0xa /* AOC_RET pin */ +#define S2MPG11_PCTRLSEL_UFS_EN 0xb /* UFS_EN pin */ +#define S2MPG11_PCTRLSEL_LDO13S_EN 0xc /* VLDO13S_EN pin */ + +/* Meter registers (type 0xa00) */ +enum s2mpg11_meter_reg { + S2MPG11_METER_CTRL1, + S2MPG11_METER_CTRL2, + S2MPG11_METER_CTRL3, + S2MPG11_METER_CTRL4, + S2MPG11_METER_CTRL5, + S2MPG11_METER_BUCKEN1, + S2MPG11_METER_BUCKEN2, + S2MPG11_METER_MUXSEL0, + S2MPG11_METER_MUXSEL1, + S2MPG11_METER_MUXSEL2, + S2MPG11_METER_MUXSEL3, + S2MPG11_METER_MUXSEL4, + S2MPG11_METER_MUXSEL5, + S2MPG11_METER_MUXSEL6, + S2MPG11_METER_MUXSEL7, + S2MPG11_METER_LPF_C0_0, + S2MPG11_METER_LPF_C0_1, + S2MPG11_METER_LPF_C0_2, + S2MPG11_METER_LPF_C0_3, + S2MPG11_METER_LPF_C0_4, + S2MPG11_METER_LPF_C0_5, + S2MPG11_METER_LPF_C0_6, + S2MPG11_METER_LPF_C0_7, + S2MPG11_METER_NTC_LPF_C0_0, + S2MPG11_METER_NTC_LPF_C0_1, + S2MPG11_METER_NTC_LPF_C0_2, + S2MPG11_METER_NTC_LPF_C0_3, + S2MPG11_METER_NTC_LPF_C0_4, + S2MPG11_METER_NTC_LPF_C0_5, + S2MPG11_METER_NTC_LPF_C0_6, + S2MPG11_METER_NTC_LPF_C0_7, + S2MPG11_METER_PWR_WARN0, + S2MPG11_METER_PWR_WARN1, + S2MPG11_METER_PWR_WARN2, + S2MPG11_METER_PWR_WARN3, + S2MPG11_METER_PWR_WARN4, + S2MPG11_METER_PWR_WARN5, + S2MPG11_METER_PWR_WARN6, + S2MPG11_METER_PWR_WARN7, + S2MPG11_METER_NTC_L_WARN0, + S2MPG11_METER_NTC_L_WARN1, + S2MPG11_METER_NTC_L_WARN2, + S2MPG11_METER_NTC_L_WARN3, + S2MPG11_METER_NTC_L_WARN4, + S2MPG11_METER_NTC_L_WARN5, + S2MPG11_METER_NTC_L_WARN6, + S2MPG11_METER_NTC_L_WARN7, + S2MPG11_METER_NTC_H_WARN0, + S2MPG11_METER_NTC_H_WARN1, + S2MPG11_METER_NTC_H_WARN2, + S2MPG11_METER_NTC_H_WARN3, + S2MPG11_METER_NTC_H_WARN4, + S2MPG11_METER_NTC_H_WARN5, + S2MPG11_METER_NTC_H_WARN6, + S2MPG11_METER_NTC_H_WARN7, + S2MPG11_METER_PWR_HYS1, + S2MPG11_METER_PWR_HYS2, + S2MPG11_METER_PWR_HYS3, + S2MPG11_METER_PWR_HYS4, + S2MPG11_METER_NTC_HYS1, + S2MPG11_METER_NTC_HYS2, + S2MPG11_METER_NTC_HYS3, + S2MPG11_METER_NTC_HYS4, + /* Nothing @ 0x3f */ + S2MPG11_METER_ACC_DATA_CH0_1 =3D 0x40, + S2MPG11_METER_ACC_DATA_CH0_2, + S2MPG11_METER_ACC_DATA_CH0_3, + S2MPG11_METER_ACC_DATA_CH0_4, + S2MPG11_METER_ACC_DATA_CH0_5, + S2MPG11_METER_ACC_DATA_CH0_6, + S2MPG11_METER_ACC_DATA_CH1_1, + S2MPG11_METER_ACC_DATA_CH1_2, + S2MPG11_METER_ACC_DATA_CH1_3, + S2MPG11_METER_ACC_DATA_CH1_4, + S2MPG11_METER_ACC_DATA_CH1_5, + S2MPG11_METER_ACC_DATA_CH1_6, + S2MPG11_METER_ACC_DATA_CH2_1, + S2MPG11_METER_ACC_DATA_CH2_2, + S2MPG11_METER_ACC_DATA_CH2_3, + S2MPG11_METER_ACC_DATA_CH2_4, + S2MPG11_METER_ACC_DATA_CH2_5, + S2MPG11_METER_ACC_DATA_CH2_6, + S2MPG11_METER_ACC_DATA_CH3_1, + S2MPG11_METER_ACC_DATA_CH3_2, + S2MPG11_METER_ACC_DATA_CH3_3, + S2MPG11_METER_ACC_DATA_CH3_4, + S2MPG11_METER_ACC_DATA_CH3_5, + S2MPG11_METER_ACC_DATA_CH3_6, + S2MPG11_METER_ACC_DATA_CH4_1, + S2MPG11_METER_ACC_DATA_CH4_2, + S2MPG11_METER_ACC_DATA_CH4_3, + S2MPG11_METER_ACC_DATA_CH4_4, + S2MPG11_METER_ACC_DATA_CH4_5, + S2MPG11_METER_ACC_DATA_CH4_6, + S2MPG11_METER_ACC_DATA_CH5_1, + S2MPG11_METER_ACC_DATA_CH5_2, + S2MPG11_METER_ACC_DATA_CH5_3, + S2MPG11_METER_ACC_DATA_CH5_4, + S2MPG11_METER_ACC_DATA_CH5_5, + S2MPG11_METER_ACC_DATA_CH5_6, + S2MPG11_METER_ACC_DATA_CH6_1, + S2MPG11_METER_ACC_DATA_CH6_2, + S2MPG11_METER_ACC_DATA_CH6_3, + S2MPG11_METER_ACC_DATA_CH6_4, + S2MPG11_METER_ACC_DATA_CH6_5, + S2MPG11_METER_ACC_DATA_CH6_6, + S2MPG11_METER_ACC_DATA_CH7_1, + S2MPG11_METER_ACC_DATA_CH7_2, + S2MPG11_METER_ACC_DATA_CH7_3, + S2MPG11_METER_ACC_DATA_CH7_4, + S2MPG11_METER_ACC_DATA_CH7_5, + S2MPG11_METER_ACC_DATA_CH7_6, + S2MPG11_METER_ACC_COUNT_1, + S2MPG11_METER_ACC_COUNT_2, + S2MPG11_METER_ACC_COUNT_3, + S2MPG11_METER_LPF_DATA_CH0_1, + S2MPG11_METER_LPF_DATA_CH0_2, + S2MPG11_METER_LPF_DATA_CH0_3, + S2MPG11_METER_LPF_DATA_CH1_1, + S2MPG11_METER_LPF_DATA_CH1_2, + S2MPG11_METER_LPF_DATA_CH1_3, + S2MPG11_METER_LPF_DATA_CH2_1, + S2MPG11_METER_LPF_DATA_CH2_2, + S2MPG11_METER_LPF_DATA_CH2_3, + S2MPG11_METER_LPF_DATA_CH3_1, + S2MPG11_METER_LPF_DATA_CH3_2, + S2MPG11_METER_LPF_DATA_CH3_3, + S2MPG11_METER_LPF_DATA_CH4_1, + S2MPG11_METER_LPF_DATA_CH4_2, + S2MPG11_METER_LPF_DATA_CH4_3, + S2MPG11_METER_LPF_DATA_CH5_1, + S2MPG11_METER_LPF_DATA_CH5_2, + S2MPG11_METER_LPF_DATA_CH5_3, + S2MPG11_METER_LPF_DATA_CH6_1, + S2MPG11_METER_LPF_DATA_CH6_2, + S2MPG11_METER_LPF_DATA_CH6_3, + S2MPG11_METER_LPF_DATA_CH7_1, + S2MPG11_METER_LPF_DATA_CH7_2, + S2MPG11_METER_LPF_DATA_CH7_3, + /* Nothing @ 0x8b 0x8c */ + S2MPG11_METER_LPF_DATA_NTC0_1 =3D 0x8d, + S2MPG11_METER_LPF_DATA_NTC0_2, + S2MPG11_METER_LPF_DATA_NTC1_1, + S2MPG11_METER_LPF_DATA_NTC1_2, + S2MPG11_METER_LPF_DATA_NTC2_1, + S2MPG11_METER_LPF_DATA_NTC2_2, + S2MPG11_METER_LPF_DATA_NTC3_1, + S2MPG11_METER_LPF_DATA_NTC3_2, + S2MPG11_METER_LPF_DATA_NTC4_1, + S2MPG11_METER_LPF_DATA_NTC4_2, + S2MPG11_METER_LPF_DATA_NTC5_1, + S2MPG11_METER_LPF_DATA_NTC5_2, + S2MPG11_METER_LPF_DATA_NTC6_1, + S2MPG11_METER_LPF_DATA_NTC6_2, + S2MPG11_METER_LPF_DATA_NTC7_1, + S2MPG11_METER_LPF_DATA_NTC7_2, +}; + +/* S2MPG11 regulator IDs */ +enum s2mpg11_regulators { + S2MPG11_LDO1, + S2MPG11_LDO2, + S2MPG11_LDO3, + S2MPG11_LDO4, + S2MPG11_LDO5, + S2MPG11_LDO6, + S2MPG11_LDO7, + S2MPG11_LDO8, + S2MPG11_LDO9, + S2MPG11_LDO10, + S2MPG11_LDO11, + S2MPG11_LDO12, + S2MPG11_LDO13, + S2MPG11_LDO14, + S2MPG11_LDO15, + S2MPG11_BUCK1, + S2MPG11_BUCK2, + S2MPG11_BUCK3, + S2MPG11_BUCK4, + S2MPG11_BUCK5, + S2MPG11_BUCK6, + S2MPG11_BUCK7, + S2MPG11_BUCK8, + S2MPG11_BUCK9, + S2MPG11_BUCK10, + S2MPG11_BUCKD, + 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:04 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:53 +0000 Subject: [PATCH v4 10/20] regulator: add REGULATOR_LINEAR_VRANGE macro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-10-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 REGULATOR_LINEAR_VRANGE is similar to REGULATOR_LINEAR_RANGE, but allows a more natural declaration of a voltage range for a regulator, in that it expects the minimum and maximum values as voltages rather than as selectors. Using voltages arguably makes this macro easier to use by drivers and code using it can become easier to read compared to REGULATOR_LINEAR_RANGE. Signed-off-by: Andr=C3=A9 Draszik --- While this commit doesn't introduce any users, the upcoming s2mpg10 and s2mpg11 drivers are using it. v3: - new patch --- include/linux/regulator/driver.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/dri= ver.h index 978cf593b6624228fe1fd9c2a3e186b53ef172f8..977755db64c6dfaea7246067eab= 0d9a2971caa01 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -53,6 +53,11 @@ enum regulator_detection_severity { #define REGULATOR_LINEAR_RANGE(_min_uV, _min_sel, _max_sel, _step_uV) \ LINEAR_RANGE(_min_uV, _min_sel, _max_sel, _step_uV) =20 +/* Initialize struct linear_range using voltages, not selectors */ +#define REGULATOR_LINEAR_VRANGE(_offs_uV, _min_uV, _max_uV, _step_uV) \ + LINEAR_RANGE(_min_uV, ((_min_uV) - (_offs_uV)) / (_step_uV), \ + ((_max_uV) - (_offs_uV)) / (_step_uV), _step_uV) + /** * struct regulator_ops - regulator operations. * --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D76F533858B for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:04 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:54 +0000 Subject: [PATCH v4 11/20] regulator: s2mps11: drop two needless variable initialisations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-11-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 The initialisations being removed are needless, as both variables are being assigned values unconditionally further down. Additionally, doing this eager init here might lead to preventing the compiler from issuing a warning if a future code change actually forgets to assign a useful value in some code path. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 04ae9c6150bd5ae9dba47b9b3cfcfb62e4698b6d..1f51fbc6c7b6e158f9707c04d9f= 030b9eee5e842 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -1207,8 +1207,8 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) struct sec_pmic_dev *iodev =3D dev_get_drvdata(pdev->dev.parent); struct regulator_config config =3D { }; struct s2mps11_info *s2mps11; - unsigned int rdev_num =3D 0; - int i, ret =3D 0; + unsigned int rdev_num; + int i, ret; const struct regulator_desc *regulators; =20 s2mps11 =3D devm_kzalloc(&pdev->dev, sizeof(struct s2mps11_info), --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CAE933858F for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:05 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:55 +0000 Subject: [PATCH v4 12/20] regulator: s2mps11: use dev_err_probe() where appropriate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-12-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 dev_err_probe() exists to simplify code and harmonise error messages, there's no reason not to use it here. While at it, harmonise some error messages to add regulator name and ID like in other messages in this driver, and update messages to be more similar to other child-drivers of this PMIC (e.g. RTC). Reviewed-by: Krzysztof Kozlowski Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 1f51fbc6c7b6e158f9707c04d9f030b9eee5e842..30586e9884bfb998ff07e314881= 3344b307506c0 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -1249,9 +1249,9 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mpu05_regulators)); break; default: - dev_err(&pdev->dev, "Invalid device type: %u\n", - s2mps11->dev_type); - return -EINVAL; + return dev_err_probe(&pdev->dev, -ENODEV, + "Unsupported device type %d\n", + s2mps11->dev_type); } =20 s2mps11->ext_control_gpiod =3D devm_kcalloc(&pdev->dev, rdev_num, @@ -1290,21 +1290,20 @@ static int s2mps11_pmic_probe(struct platform_devic= e *pdev) devm_gpiod_unhinge(&pdev->dev, config.ena_gpiod); regulator =3D devm_regulator_register(&pdev->dev, ®ulators[i], &config); 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:05 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:56 +0000 Subject: [PATCH v4 13/20] regulator: s2mps11: place constants on right side of comparison tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-13-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 For the lines being changed, checkpatch reports: WARNING: Comparisons should place the constant on the right side of the= test Update the code accordingly. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Andr=C3=A9 Draszik --- v3: - new patch --- drivers/regulator/s2mps11.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 30586e9884bfb998ff07e3148813344b307506c0..8a36ab67b73e4151c7f67af0555= a6465ee1e7a04 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -1221,32 +1221,32 @@ static int s2mps11_pmic_probe(struct platform_devic= e *pdev) case S2MPS11X: rdev_num =3D ARRAY_SIZE(s2mps11_regulators); regulators =3D s2mps11_regulators; - BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps11_regulators)); + BUILD_BUG_ON(ARRAY_SIZE(s2mps11_regulators) > S2MPS_REGULATOR_MAX); break; case S2MPS13X: rdev_num =3D ARRAY_SIZE(s2mps13_regulators); regulators =3D s2mps13_regulators; - BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps13_regulators)); + BUILD_BUG_ON(ARRAY_SIZE(s2mps13_regulators) > S2MPS_REGULATOR_MAX); break; case S2MPS14X: rdev_num =3D ARRAY_SIZE(s2mps14_regulators); regulators =3D s2mps14_regulators; - BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps14_regulators)); + BUILD_BUG_ON(ARRAY_SIZE(s2mps14_regulators) > S2MPS_REGULATOR_MAX); break; case S2MPS15X: rdev_num =3D ARRAY_SIZE(s2mps15_regulators); regulators =3D s2mps15_regulators; - BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps15_regulators)); + BUILD_BUG_ON(ARRAY_SIZE(s2mps15_regulators) > S2MPS_REGULATOR_MAX); break; case S2MPU02: rdev_num =3D ARRAY_SIZE(s2mpu02_regulators); regulators =3D s2mpu02_regulators; - BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mpu02_regulators)); + BUILD_BUG_ON(ARRAY_SIZE(s2mpu02_regulators) > S2MPS_REGULATOR_MAX); break; case S2MPU05: rdev_num =3D ARRAY_SIZE(s2mpu05_regulators); regulators =3D s2mpu05_regulators; - BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mpu05_regulators)); + BUILD_BUG_ON(ARRAY_SIZE(s2mpu05_regulators) > S2MPS_REGULATOR_MAX); break; default: return dev_err_probe(&pdev->dev, -ENODEV, --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 160A933859C for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:06 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:57 +0000 Subject: [PATCH v4 14/20] regulator: s2mps11: update node parsing (allow -supply properties) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-14-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 For the upcoming S2MPG10 and S2MPG11 support, we need to be able to parse -supply properties in the PMIC's DT node. This currently doesn't work, because the code here currently points the regulator core at each individual regulator sub-node, and therefore the regulator core is unable to find the -supply properties. Update the code to simply let the regulator core handle all the parsing by adding the ::of_match and ::regulators_node members to all existing regulator descriptions, by adding ::of_parse_cb() to those regulators which support the vendor-specific samsung,ext-control-gpios to parse it (S2MPS14), and by dropping the explicit call to of_regulator_match(). Configuring the PMIC to respect the external control GPIOs via s2mps14_pmic_enable_ext_control() is left outside ::of_parse_cb() because the regulator core ignores errors other than -EPROBE_DEFER from that callback, while the code currently fails probe on register write errors and I believe it should stay that way. The driver can now avoid the devm_gpiod_unhinge() dance due to simpler error handling of GPIO descriptor acquisition. This change also has the advantage of reducing runtime memory consumption by quite a bit as the driver doesn't need to allocate a 'struct of_regulator_match' and a 'struct gpio_desc *' for each regulator for all PMICs as the regulator core does that. This saves 40+8 bytes on arm64 for each individual regulator on all supported PMICs (even on non-S2MPS14 due to currently unnecessarily allocating the extra memory unconditionally). With the upcoming S2MPG10 and S2MPG11 support, this amounts to 1640+328 and 1120+224 bytes respectively. Signed-off-by: Andr=C3=A9 Draszik --- v2: - fix commit message typos: s2mp1 -> s2mpg1 --- drivers/regulator/s2mps11.c | 192 ++++++++++++++++++++++++----------------= ---- 1 file changed, 105 insertions(+), 87 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 8a36ab67b73e4151c7f67af0555a6465ee1e7a04..88e21c90832a45547e5791b15cd= 1de274f81fed6 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -40,12 +40,6 @@ struct s2mps11_info { * the suspend mode was enabled. */ DECLARE_BITMAP(suspend_state, S2MPS_REGULATOR_MAX); - - /* - * Array (size: number of regulators) with GPIO-s for external - * sleep control. - */ - struct gpio_desc **ext_control_gpiod; }; =20 static int get_ramp_delay(int ramp_delay) @@ -244,7 +238,7 @@ static int s2mps11_regulator_enable(struct regulator_de= v *rdev) case S2MPS14X: if (test_bit(rdev_id, s2mps11->suspend_state)) val =3D S2MPS14_ENABLE_SUSPEND; - else if (s2mps11->ext_control_gpiod[rdev_id]) + else if (rdev->ena_pin) val =3D S2MPS14_ENABLE_EXT_CONTROL; else val =3D rdev->desc->enable_mask; @@ -334,6 +328,58 @@ static int s2mps11_regulator_set_suspend_disable(struc= t regulator_dev *rdev) rdev->desc->enable_mask, state); } =20 +static int s2mps11_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + const struct s2mps11_info *s2mps11 =3D config->driver_data; + struct gpio_desc *ena_gpiod; + int ret; + + if (s2mps11->dev_type =3D=3D S2MPS14X) + switch (desc->id) { + case S2MPS14_LDO10: + case S2MPS14_LDO11: + case S2MPS14_LDO12: + break; + + default: + return 0; + } + else + return 0; + + ena_gpiod =3D fwnode_gpiod_get_index(of_fwnode_handle(np), + "samsung,ext-control", 0, + GPIOD_OUT_HIGH | + GPIOD_FLAGS_BIT_NONEXCLUSIVE, + "s2mps11-regulator"); + if (IS_ERR(ena_gpiod)) { + ret =3D PTR_ERR(ena_gpiod); + + /* Ignore all errors except probe defer. */ + if (ret =3D=3D -EPROBE_DEFER) + return ret; + + if (ret =3D=3D -ENOENT) + dev_info(config->dev, + "No entry for control GPIO for %d/%s in node %pOF\n", + desc->id, desc->name, np); + else + dev_warn_probe(config->dev, ret, + "Failed to get control GPIO for %d/%s in node %pOF\n", + desc->id, desc->name, np); + return 0; + } + + dev_info(config->dev, "Using GPIO for ext-control over %d/%s\n", + desc->id, desc->name); + + config->ena_gpiod =3D ena_gpiod; + + return 0; +} + static const struct regulator_ops s2mps11_ldo_ops =3D { .list_voltage =3D regulator_list_voltage_linear, .map_voltage =3D regulator_map_voltage_linear, @@ -362,6 +408,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_ldo(num, step) { \ .name =3D "LDO"#num, \ .id =3D S2MPS11_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -378,6 +426,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_buck1_4(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS11_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -395,6 +445,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_buck5 { \ .name =3D "BUCK5", \ .id =3D S2MPS11_BUCK5, \ + .of_match =3D of_match_ptr("BUCK5"), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -412,6 +464,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_buck67810(num, min, step, min_sel, voltages= ) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS11_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -429,6 +483,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_buck9 { \ .name =3D "BUCK9", \ .id =3D S2MPS11_BUCK9, \ + .of_match =3D of_match_ptr("BUCK9"), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -502,6 +558,8 @@ static const struct regulator_ops s2mps14_reg_ops; #define regulator_desc_s2mps13_ldo(num, min, step, min_sel) { \ .name =3D "LDO"#num, \ .id =3D S2MPS13_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -518,6 +576,8 @@ static const struct regulator_ops s2mps14_reg_ops; #define regulator_desc_s2mps13_buck(num, min, step, min_sel) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS13_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -535,6 +595,8 @@ static const struct regulator_ops s2mps14_reg_ops; #define regulator_desc_s2mps13_buck7(num, min, step, min_sel) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS13_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -552,6 +614,8 @@ static const struct regulator_ops s2mps14_reg_ops; #define regulator_desc_s2mps13_buck8_10(num, min, step, min_sel) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS13_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -634,6 +698,9 @@ static const struct regulator_ops s2mps14_reg_ops =3D { #define regulator_desc_s2mps14_ldo(num, min, step) { \ .name =3D "LDO"#num, \ .id =3D S2MPS14_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .of_parse_cb =3D s2mps11_of_parse_cb, \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -649,6 +716,9 @@ static const struct regulator_ops s2mps14_reg_ops =3D { #define regulator_desc_s2mps14_buck(num, min, step, min_sel) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS14_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .of_parse_cb =3D s2mps11_of_parse_cb, \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -725,6 +795,8 @@ static const struct regulator_ops s2mps15_reg_buck_ops = =3D { #define regulator_desc_s2mps15_ldo(num, range) { \ .name =3D "LDO"#num, \ .id =3D S2MPS15_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps15_reg_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -740,6 +812,8 @@ static const struct regulator_ops s2mps15_reg_buck_ops = =3D { #define regulator_desc_s2mps15_buck(num, range) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS15_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps15_reg_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -835,60 +909,6 @@ static int s2mps14_pmic_enable_ext_control(struct s2mp= s11_info *s2mps11, rdev->desc->enable_mask, S2MPS14_ENABLE_EXT_CONTROL); } =20 -static void s2mps14_pmic_dt_parse_ext_control_gpio(struct platform_device = *pdev, - struct of_regulator_match *rdata, struct s2mps11_info *s2mps11) -{ - struct gpio_desc **gpio =3D s2mps11->ext_control_gpiod; - unsigned int i; - unsigned int valid_regulators[3] =3D { S2MPS14_LDO10, S2MPS14_LDO11, - S2MPS14_LDO12 }; - - for (i =3D 0; i < ARRAY_SIZE(valid_regulators); i++) { - unsigned int reg =3D valid_regulators[i]; - - if (!rdata[reg].init_data || !rdata[reg].of_node) - continue; - - gpio[reg] =3D devm_fwnode_gpiod_get(&pdev->dev, - of_fwnode_handle(rdata[reg].of_node), - "samsung,ext-control", - GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE, - "s2mps11-regulator"); - if (PTR_ERR(gpio[reg]) =3D=3D -ENOENT) - gpio[reg] =3D NULL; - else if (IS_ERR(gpio[reg])) { - dev_err(&pdev->dev, "Failed to get control GPIO for %d/%s\n", - reg, rdata[reg].name); - gpio[reg] =3D NULL; - continue; - } - if (gpio[reg]) - dev_dbg(&pdev->dev, "Using GPIO for ext-control over %d/%s\n", - reg, rdata[reg].name); - } -} - -static int s2mps11_pmic_dt_parse(struct platform_device *pdev, - struct of_regulator_match *rdata, struct s2mps11_info *s2mps11, - unsigned int rdev_num) -{ - struct device_node *reg_np; - - reg_np =3D of_get_child_by_name(pdev->dev.parent->of_node, "regulators"); - if (!reg_np) { - dev_err(&pdev->dev, "could not find regulators sub-node\n"); - return -EINVAL; - } - - of_regulator_match(&pdev->dev, reg_np, rdata, rdev_num); - if (s2mps11->dev_type =3D=3D S2MPS14X) - s2mps14_pmic_dt_parse_ext_control_gpio(pdev, rdata, s2mps11); - - of_node_put(reg_np); - - return 0; -} - static int s2mpu02_set_ramp_delay(struct regulator_dev *rdev, int ramp_del= ay) { unsigned int ramp_val, ramp_shift, ramp_reg; @@ -946,6 +966,8 @@ static const struct regulator_ops s2mpu02_buck_ops =3D { #define regulator_desc_s2mpu02_ldo1(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -961,6 +983,8 @@ static const struct regulator_ops s2mpu02_buck_ops =3D { #define regulator_desc_s2mpu02_ldo2(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -976,6 +1000,8 @@ static const struct regulator_ops s2mpu02_buck_ops =3D= { #define regulator_desc_s2mpu02_ldo3(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -991,6 +1017,8 @@ static const struct regulator_ops s2mpu02_buck_ops =3D= { #define regulator_desc_s2mpu02_ldo4(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1006,6 +1034,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_ldo5(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1022,6 +1052,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_buck1234(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPU02_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1038,6 +1070,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_buck5(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPU02_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1054,6 +1088,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_buck6(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPU02_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1070,6 +1106,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_buck7(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPU02_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1125,6 +1163,8 @@ static const struct regulator_desc s2mpu02_regulators= [] =3D { #define regulator_desc_s2mpu05_ldo_reg(num, min, step, reg) { \ .name =3D "ldo"#num, \ .id =3D S2MPU05_LDO##num, \ + .of_match =3D of_match_ptr("ldo"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1156,6 +1196,8 @@ static const struct regulator_desc s2mpu02_regulators= [] =3D { #define regulator_desc_s2mpu05_buck(num, which) { \ .name =3D "buck"#num, \ .id =3D S2MPU05_BUCK##num, \ + .of_match =3D of_match_ptr("buck"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1254,22 +1296,7 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) s2mps11->dev_type); } =20 - s2mps11->ext_control_gpiod =3D devm_kcalloc(&pdev->dev, rdev_num, - sizeof(*s2mps11->ext_control_gpiod), GFP_KERNEL); - if (!s2mps11->ext_control_gpiod) - return -ENOMEM; - - struct of_regulator_match *rdata __free(kfree) =3D - kcalloc(rdev_num, sizeof(*rdata), GFP_KERNEL); - if (!rdata) - return -ENOMEM; - - for (i =3D 0; i < rdev_num; i++) - rdata[i].name =3D regulators[i].name; - - ret =3D s2mps11_pmic_dt_parse(pdev, rdata, s2mps11, rdev_num); - if (ret) - return ret; + device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent); =20 platform_set_drvdata(pdev, s2mps11); =20 @@ -1279,15 +1306,6 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) for (i =3D 0; i < rdev_num; i++) { struct regulator_dev *regulator; =20 - config.init_data =3D rdata[i].init_data; - config.of_node =3D rdata[i].of_node; - config.ena_gpiod =3D s2mps11->ext_control_gpiod[i]; - /* - * Hand the GPIO descriptor management over to the regulator - * core, remove it from devres management. - */ - if (config.ena_gpiod) - devm_gpiod_unhinge(&pdev->dev, config.ena_gpiod); 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:06 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:58 +0000 Subject: [PATCH v4 15/20] regulator: s2mps11: refactor handling of external rail control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-15-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Refactor s2mps14_pmic_enable_ext_control() and s2mps11_of_parse_cb() slightly as a preparation for adding S2MPG10 and S2MPG11 support, as both of those PMICs also support control of rails via GPIOs. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 86 ++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 57 insertions(+), 29 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 88e21c90832a45547e5791b15cd1de274f81fed6..bb0a4f35ef47551f7171321fdde= 2c0202ce86ede 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -328,27 +328,13 @@ static int s2mps11_regulator_set_suspend_disable(stru= ct regulator_dev *rdev) rdev->desc->enable_mask, state); } =20 -static int s2mps11_of_parse_cb(struct device_node *np, - const struct regulator_desc *desc, - struct regulator_config *config) +static int s2mps11_of_parse_gpiod(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) { - const struct s2mps11_info *s2mps11 =3D config->driver_data; struct gpio_desc *ena_gpiod; int ret; =20 - if (s2mps11->dev_type =3D=3D S2MPS14X) - switch (desc->id) { - case S2MPS14_LDO10: - case S2MPS14_LDO11: - case S2MPS14_LDO12: - break; - - default: - return 0; - } - else - return 0; - ena_gpiod =3D fwnode_gpiod_get_index(of_fwnode_handle(np), "samsung,ext-control", 0, GPIOD_OUT_HIGH | @@ -380,6 +366,28 @@ static int s2mps11_of_parse_cb(struct device_node *np, return 0; } =20 +static int s2mps11_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + const struct s2mps11_info *s2mps11 =3D config->driver_data; + + if (s2mps11->dev_type =3D=3D S2MPS14X) + switch (desc->id) { + case S2MPS14_LDO10: + case S2MPS14_LDO11: + case S2MPS14_LDO12: + break; + + default: + return 0; + } + else + return 0; + + return s2mps11_of_parse_gpiod(np, desc, config); +} + static const struct regulator_ops s2mps11_ldo_ops =3D { .list_voltage =3D regulator_list_voltage_linear, .map_voltage =3D regulator_map_voltage_linear, @@ -903,10 +911,16 @@ static const struct regulator_desc s2mps15_regulators= [] =3D { }; =20 static int s2mps14_pmic_enable_ext_control(struct s2mps11_info *s2mps11, - struct regulator_dev *rdev) + struct regulator_dev *rdev) { - return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, - rdev->desc->enable_mask, S2MPS14_ENABLE_EXT_CONTROL); + int ret =3D regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, + rdev->desc->enable_mask, + S2MPS14_ENABLE_EXT_CONTROL); + if (ret < 0) + return dev_err_probe(rdev_get_dev(rdev), ret, + "failed to enable GPIO control over %d/%s\n", + rdev->desc->id, rdev->desc->name); + return 0; } =20 static int s2mpu02_set_ramp_delay(struct regulator_dev *rdev, int ramp_del= ay) @@ -1244,6 +1258,26 @@ static const struct regulator_desc s2mpu05_regulator= s[] =3D { regulator_desc_s2mpu05_buck45(5), }; =20 +static int s2mps11_handle_ext_control(struct s2mps11_info *s2mps11, + struct regulator_dev *rdev) +{ + int ret; + + switch (s2mps11->dev_type) { + case S2MPS14X: + if (!rdev->ena_pin) + return 0; + + ret =3D s2mps14_pmic_enable_ext_control(s2mps11, rdev); + break; + + default: + return 0; + } + + return ret; +} + static int s2mps11_pmic_probe(struct platform_device *pdev) { struct sec_pmic_dev *iodev =3D dev_get_drvdata(pdev->dev.parent); @@ -1314,15 +1348,9 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) regulators[i].id, regulators[i].name); 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:07 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:28:59 +0000 Subject: [PATCH v4 16/20] regulator: s2mps11: add S2MPG10 regulator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-16-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The S2MPG10 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, RTC, clock outputs, and additional GPIO interfaces. It has 10 buck and 31 LDO rails. Several of these can either be controlled via software (register writes) or via external signals, in particular by: * one out of several input pins connected to a main processor's: * GPIO pins * other pins that are e.g. firmware- or power-domain-controlled without explicit driver intervention * a combination of input pins and register writes. Control via input pins allows PMIC rails to be controlled by firmware, e.g. during standby/suspend, or as part of power domain handling where otherwise that would not be possible. Additionally toggling a pin is faster than register writes, and it also allows the PMIC to ensure that any necessary timing requirements between rails are respected automatically if multiple rails are to be enabled or disabled quasi simultaneously. This commit implements support for all these rails and control combinations. Additional data needs to be stored for each regulator, e.g. the input pin for external control, or a rail-specific ramp-rate for when enabling a buck-rail. Therefore, probe() is updated slightly to make that possible. Note1: For an externally controlled rail, the regulator_ops provide an empty ::enable() and no ::disable() implementations, even though Linux can not enable the rail and one might think ::enable could be NULL. Without ops->enable(), the regulator core will assume enabling such a rail failed, though, and in turn never add a reference to its parent (supplier) rail. Once a different (Linux-controlled) sibling (consumer) rail on that same parent rail gets disabled, the parent gets disabled (cutting power to the externally controlled rail although it should stay on), and the system will misbehave. Note2: The rails are instantiated as separate driver instances for each rail, because S2MPG10 is typically used with an S2MPG11 sub-PMIC where some bucks of one typically supply at least some of the LDOs of the other. Using separate instances avoids issues around circular dependencies which occur otherwise. Note3: While external control via input pins appears to exist on other versions of this PMIC, there is more flexibility in this version, in particular there is a selection of input pins to choose from for each rail (which must therefore be configured accordingly if in use), whereas other versions don't have this flexibility. Signed-off-by: Andr=C3=A9 Draszik --- v3: - one instance per actual rail, not per rail type (LDO or buck) - use REGULATOR_LINEAR_VRANGE macro - sort s2mpg10 bucks before LDOs throughout (alphabetic ordering) - LDO 1 and 7 also support setting a ramp rate - add ::enable() to ops for signal-controlled rails and update commit message detailing why - more details around signal controlled rails in commit message - switch to 'enable-gpios' instead of samsung,ext-control-gpios for OS-controlled GPIOs (Krzysztof) v2: - move assignment of ::of_parse_cb in regulator_desc_s2mpg10_buck() to match order of struct definition --- drivers/regulator/s2mps11.c | 599 ++++++++++++++++++++++++++++++++= +++- include/linux/mfd/samsung/s2mpg10.h | 24 ++ 2 files changed, 617 insertions(+), 6 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index bb0a4f35ef47551f7171321fdde2c0202ce86ede..aff85138fa5da4cff83bdec5cdb= 3086a58afc7ce 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -3,6 +3,7 @@ // Copyright (c) 2012-2014 Samsung Electronics Co., Ltd // http://www.samsung.com =20 +#include #include #include #include @@ -15,7 +16,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -23,6 +26,11 @@ #include #include =20 +enum { + S2MPG10_REGULATOR_OPS_STD, + S2MPG10_REGULATOR_OPS_EXTCONTROL, +}; + /* The highest number of possible regulators for supported devices. */ #define S2MPS_REGULATOR_MAX S2MPS13_REGULATOR_MAX struct s2mps11_info { @@ -42,6 +50,21 @@ struct s2mps11_info { DECLARE_BITMAP(suspend_state, S2MPS_REGULATOR_MAX); }; =20 +#define to_s2mpg10_regulator_desc(x) container_of((x), struct s2mpg10_regu= lator_desc, desc) + +struct s2mpg10_regulator_desc { + struct regulator_desc desc; + + /* Ramp rate during enable, valid for bucks only. */ + unsigned int enable_ramp_rate; + + /* Registers for external control of rail. */ + unsigned int pctrlsel_reg; + unsigned int pctrlsel_mask; + /* Populated from DT. */ + unsigned int pctrlsel_val; +}; + static int get_ramp_delay(int ramp_delay) { unsigned char cnt =3D 0; @@ -329,14 +352,14 @@ static int s2mps11_regulator_set_suspend_disable(stru= ct regulator_dev *rdev) } =20 static int s2mps11_of_parse_gpiod(struct device_node *np, + const char *con_id, const struct regulator_desc *desc, struct regulator_config *config) { struct gpio_desc *ena_gpiod; int ret; =20 - ena_gpiod =3D fwnode_gpiod_get_index(of_fwnode_handle(np), - "samsung,ext-control", 0, + ena_gpiod =3D fwnode_gpiod_get_index(of_fwnode_handle(np), con_id, 0, GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE, "s2mps11-regulator"); @@ -385,9 +408,533 @@ static int s2mps11_of_parse_cb(struct device_node *np, else return 0; =20 - return s2mps11_of_parse_gpiod(np, desc, config); + return s2mps11_of_parse_gpiod(np, "samsung,ext-control", desc, config); +} + +static int s2mpg10_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + const struct s2mps11_info *s2mps11 =3D config->driver_data; + struct s2mpg10_regulator_desc *s2mpg10_desc =3D to_s2mpg10_regulator_desc= (desc); + static const u32 ext_control_s2mpg10[] =3D { + [S2MPG10_EXTCTRL_PWREN] =3D S2MPG10_PCTRLSEL_PWREN, + [S2MPG10_EXTCTRL_PWREN_MIF] =3D S2MPG10_PCTRLSEL_PWREN_MIF, + [S2MPG10_EXTCTRL_AP_ACTIVE_N] =3D S2MPG10_PCTRLSEL_AP_ACTIVE_N, + [S2MPG10_EXTCTRL_CPUCL1_EN] =3D S2MPG10_PCTRLSEL_CPUCL1_EN, + [S2MPG10_EXTCTRL_CPUCL1_EN2] =3D S2MPG10_PCTRLSEL_CPUCL1_EN2, + [S2MPG10_EXTCTRL_CPUCL2_EN] =3D S2MPG10_PCTRLSEL_CPUCL2_EN, + [S2MPG10_EXTCTRL_CPUCL2_EN2] =3D S2MPG10_PCTRLSEL_CPUCL2_EN2, + [S2MPG10_EXTCTRL_TPU_EN] =3D S2MPG10_PCTRLSEL_TPU_EN, + [S2MPG10_EXTCTRL_TPU_EN2] =3D S2MPG10_PCTRLSEL_TPU_EN2, + [S2MPG10_EXTCTRL_TCXO_ON] =3D S2MPG10_PCTRLSEL_TCXO_ON, + [S2MPG10_EXTCTRL_TCXO_ON2] =3D S2MPG10_PCTRLSEL_TCXO_ON2, + [S2MPG10_EXTCTRL_LDO20M_EN2] =3D S2MPG10_PCTRLSEL_LDO20M_EN2, + [S2MPG10_EXTCTRL_LDO20M_EN] =3D S2MPG10_PCTRLSEL_LDO20M_EN, + }; + u32 ext_control; + + if (s2mps11->dev_type !=3D S2MPG10) + return 0; + + if (of_property_read_u32(np, "samsung,ext-control", &ext_control)) + return 0; + + switch (s2mps11->dev_type) { + case S2MPG10: + switch (desc->id) { + case S2MPG10_BUCK1 ... S2MPG10_BUCK7: + case S2MPG10_BUCK10: + case S2MPG10_LDO3 ... S2MPG10_LDO19: + if (ext_control > S2MPG10_EXTCTRL_TCXO_ON2) + return -EINVAL; + break; + + case S2MPG10_LDO20: + if (ext_control < S2MPG10_EXTCTRL_LDO20M_EN2 || + ext_control > S2MPG10_EXTCTRL_LDO20M_EN) + return -EINVAL; + break; + + default: + return -EINVAL; + } + + if (ext_control > ARRAY_SIZE(ext_control_s2mpg10)) + return -EINVAL; + ext_control =3D ext_control_s2mpg10[ext_control]; + break; + + default: + return -EINVAL; + } + + /* + * If the regulator should be configured for external control, then: + * 1) the PCTRLSELx register needs to be set accordingly + * 2) regulator_desc::enable_val needs to be: + * a) updated and + * b) written to the hardware + * 3) we switch to the ::ops that provide an empty ::enable() and no + * ::disable() implementations + * + * Points 1) and 2b) will be handled in _probe(), after + * devm_regulator_register() returns, so that we can properly act on + * failures, since the regulator core ignores most return values from + * this parse callback. + */ + s2mpg10_desc->pctrlsel_val =3D ext_control; + s2mpg10_desc->pctrlsel_val <<=3D (ffs(s2mpg10_desc->pctrlsel_mask) - 1); + + s2mpg10_desc->desc.enable_val =3D S2MPG10_PMIC_CTRL_ENABLE_EXT; + s2mpg10_desc->desc.enable_val <<=3D (ffs(desc->enable_mask) - 1); + + ++s2mpg10_desc->desc.ops; + + return s2mps11_of_parse_gpiod(np, "enable", desc, config); +} + +static int s2mpg10_enable_ext_control(struct s2mps11_info *s2mps11, + struct regulator_dev *rdev) +{ + const struct s2mpg10_regulator_desc *s2mpg10_desc; + int ret; + + switch (s2mps11->dev_type) { + case S2MPG10: + s2mpg10_desc =3D to_s2mpg10_regulator_desc(rdev->desc); + break; + + default: + return 0; + } + + ret =3D regmap_update_bits(rdev_get_regmap(rdev), + s2mpg10_desc->pctrlsel_reg, + s2mpg10_desc->pctrlsel_mask, + s2mpg10_desc->pctrlsel_val); + if (ret) + return dev_err_probe(rdev_get_dev(rdev), ret, + "failed to configure pctrlsel for %s\n", + rdev->desc->name); + + /* + * When using external control, the enable bit of the regulator still + * needs to be set. The actual state will still be determined by the + * external signal. + */ + ret =3D regulator_enable_regmap(rdev); + if (ret) + return dev_err_probe(rdev_get_dev(rdev), ret, + "failed to enable regulator %s\n", + rdev->desc->name); + + return 0; +} + +static int s2mpg10_regulator_enable_nop(struct regulator_dev *rdev) +{ + /* + * We need to provide this, otherwise the regulator core's enable on + * this regulator will return a failure and subsequently disable our + * parent regulator. + */ + return 0; +} + +static int s2mpg10_regulator_buck_enable_time(struct regulator_dev *rdev) +{ + const struct s2mpg10_regulator_desc * const s2mpg10_desc =3D + to_s2mpg10_regulator_desc(rdev->desc); + const struct regulator_ops * const ops =3D rdev->desc->ops; + int vsel, curr_uV; + + vsel =3D ops->get_voltage_sel(rdev); + if (vsel < 0) + return vsel; + + curr_uV =3D ops->list_voltage(rdev, vsel); + if (curr_uV < 0) + return curr_uV; + + return (rdev->desc->enable_time + + DIV_ROUND_UP(curr_uV, s2mpg10_desc->enable_ramp_rate)); } =20 +static int s2mpg10_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, + int old_uV, int new_uV) +{ + unsigned int ramp_reg, ramp_sel, ramp_rate; + int ret; + + if (old_uV =3D=3D new_uV) + return 0; + + ramp_reg =3D rdev->desc->ramp_reg; + if (old_uV > new_uV) + /* The downwards ramp is at a different offset. */ + ramp_reg +=3D S2MPG10_PMIC_DVS_RAMP4 - S2MPG10_PMIC_DVS_RAMP1; + + ret =3D regmap_read(rdev->regmap, ramp_reg, &ramp_sel); + if (ret) + return ret; + + ramp_sel &=3D rdev->desc->ramp_mask; + ramp_sel >>=3D ffs(rdev->desc->ramp_mask) - 1; + if (ramp_sel >=3D rdev->desc->n_ramp_values || + !rdev->desc->ramp_delay_table) + return -EINVAL; + + ramp_rate =3D rdev->desc->ramp_delay_table[ramp_sel]; + + return DIV_ROUND_UP(abs(new_uV - old_uV), ramp_rate); +} + +/* + * We assign both, ::set_voltage_time() and ::set_voltage_time_sel(), beca= use + * only if the latter is !=3D NULL, the regulator core will call neither d= uring + * DVS if the regulator is disabled. If the latter is NULL, the core always + * calls the ::set_voltage_time() callback, which would give incorrect res= ults + * if the regulator is off. + * At the same time, we do need ::set_voltage_time() due to differing upwa= rds + * and downwards ramps and we can not make that code dependent on the regu= lator + * enable state, as that would break regulator_set_voltage_time() which + * expects a correct result no matter the enable state. + */ +static const struct regulator_ops s2mpg10_reg_buck_ops[] =3D { + [S2MPG10_REGULATOR_OPS_STD] =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .enable_time =3D s2mpg10_regulator_buck_enable_time, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time =3D s2mpg10_regulator_buck_set_voltage_time, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + }, + [S2MPG10_REGULATOR_OPS_EXTCONTROL] =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .enable =3D s2mpg10_regulator_enable_nop, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time =3D s2mpg10_regulator_buck_set_voltage_time, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + } +}; + +#define s2mpg10_buck_to_ramp_mask(n) (GENMASK(1, 0) << (((n) % 4) * 2)) + +/* + * The ramp_delay during enable is fixed (12.5mV/=CE=BCs), while the ramp = during + * DVS can be adjusted. Linux can adjust the ramp delay via DT, in which c= ase + * the regulator core will modify the regulator's constraints and call our + * .set_ramp_delay() which updates the DVS ramp in ramp_reg. + * For enable, our .enable_time() unconditionally uses enable_ramp_rate + * (12.5mV/=CE=BCs) while our ::set_voltage_time() takes the value in ramp= _reg + * into account. + */ +#define regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg) { \ + .name =3D "buck"#_num "m", \ + .supply_name =3D "vinb"#_num "m", \ + .of_match =3D of_match_ptr("buck"#_num "m"), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .of_parse_cb =3D s2mpg10_of_parse_cb, \ + .id =3D S2MPG10_BUCK##_num, \ + .ops =3D &s2mpg10_reg_buck_ops[0], \ + .type =3D REGULATOR_VOLTAGE, \ + .owner =3D THIS_MODULE, \ + .linear_ranges =3D _vrange, \ + .n_linear_ranges =3D ARRAY_SIZE(_vrange), \ + .n_voltages =3D _vrange##_count, \ + .vsel_reg =3D S2MPG10_PMIC_B##_num##M_OUT1, \ + .vsel_mask =3D 0xff, \ + .enable_reg =3D S2MPG10_PMIC_B##_num##M_CTRL, \ + .enable_mask =3D GENMASK(7, 6), \ + .ramp_reg =3D S2MPG10_PMIC_##_r_reg, \ + .ramp_mask =3D s2mpg10_buck_to_ramp_mask(S2MPG10_BUCK##_num \ + - S2MPG10_BUCK1), \ + .ramp_delay_table =3D s2mpg10_buck_ramp_table, \ + .n_ramp_values =3D ARRAY_SIZE(s2mpg10_buck_ramp_table), \ + .enable_time =3D 30, /* + V/enable_ramp_rate */ \ +} + +#define s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg) \ + .desc =3D regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg), \ + .enable_ramp_rate =3D 12500 + +#define s2mpg10_regulator_desc_buck_gpio(_num, _vrange, _r_reg, \ + _pc_reg, _pc_mask) \ + [S2MPG10_BUCK##_num] =3D { \ + s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg), \ + .pctrlsel_reg =3D S2MPG10_PMIC_##_pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +#define s2mpg10_regulator_desc_buck(_num, _vrange, _r_reg) \ + [S2MPG10_BUCK##_num] =3D { \ + s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg), \ + } + +/* ops for S2MPG1x LDO regulators without ramp control */ +static const struct regulator_ops s2mpg10_reg_ldo_ops[] =3D { + [S2MPG10_REGULATOR_OPS_STD] =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + }, + [S2MPG10_REGULATOR_OPS_EXTCONTROL] =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .enable =3D s2mpg10_regulator_enable_nop, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + } +}; + +/* ops for S2MPG1x LDO regulators that have ramp control */ +static const struct regulator_ops s2mpg10_reg_ldo_ramp_ops[] =3D { + [S2MPG10_REGULATOR_OPS_STD] =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + }, + [S2MPG10_REGULATOR_OPS_EXTCONTROL] =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .enable =3D s2mpg10_regulator_enable_nop, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + } +}; + +#define regulator_desc_s2mpg10_ldo_cmn(_num, _supply, _ops, _vrange, \ + _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz) { \ + .name =3D "ldo"#_num "m", \ + .supply_name =3D _supply, \ + .of_match =3D of_match_ptr("ldo"#_num "m"), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .of_parse_cb =3D s2mpg10_of_parse_cb, \ + .id =3D S2MPG10_LDO##_num, \ + .ops =3D &(_ops)[0], \ + .type =3D REGULATOR_VOLTAGE, \ + .owner =3D THIS_MODULE, \ + .linear_ranges =3D _vrange, \ + .n_linear_ranges =3D ARRAY_SIZE(_vrange), \ + .n_voltages =3D _vrange##_count, \ + .vsel_reg =3D S2MPG10_PMIC_L##_num##M_##_vsel_reg_sfx, \ + .vsel_mask =3D _vsel_mask, \ + .enable_reg =3D S2MPG10_PMIC_##_en_reg, \ + .enable_mask =3D _en_mask, \ + .ramp_delay =3D _ramp_delay, \ + .ramp_reg =3D _r_reg, \ + .ramp_mask =3D _r_mask, \ + .ramp_delay_table =3D _r_table, \ + .n_ramp_values =3D _r_table_sz, \ + .enable_time =3D 130, /* startup 20+-10 + ramp 30..100=CE=BCs */ \ +} + +#define s2mpg10_regulator_desc_ldo_cmn(_num, _supply, _ops, _vrange, \ + _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz, \ + _pc_reg, _pc_mask) \ + [S2MPG10_LDO##_num] =3D { \ + .desc =3D regulator_desc_s2mpg10_ldo_cmn(_num, _supply, \ + _ops, \ + _vrange, _vsel_reg_sfx, _vsel_mask, \ + _en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, \ + _r_table_sz), \ + .pctrlsel_reg =3D _pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +/* standard LDO via LxM_CTRL */ +#define s2mpg10_regulator_desc_ldo(_num, _supply, _vrange) \ + s2mpg10_regulator_desc_ldo_cmn(_num, _supply, \ + s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \ + L##_num##M_CTRL, BIT(7), \ + 0, 0, 0, NULL, 0, \ + 0, 0) + +/* standard LDO but possibly GPIO controlled */ +#define s2mpg10_regulator_desc_ldo_gpio(_num, _supply, _vrange, \ + _pc_reg, _pc_mask) \ + s2mpg10_regulator_desc_ldo_cmn(_num, _supply, \ + s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \ + L##_num##M_CTRL, GENMASK(7, 6), \ + 0, 0, 0, NULL, 0, \ + S2MPG10_PMIC_##_pc_reg, _pc_mask) + +/* LDO with ramp support and possibly GPIO controlled */ +#define s2mpg10_regulator_desc_ldo_ramp(_num, _supply, _vrange, \ + _en_mask, _r_reg, _pc_reg, _pc_mask) \ + s2mpg10_regulator_desc_ldo_cmn(_num, _supply, \ + s2mpg10_reg_ldo_ramp_ops, _vrange, CTRL1, GENMASK(6, 0), \ + LDO_CTRL2, _en_mask, \ + 6250, S2MPG10_PMIC_##_r_reg, GENMASK(1, 0), \ + s2mpg10_ldo_ramp_table, \ + ARRAY_SIZE(s2mpg10_ldo_ramp_table), \ + S2MPG10_PMIC_##_pc_reg, _pc_mask) + +#define S2MPG10_VOLTAGE_RANGE(_prefix, _idx, _offs_uV, _min_uV, \ + _max_uV, _step_uV) \ +static const struct linear_range _prefix##_vranges##_idx[] =3D { \ + REGULATOR_LINEAR_VRANGE(_offs_uV, _min_uV, _max_uV, _step_uV) \ +}; \ +static const unsigned int _prefix##_vranges##_idx##_count =3D \ + ((((_max_uV) - (_offs_uV)) / (_step_uV)) + 1) + +/* voltage range for s2mpg10 BUCK 1, 2, 3, 4, 5, 7, 8, 9, 10 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_buck, 1, 200000, 450000, 1300000, STEP_6_25_= MV); + +/* voltage range for s2mpg10 BUCK 6 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_buck, 6, 200000, 450000, 1350000, STEP_6_25_= MV); + +static const unsigned int s2mpg10_buck_ramp_table[] =3D { + 6250, 12500, 25000 +}; + +/* voltage range for s2mpg10 LDO 1, 11, 12 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 1, 300000, 700000, 1300000, STEP_12_5_M= V); + +/* voltage range for s2mpg10 LDO 2, 4, 9, 14, 18, 19, 20, 23, 25, 29, 30, = 31 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 2, 700000, 1600000, 1950000, STEP_25_MV= ); + +/* voltage range for s2mpg10 LDO 3, 5, 6, 8, 16, 17, 24, 28 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 3, 725000, 725000, 1300000, STEP_12_5_M= V); + +/* voltage range for s2mpg10 LDO 7 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 7, 300000, 450000, 1300000, STEP_12_5_M= V); + +/* voltage range for s2mpg10 LDO 13, 15 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 13, 300000, 450000, 950000, STEP_12_5_M= V); + +/* voltage range for s2mpg10 LDO 10 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 10, 1800000, 1800000, 3350000, STEP_25_= MV); + +/* voltage range for s2mpg10 LDO 21, 22, 26, 27 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 21, 1800000, 2500000, 3300000, STEP_25_= MV); + +/* possible ramp values for s2mpg10 LDO 1, 7, 11, 12, 13, 15 */ +static const unsigned int s2mpg10_ldo_ramp_table[] =3D { + 6250, 12500 +}; + +static const struct s2mpg10_regulator_desc s2mpg10_regulators[] =3D { + s2mpg10_regulator_desc_buck_gpio(1, s2mpg10_buck_vranges1, DVS_RAMP1, + PCTRLSEL1, GENMASK(3, 0)), + s2mpg10_regulator_desc_buck_gpio(2, s2mpg10_buck_vranges1, DVS_RAMP1, + PCTRLSEL1, GENMASK(7, 4)), + s2mpg10_regulator_desc_buck_gpio(3, s2mpg10_buck_vranges1, DVS_RAMP1, + PCTRLSEL2, GENMASK(3, 0)), + s2mpg10_regulator_desc_buck_gpio(4, s2mpg10_buck_vranges1, DVS_RAMP1, + PCTRLSEL2, GENMASK(7, 4)), + s2mpg10_regulator_desc_buck_gpio(5, s2mpg10_buck_vranges1, DVS_RAMP2, + PCTRLSEL3, GENMASK(3, 0)), + s2mpg10_regulator_desc_buck_gpio(6, s2mpg10_buck_vranges6, DVS_RAMP2, + PCTRLSEL3, GENMASK(7, 4)), + s2mpg10_regulator_desc_buck_gpio(7, s2mpg10_buck_vranges1, DVS_RAMP2, + PCTRLSEL4, GENMASK(3, 0)), + s2mpg10_regulator_desc_buck(8, s2mpg10_buck_vranges1, DVS_RAMP2), + s2mpg10_regulator_desc_buck(9, s2mpg10_buck_vranges1, DVS_RAMP3), + s2mpg10_regulator_desc_buck_gpio(10, s2mpg10_buck_vranges1, DVS_RAMP3, + PCTRLSEL4, GENMASK(7, 4)), + /* + * Standard LDO via LxM_CTRL but non-standard (greater) V-range and with + * ramp support. + */ + s2mpg10_regulator_desc_ldo_cmn(1, "vinl3m", s2mpg10_reg_ldo_ramp_ops, + s2mpg10_ldo_vranges1, + CTRL, GENMASK(6, 0), + L1M_CTRL, BIT(7), + 6250, S2MPG10_PMIC_DVS_RAMP6, + GENMASK(5, 4), s2mpg10_ldo_ramp_table, + ARRAY_SIZE(s2mpg10_ldo_ramp_table), + 0, 0), + s2mpg10_regulator_desc_ldo(2, "vinl9m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo_gpio(3, "vinl4m", s2mpg10_ldo_vranges3, + PCTRLSEL5, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(4, "vinl9m", s2mpg10_ldo_vranges2, + PCTRLSEL5, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_gpio(5, "vinl3m", s2mpg10_ldo_vranges3, + PCTRLSEL6, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(6, "vinl7m", s2mpg10_ldo_vranges3, + PCTRLSEL6, GENMASK(7, 4)), + /* + * Ramp support, possibly GPIO controlled, non-standard (greater) V- + * range and enable reg & mask. + */ + s2mpg10_regulator_desc_ldo_cmn(7, "vinl3m", s2mpg10_reg_ldo_ramp_ops, + s2mpg10_ldo_vranges7, + CTRL, GENMASK(6, 0), + LDO_CTRL1, GENMASK(4, 3), + 6250, S2MPG10_PMIC_DVS_RAMP6, + GENMASK(7, 6), s2mpg10_ldo_ramp_table, + ARRAY_SIZE(s2mpg10_ldo_ramp_table), + S2MPG10_PMIC_PCTRLSEL7, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(8, "vinl4m", s2mpg10_ldo_vranges3, + PCTRLSEL7, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_gpio(9, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL8, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(10, "vinl15m", s2mpg10_ldo_vranges10, + PCTRLSEL8, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_ramp(11, "vinl7m", s2mpg10_ldo_vranges1, + GENMASK(1, 0), DVS_SYNC_CTRL3, + PCTRLSEL9, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_ramp(12, "vinl8m", s2mpg10_ldo_vranges1, + GENMASK(3, 2), DVS_SYNC_CTRL4, + PCTRLSEL9, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_ramp(13, "vinl1m", s2mpg10_ldo_vranges13, + GENMASK(5, 4), DVS_SYNC_CTRL5, + PCTRLSEL10, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(14, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL10, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_ramp(15, "vinl2m", s2mpg10_ldo_vranges13, + GENMASK(7, 6), DVS_SYNC_CTRL6, + PCTRLSEL11, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(16, "vinl5m", s2mpg10_ldo_vranges3, + PCTRLSEL11, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_gpio(17, "vinl6m", s2mpg10_ldo_vranges3, + PCTRLSEL12, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(18, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL12, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_gpio(19, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL13, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(20, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL13, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo(21, "vinl14m", s2mpg10_ldo_vranges21), + s2mpg10_regulator_desc_ldo(22, "vinl15m", s2mpg10_ldo_vranges21), + s2mpg10_regulator_desc_ldo(23, "vinl11m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo(24, "vinl7m", s2mpg10_ldo_vranges3), + s2mpg10_regulator_desc_ldo(25, "vinl10m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo(26, "vinl15m", s2mpg10_ldo_vranges21), + s2mpg10_regulator_desc_ldo(27, "vinl15m", s2mpg10_ldo_vranges21), + s2mpg10_regulator_desc_ldo(28, "vinl7m", s2mpg10_ldo_vranges3), + s2mpg10_regulator_desc_ldo(29, "vinl12m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo(30, "vinl13m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo(31, "vinl11m", s2mpg10_ldo_vranges2) +}; + static const struct regulator_ops s2mps11_ldo_ops =3D { .list_voltage =3D regulator_list_voltage_linear, .map_voltage =3D regulator_map_voltage_linear, @@ -1271,6 +1818,18 @@ static int s2mps11_handle_ext_control(struct s2mps11= _info *s2mps11, ret =3D s2mps14_pmic_enable_ext_control(s2mps11, rdev); break; =20 + case S2MPG10: + /* + * If desc.enable_val is !=3D 0, then external control was + * requested. We can not test s2mpg10_desc::ext_control, + * because 0 is a valid value. + */ + if (!rdev->desc->enable_val) + return 0; + + ret =3D s2mpg10_enable_ext_control(s2mps11, rdev); + break; + default: return 0; } @@ -1281,11 +1840,13 @@ static int s2mps11_handle_ext_control(struct s2mps1= 1_info *s2mps11, static int s2mps11_pmic_probe(struct platform_device *pdev) { struct sec_pmic_dev *iodev =3D dev_get_drvdata(pdev->dev.parent); + const struct mfd_cell *cell =3D mfd_get_cell(pdev); struct regulator_config config =3D { }; struct s2mps11_info *s2mps11; unsigned int rdev_num; int i, ret; const struct regulator_desc *regulators; + const struct s2mpg10_regulator_desc *s2mpg1x_regulators =3D NULL; =20 s2mps11 =3D devm_kzalloc(&pdev->dev, sizeof(struct s2mps11_info), GFP_KERNEL); @@ -1294,6 +1855,16 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) =20 s2mps11->dev_type =3D platform_get_device_id(pdev)->driver_data; switch (s2mps11->dev_type) { + case S2MPG10: + if (cell->id >=3D ARRAY_SIZE(s2mpg10_regulators)) + return dev_err_probe(&pdev->dev, -ENODEV, + "Unsupported regulator ID %d\n", + cell->id); + + rdev_num =3D 1; + s2mpg1x_regulators =3D &s2mpg10_regulators[cell->id]; + BUILD_BUG_ON(ARRAY_SIZE(s2mpg10_regulators) > S2MPS_REGULATOR_MAX); + break; case S2MPS11X: rdev_num =3D ARRAY_SIZE(s2mps11_regulators); regulators =3D s2mps11_regulators; @@ -1338,15 +1909,30 @@ static int s2mps11_pmic_probe(struct platform_devic= e *pdev) config.regmap =3D iodev->regmap_pmic; config.driver_data =3D s2mps11; for (i =3D 0; i < rdev_num; i++) { + const struct regulator_desc *rdesc; struct regulator_dev *regulator; =20 + if (s2mpg1x_regulators) { + struct s2mpg10_regulator_desc *s2mpg10_desc; + + s2mpg10_desc =3D devm_kmemdup(&pdev->dev, + &s2mpg1x_regulators[i], + sizeof(*s2mpg10_desc), + GFP_KERNEL); + if (!s2mpg10_desc) + return -ENOMEM; + + rdesc =3D &s2mpg10_desc->desc; + } else { + rdesc =3D ®ulators[i]; + } + regulator =3D devm_regulator_register(&pdev->dev, - ®ulators[i], &config); + rdesc, &config); if (IS_ERR(regulator)) return dev_err_probe(&pdev->dev, PTR_ERR(regulator), "regulator init failed for %d/%s\n", - regulators[i].id, - regulators[i].name); + rdesc->id, rdesc->name); =20 ret =3D s2mps11_handle_ext_control(s2mps11, regulator); if (ret < 0) @@ -1357,6 +1943,7 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) } =20 static const struct platform_device_id s2mps11_pmic_id[] =3D { + { "s2mpg10-regulator", S2MPG10}, { "s2mps11-regulator", S2MPS11X}, { "s2mps13-regulator", S2MPS13X}, { "s2mps14-regulator", S2MPS14X}, diff --git a/include/linux/mfd/samsung/s2mpg10.h b/include/linux/mfd/samsun= g/s2mpg10.h index 9f5919b89a3c286bf1cd6b3ef0e74bc993bff01a..2c324a2bbbd9000f025eb49231e= a601ac7b5008e 100644 --- a/include/linux/mfd/samsung/s2mpg10.h +++ b/include/linux/mfd/samsung/s2mpg10.h @@ -290,6 +290,30 @@ enum s2mpg10_pmic_reg { S2MPG10_PMIC_LDO_SENSE4, }; =20 +/* Rail controlled externally, based on PCTRLSELx */ +#define S2MPG10_PMIC_CTRL_ENABLE_EXT BIT(0) + +/* For S2MPG10_PMIC_PCTRLSELx */ +#define S2MPG10_PCTRLSEL_PWREN 0x1 /* PWREN pin */ +#define S2MPG10_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING= _CTRL */ +#define S2MPG10_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */ +#define S2MPG10_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMIC= KING_CTRL */ +#define S2MPG10_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */ +#define S2MPG10_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MI= MICKING_CTRL */ +#define S2MPG10_PCTRLSEL_CPUCL1_EN 0x7 /* CPUCL1_EN pin */ +#define S2MPG10_PCTRLSEL_CPUCL1_EN2 0x8 /* CPUCL1_EN & PWREN pins */ +#define S2MPG10_PCTRLSEL_CPUCL2_EN 0x9 /* CPUCL2_EN pin */ +#define S2MPG10_PCTRLSEL_CPUCL2_EN2 0xa /* CPUCL2_E2 & PWREN pins */ +#define S2MPG10_PCTRLSEL_TPU_EN 0xb /* TPU_EN pin */ +#define S2MPG10_PCTRLSEL_TPU_EN2 0xc /* TPU_EN & ~AP_ACTIVE_N pins= */ +#define S2MPG10_PCTRLSEL_TCXO_ON 0xd /* TCXO_ON pin */ +#define S2MPG10_PCTRLSEL_TCXO_ON2 0xe /* TCXO_ON & ~AP_ACTIVE_N pin= s */ + +/* For S2MPG10_PMIC_PCTRLSELx of LDO20M */ +#define S2MPG10_PCTRLSEL_LDO20M_EN2 0x1 /* VLDO20M_EN & LDO20M_SFR */ +#define S2MPG10_PCTRLSEL_LDO20M_EN 0x2 /* VLDO20M_EN pin */ +#define S2MPG10_PCTRLSEL_LDO20M_SFR 0x3 /* LDO20M_SFR bit in LDO_CTRL= 1 register */ + /* Meter registers (type 0xa00) */ enum s2mpg10_meter_reg { S2MPG10_METER_CTRL1, --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E883B339708 for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:07 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:29:00 +0000 Subject: [PATCH v4 17/20] regulator: s2mps11: refactor S2MPG10 ::set_voltage_time() for S2MPG11 reuse Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-17-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The upcoming S2MPG11 support needs a similar, but different version of ::set_voltage_time(). For S2MPG10, the downwards and upwards ramps for a rail are at different offsets at the same bit positions, while for S2MPG11 the ramps are at the same offset at different bit positions. Refactor the existing version slightly to allow reuse. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index aff85138fa5da4cff83bdec5cdb3086a58afc7ce..d840aec236dcbdc8b460f89b4cd= 04e42e3b3da7d 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -561,26 +561,23 @@ static int s2mpg10_regulator_buck_enable_time(struct = regulator_dev *rdev) + DIV_ROUND_UP(curr_uV, s2mpg10_desc->enable_ramp_rate)); } =20 -static int s2mpg10_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, - int old_uV, int new_uV) +static int s2mpg1x_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, + int old_uV, int new_uV, + unsigned int ramp_reg, + unsigned int ramp_mask) { - unsigned int ramp_reg, ramp_sel, ramp_rate; + unsigned int ramp_sel, ramp_rate; int ret; =20 if (old_uV =3D=3D new_uV) return 0; =20 - ramp_reg =3D rdev->desc->ramp_reg; - if (old_uV > new_uV) - /* The downwards ramp is at a different offset. */ - ramp_reg +=3D S2MPG10_PMIC_DVS_RAMP4 - S2MPG10_PMIC_DVS_RAMP1; - ret =3D regmap_read(rdev->regmap, ramp_reg, &ramp_sel); if (ret) return ret; =20 - ramp_sel &=3D rdev->desc->ramp_mask; - ramp_sel >>=3D ffs(rdev->desc->ramp_mask) - 1; + ramp_sel &=3D ramp_mask; + ramp_sel >>=3D ffs(ramp_mask) - 1; if (ramp_sel >=3D rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table) return -EINVAL; @@ -590,6 +587,21 @@ static int s2mpg10_regulator_buck_set_voltage_time(str= uct regulator_dev *rdev, return DIV_ROUND_UP(abs(new_uV - old_uV), ramp_rate); } =20 +static int s2mpg10_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, + int old_uV, int new_uV) +{ + unsigned int ramp_reg; + + ramp_reg =3D rdev->desc->ramp_reg; + if (old_uV > new_uV) + /* The downwards ramp is at a different offset. */ + ramp_reg +=3D S2MPG10_PMIC_DVS_RAMP4 - S2MPG10_PMIC_DVS_RAMP1; + + return s2mpg1x_regulator_buck_set_voltage_time(rdev, old_uV, new_uV, + ramp_reg, + rdev->desc->ramp_mask); +} + /* * We assign both, ::set_voltage_time() and ::set_voltage_time_sel(), beca= use * only if the latter is !=3D NULL, the regulator core will call neither d= uring --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33835336EEB for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:08 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:29:01 +0000 Subject: [PATCH v4 18/20] regulator: s2mps11: refactor S2MPG10 regulator macros for S2MPG11 reuse Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-18-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Rails in the S2MPG11 share a very similar set of properties with S2MPG10 with slight differences. Update the existing macros to allow reuse by the upcoming S2MPG11 driver. Signed-off-by: Andr=C3=A9 Draszik --- Note: checkpatch complains about unused macro arguments _r_mask, _r_table, and _r_table_sz, but these are false-positives due to patch context. v2: - fix commit message typos: s2mp1 -> s2mpg1 - drop duplicated assignment of ::of_parse_cb in regulator_desc_s2mpg1x_buck_cmn() macro --- drivers/regulator/s2mps11.c | 69 +++++++++++++++++++++++++++--------------= ---- 1 file changed, 42 insertions(+), 27 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index d840aec236dcbdc8b460f89b4cd04e42e3b3da7d..35cfea6b6d8091ba21f00e1cb82= b11a8dc9bc3ec 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -650,31 +650,44 @@ static const struct regulator_ops s2mpg10_reg_buck_op= s[] =3D { * (12.5mV/=CE=BCs) while our ::set_voltage_time() takes the value in ramp= _reg * into account. */ -#define regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg) { \ - .name =3D "buck"#_num "m", \ - .supply_name =3D "vinb"#_num "m", \ - .of_match =3D of_match_ptr("buck"#_num "m"), \ +#define regulator_desc_s2mpg1x_buck_cmn(_name, _id, _supply, _ops, \ + _vrange, _vsel_reg, _vsel_mask, _en_reg, _en_mask, \ + _r_reg, _r_mask, _r_table, _r_table_sz, \ + _en_time) { \ + .name =3D "buck" _name, \ + .supply_name =3D _supply, \ + .of_match =3D of_match_ptr("buck" _name), \ .regulators_node =3D of_match_ptr("regulators"), \ .of_parse_cb =3D s2mpg10_of_parse_cb, \ - .id =3D S2MPG10_BUCK##_num, \ - .ops =3D &s2mpg10_reg_buck_ops[0], \ + .id =3D _id, \ + .ops =3D &(_ops)[0], \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ .linear_ranges =3D _vrange, \ .n_linear_ranges =3D ARRAY_SIZE(_vrange), \ .n_voltages =3D _vrange##_count, \ - .vsel_reg =3D S2MPG10_PMIC_B##_num##M_OUT1, \ - .vsel_mask =3D 0xff, \ - .enable_reg =3D S2MPG10_PMIC_B##_num##M_CTRL, \ - .enable_mask =3D GENMASK(7, 6), \ - .ramp_reg =3D S2MPG10_PMIC_##_r_reg, \ - .ramp_mask =3D s2mpg10_buck_to_ramp_mask(S2MPG10_BUCK##_num \ - - S2MPG10_BUCK1), \ - .ramp_delay_table =3D s2mpg10_buck_ramp_table, \ - .n_ramp_values =3D ARRAY_SIZE(s2mpg10_buck_ramp_table), \ - .enable_time =3D 30, /* + V/enable_ramp_rate */ \ + .vsel_reg =3D _vsel_reg, \ + .vsel_mask =3D _vsel_mask, \ + .enable_reg =3D _en_reg, \ + .enable_mask =3D _en_mask, \ + .ramp_reg =3D _r_reg, \ + .ramp_mask =3D _r_mask, \ + .ramp_delay_table =3D _r_table, \ + .n_ramp_values =3D _r_table_sz, \ + .enable_time =3D _en_time, /* + V/enable_ramp_rate */ \ } =20 +#define regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg) \ + regulator_desc_s2mpg1x_buck_cmn(#_num "m", S2MPG10_BUCK##_num, \ + "vinb"#_num "m", s2mpg10_reg_buck_ops, _vrange, \ + S2MPG10_PMIC_B##_num##M_OUT1, GENMASK(7, 0), \ + S2MPG10_PMIC_B##_num##M_CTRL, GENMASK(7, 6), \ + S2MPG10_PMIC_##_r_reg, \ + s2mpg10_buck_to_ramp_mask(S2MPG10_BUCK##_num \ + - S2MPG10_BUCK1), \ + s2mpg10_buck_ramp_table, \ + ARRAY_SIZE(s2mpg10_buck_ramp_table), 30) + #define s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg) \ .desc =3D regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg), \ .enable_ramp_rate =3D 12500 @@ -738,24 +751,24 @@ static const struct regulator_ops s2mpg10_reg_ldo_ram= p_ops[] =3D { } }; =20 -#define regulator_desc_s2mpg10_ldo_cmn(_num, _supply, _ops, _vrange, \ - _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \ +#define regulator_desc_s2mpg1x_ldo_cmn(_name, _id, _supply, _ops, \ + _vrange, _vsel_reg, _vsel_mask, _en_reg, _en_mask, \ _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz) { \ - .name =3D "ldo"#_num "m", \ + .name =3D "ldo" _name, \ .supply_name =3D _supply, \ - .of_match =3D of_match_ptr("ldo"#_num "m"), \ + .of_match =3D of_match_ptr("ldo" _name), \ .regulators_node =3D of_match_ptr("regulators"), \ .of_parse_cb =3D s2mpg10_of_parse_cb, \ - .id =3D S2MPG10_LDO##_num, \ + .id =3D _id, \ .ops =3D &(_ops)[0], \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ .linear_ranges =3D _vrange, \ .n_linear_ranges =3D ARRAY_SIZE(_vrange), \ .n_voltages =3D _vrange##_count, \ - .vsel_reg =3D S2MPG10_PMIC_L##_num##M_##_vsel_reg_sfx, \ + .vsel_reg =3D _vsel_reg, \ .vsel_mask =3D _vsel_mask, \ - .enable_reg =3D S2MPG10_PMIC_##_en_reg, \ + .enable_reg =3D _en_reg, \ .enable_mask =3D _en_mask, \ .ramp_delay =3D _ramp_delay, \ .ramp_reg =3D _r_reg, \ @@ -770,10 +783,12 @@ static const struct regulator_ops s2mpg10_reg_ldo_ram= p_ops[] =3D { _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz, \ _pc_reg, _pc_mask) \ [S2MPG10_LDO##_num] =3D { \ - .desc =3D regulator_desc_s2mpg10_ldo_cmn(_num, _supply, \ - _ops, \ - _vrange, _vsel_reg_sfx, _vsel_mask, \ - _en_reg, _en_mask, \ + .desc =3D regulator_desc_s2mpg1x_ldo_cmn(#_num "m", \ + S2MPG10_LDO##_num, _supply, _ops, \ + _vrange, \ + S2MPG10_PMIC_L##_num##M_##_vsel_reg_sfx, \ + _vsel_mask, \ + S2MPG10_PMIC_##_en_reg, _en_mask, \ _ramp_delay, _r_reg, _r_mask, _r_table, \ _r_table_sz), \ .pctrlsel_reg =3D _pc_reg, \ --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B0F333A039 for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:08 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:29:02 +0000 Subject: [PATCH v4 19/20] regulator: s2mps11: add S2MPG11 regulator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-19-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The S2MPG11 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, and additional GPIO interfaces. It typically complements an S2MPG10 PMIC in a main/sub configuration as the sub-PMIC. It has 12 buck, 1 buck-boost, and 15 LDO rails. Several of these can either be controlled via software (register writes) or via external signals, in particular by: * input pins connected to a main processor's: * GPIO pins * other pins that are e.g. firmware- or power-domain-controlled without explicit driver intervention * a combination of input pins and register writes. Control via input pins allows PMIC rails to be controlled by firmware, e.g. during standby/suspend or as part of power domain handling where otherwise that would not be possible. Additionally toggling a pin is faster than register writes, and it also allows the PMIC to ensure that any necessary timing requirements between rails are respected automatically if multiple rails are to be enabled or disabled quasi simultaneously. This commit implements support for all these rails and control combination. Note1: For an externally controlled rail, the regulator_ops provide an empty ::enable() and no ::disable() implementations, even though Linux can not enable the rail and one might think ::enable could be NULL. Without ops->enable(), the regulator core will assume enabling such a rail failed, though, and in turn never add a reference to its parent (supplier) rail. Once a different (Linux-controlled) sibling (consumer) rail on that same parent rail gets disabled, the parent gets disabled (cutting power to the externally controlled rail although it should stay on), and the system will misbehave. Note2: The rails are instantiated as separate driver instances for each rail, because S2MPG11 is typically used with an S2MPG10 main-PMIC where some bucks of one typically supply at least some of the LDOs of the other. Using separate instances avoids issues around circular dependencies which occur otherwise. Note3: While external control via input pins appears to exist on other versions of this PMIC, there is more flexibility in this version, in particular there is a selection of input pins to choose from for each rail (which must therefore be configured accordingly if in use), whereas other versions don't have this flexibility. Signed-off-by: Andr=C3=A9 Draszik --- v3: - one instance per actual rail, not per rail type (LDO or buck) - assign correct ::ops for LDOs with ramp support - sort s2mpg11 bucks before LDOs throughout (alphabetic ordering) - add ::enable() to ops for signal-controlled rails and update commit message detailing why - more details around signal controlled rails in commit message v2: - fix commit message typo - mention GPIOs in commit message --- drivers/regulator/s2mps11.c | 307 ++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 306 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 35cfea6b6d8091ba21f00e1cb82b11a8dc9bc3ec..f19140e97b9d7a5e7c07cdc5e00= 2de345aad32d9 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -432,9 +433,20 @@ static int s2mpg10_of_parse_cb(struct device_node *np, [S2MPG10_EXTCTRL_LDO20M_EN2] =3D S2MPG10_PCTRLSEL_LDO20M_EN2, [S2MPG10_EXTCTRL_LDO20M_EN] =3D S2MPG10_PCTRLSEL_LDO20M_EN, }; + static const u32 ext_control_s2mpg11[] =3D { + [S2MPG11_EXTCTRL_PWREN] =3D S2MPG10_PCTRLSEL_PWREN, + [S2MPG11_EXTCTRL_PWREN_MIF] =3D S2MPG10_PCTRLSEL_PWREN_MIF, + [S2MPG11_EXTCTRL_AP_ACTIVE_N] =3D S2MPG10_PCTRLSEL_AP_ACTIVE_N, + [S2MPG11_EXTCTRL_G3D_EN] =3D S2MPG10_PCTRLSEL_CPUCL1_EN, + [S2MPG11_EXTCTRL_G3D_EN2] =3D S2MPG10_PCTRLSEL_CPUCL1_EN2, + [S2MPG11_EXTCTRL_AOC_VDD] =3D S2MPG10_PCTRLSEL_CPUCL2_EN, + [S2MPG11_EXTCTRL_AOC_RET] =3D S2MPG10_PCTRLSEL_CPUCL2_EN2, + [S2MPG11_EXTCTRL_UFS_EN] =3D S2MPG10_PCTRLSEL_TPU_EN, + [S2MPG11_EXTCTRL_LDO13S_EN] =3D S2MPG10_PCTRLSEL_TPU_EN2, + }; u32 ext_control; =20 - if (s2mps11->dev_type !=3D S2MPG10) + if (s2mps11->dev_type !=3D S2MPG10 && s2mps11->dev_type !=3D S2MPG11) return 0; =20 if (of_property_read_u32(np, "samsung,ext-control", &ext_control)) @@ -465,6 +477,31 @@ static int s2mpg10_of_parse_cb(struct device_node *np, ext_control =3D ext_control_s2mpg10[ext_control]; break; =20 + case S2MPG11: + switch (desc->id) { + case S2MPG11_BUCK1 ... S2MPG11_BUCK3: + case S2MPG11_BUCK5: + case S2MPG11_BUCK8: + case S2MPG11_BUCK9: + case S2MPG11_BUCKD: + case S2MPG11_BUCKA: + case S2MPG10_LDO1: + case S2MPG10_LDO2: + case S2MPG10_LDO8: + case S2MPG10_LDO13: + if (ext_control > S2MPG11_EXTCTRL_LDO13S_EN) + return -EINVAL; + break; + + default: + return -EINVAL; + } + + if (ext_control > ARRAY_SIZE(ext_control_s2mpg11)) + return -EINVAL; + ext_control =3D ext_control_s2mpg11[ext_control]; + break; + default: return -EINVAL; } @@ -502,6 +539,7 @@ static int s2mpg10_enable_ext_control(struct s2mps11_in= fo *s2mps11, =20 switch (s2mps11->dev_type) { case S2MPG10: + case S2MPG11: s2mpg10_desc =3D to_s2mpg10_regulator_desc(rdev->desc); break; =20 @@ -602,6 +640,21 @@ static int s2mpg10_regulator_buck_set_voltage_time(str= uct regulator_dev *rdev, rdev->desc->ramp_mask); } =20 +static int s2mpg11_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, + int old_uV, int new_uV) +{ + unsigned int ramp_mask; + + ramp_mask =3D rdev->desc->ramp_mask; + if (old_uV > new_uV) + /* The downwards mask is at a different position. */ + ramp_mask >>=3D 2; + + return s2mpg1x_regulator_buck_set_voltage_time(rdev, old_uV, new_uV, + rdev->desc->ramp_reg, + ramp_mask); +} + /* * We assign both, ::set_voltage_time() and ::set_voltage_time_sel(), beca= use * only if the latter is !=3D NULL, the regulator core will call neither d= uring @@ -962,6 +1015,246 @@ static const struct s2mpg10_regulator_desc s2mpg10_r= egulators[] =3D { s2mpg10_regulator_desc_ldo(31, "vinl11m", s2mpg10_ldo_vranges2) }; =20 +static const struct regulator_ops s2mpg11_reg_buck_ops[] =3D { + [S2MPG10_REGULATOR_OPS_STD] =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time =3D s2mpg11_regulator_buck_set_voltage_time, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable_time =3D s2mpg10_regulator_buck_enable_time, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + }, + [S2MPG10_REGULATOR_OPS_EXTCONTROL] =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .enable =3D s2mpg10_regulator_enable_nop, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time =3D s2mpg11_regulator_buck_set_voltage_time, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable_time =3D s2mpg10_regulator_buck_enable_time, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + } +}; + +#define s2mpg11_buck_to_ramp_mask(n) (GENMASK(3, 2) << (((n) % 2) * 4)) + +#define regulator_desc_s2mpg11_buckx(_name, _id, _supply, _vrange, \ + _vsel_reg, _en_reg, _en_mask, _r_reg) \ + regulator_desc_s2mpg1x_buck_cmn(_name, _id, _supply, \ + s2mpg11_reg_buck_ops, _vrange, \ + S2MPG11_PMIC_##_vsel_reg, GENMASK(7, 0), \ + S2MPG11_PMIC_##_en_reg, _en_mask, \ + S2MPG11_PMIC_##_r_reg, \ + s2mpg11_buck_to_ramp_mask(_id - S2MPG11_BUCK1), \ + s2mpg10_buck_ramp_table, \ + ARRAY_SIZE(s2mpg10_buck_ramp_table), 30) + +#define s2mpg11_regulator_desc_buck_xm(_num, _vrange, _vsel_reg_sfx, \ + _en_mask, _r_reg, _en_rrate) \ + .desc =3D regulator_desc_s2mpg11_buckx(#_num"s", \ + S2MPG11_BUCK##_num, "vinb"#_num"s", \ + _vrange, \ + B##_num##S_##_vsel_reg_sfx, \ + B##_num##S_CTRL, _en_mask, \ + _r_reg), \ + .enable_ramp_rate =3D _en_rrate + +#define s2mpg11_regulator_desc_buck_cm(_num, _vrange, _vsel_reg_sfx, \ + _en_mask, _r_reg) \ + [S2MPG11_BUCK##_num] =3D { \ + s2mpg11_regulator_desc_buck_xm(_num, _vrange, \ + _vsel_reg_sfx, _en_mask, _r_reg, 12500), \ + } + +#define s2mpg11_regulator_desc_buckn_cm_gpio(_num, _vrange, \ + _vsel_reg_sfx, _en_mask, _r_reg, _pc_reg, _pc_mask) \ + [S2MPG11_BUCK##_num] =3D { \ + s2mpg11_regulator_desc_buck_xm(_num, _vrange, \ + _vsel_reg_sfx, _en_mask, _r_reg, 12500), \ + .pctrlsel_reg =3D S2MPG11_PMIC_##_pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +#define s2mpg11_regulator_desc_buck_vm(_num, _vrange, _vsel_reg_sfx, \ + _en_mask, _r_reg) \ + [S2MPG11_BUCK##_num] =3D { \ + s2mpg11_regulator_desc_buck_xm(_num, _vrange, \ + _vsel_reg_sfx, _en_mask, _r_reg, 25000), \ + } + +#define s2mpg11_regulator_desc_bucka(_num, _num_lower, _r_reg, \ + _pc_reg, _pc_mask) \ + [S2MPG11_BUCK##_num] =3D { \ + .desc =3D regulator_desc_s2mpg11_buckx(#_num_lower, \ + S2MPG11_BUCK##_num, "vinb"#_num_lower, \ + s2mpg11_buck_vranges##_num_lower, \ + BUCK##_num##_OUT, \ + BUCK##_num##_CTRL, GENMASK(7, 6), \ + _r_reg), \ + .enable_ramp_rate =3D 25000, \ + .pctrlsel_reg =3D S2MPG11_PMIC_##_pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +#define s2mpg11_regulator_desc_buckboost() \ + [S2MPG11_BUCKBOOST] =3D { \ + .desc =3D regulator_desc_s2mpg1x_buck_cmn("boost", \ + S2MPG11_BUCKBOOST, "vinbb", \ + s2mpg10_reg_ldo_ops, \ + s2mpg11_buck_vrangesboost, \ + S2MPG11_PMIC_BB_OUT1, GENMASK(6, 0), \ + S2MPG11_PMIC_BB_CTRL, BIT(7), \ + 0, 0, NULL, 0, 35), \ + .enable_ramp_rate =3D 17500, \ + } + +#define s2mpg11_regulator_desc_ldo_cmn(_num, _supply, _ops, \ + _vrange, _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz, \ + _pc_reg, _pc_mask) \ + [S2MPG11_LDO##_num] =3D { \ + .desc =3D regulator_desc_s2mpg1x_ldo_cmn(#_num "s", \ + S2MPG11_LDO##_num, _supply, _ops, \ + _vrange, \ + S2MPG11_PMIC_L##_num##S_##_vsel_reg_sfx, \ + _vsel_mask, \ + S2MPG11_PMIC_##_en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, \ + _r_table_sz), \ + .pctrlsel_reg =3D _pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +/* standard LDO via LxM_CTRL */ +#define s2mpg11_regulator_desc_ldo(_num, _supply, _vrange) \ + s2mpg11_regulator_desc_ldo_cmn(_num, _supply, \ + s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \ + L##_num##S_CTRL, BIT(7), \ + 0, 0, 0, NULL, 0, \ + 0, 0) + +/* standard LDO but possibly GPIO controlled */ +#define s2mpg11_regulator_desc_ldo_gpio(_num, _supply, _vrange, \ + _pc_reg, _pc_mask) \ + s2mpg11_regulator_desc_ldo_cmn(_num, _supply, \ + s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \ + L##_num##S_CTRL, GENMASK(7, 6), \ + 0, 0, 0, NULL, 0, \ + S2MPG11_PMIC_##_pc_reg, _pc_mask) + +/* LDO with ramp support and possibly GPIO controlled */ +#define s2mpg11_regulator_desc_ldo_ramp(_num, _supply, _vrange, \ + _en_mask, _r_reg, _pc_reg, _pc_mask) \ + s2mpg11_regulator_desc_ldo_cmn(_num, _supply, \ + s2mpg10_reg_ldo_ramp_ops, _vrange, CTRL1, GENMASK(6, 0), \ + LDO_CTRL1, _en_mask, \ + 6250, S2MPG11_PMIC_##_r_reg, GENMASK(1, 0), \ + s2mpg10_ldo_ramp_table, \ + ARRAY_SIZE(s2mpg10_ldo_ramp_table), \ + S2MPG11_PMIC_##_pc_reg, _pc_mask) + +/* voltage range for s2mpg11 BUCK 1, 2, 3, 4, 8, 9, 10 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 1, 200000, 450000, 1300000, STEP_6_25_= MV); + +/* voltage range for s2mpg11 BUCK 5 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 5, 200000, 400000, 1300000, STEP_6_25_= MV); + +/* voltage range for s2mpg11 BUCK 6 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 6, 200000, 1000000, 1500000, STEP_6_25= _MV); + +/* voltage range for s2mpg11 BUCK 7 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 7, 600000, 1500000, 2200000, STEP_12_5= _MV); + +/* voltage range for s2mpg11 BUCK D */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, d, 600000, 2400000, 3300000, STEP_12_5= _MV); + +/* voltage range for s2mpg11 BUCK A */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, a, 600000, 1700000, 2100000, STEP_12_5= _MV); + +/* voltage range for s2mpg11 BUCK BOOST */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, boost, + 2600000, 3000000, 3600000, STEP_12_5_MV); + +/* voltage range for s2mpg11 LDO 1, 2 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 1, 300000, 450000, 950000, STEP_12_5_MV= ); + +/* voltage range for s2mpg11 LDO 3, 7, 10, 11, 12, 14, 15 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 3, 700000, 1600000, 1950000, STEP_25_MV= ); + +/* voltage range for s2mpg11 LDO 4, 6 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 4, 1800000, 2500000, 3300000, STEP_25_M= V); + +/* voltage range for s2mpg11 LDO 5 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 5, 1600000, 1600000, 1950000, STEP_12_5= _MV); + +/* voltage range for s2mpg11 LDO 8 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 8, 979600, 1130400, 1281200, 5800); + +/* voltage range for s2mpg11 LDO 9 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 9, 725000, 725000, 1300000, STEP_12_5_M= V); + +/* voltage range for s2mpg11 LDO 13 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 13, 1800000, 1800000, 3350000, STEP_25_= MV); + +static const struct s2mpg10_regulator_desc s2mpg11_regulators[] =3D { + s2mpg11_regulator_desc_buckboost(), + s2mpg11_regulator_desc_buckn_cm_gpio(1, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP1, + PCTRLSEL1, GENMASK(3, 0)), + s2mpg11_regulator_desc_buckn_cm_gpio(2, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP1, + PCTRLSEL1, GENMASK(7, 4)), + s2mpg11_regulator_desc_buckn_cm_gpio(3, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP2, + PCTRLSEL2, GENMASK(3, 0)), + s2mpg11_regulator_desc_buck_cm(4, s2mpg11_buck_vranges1, + OUT, BIT(7), DVS_RAMP2), + s2mpg11_regulator_desc_buckn_cm_gpio(5, s2mpg11_buck_vranges5, + OUT, GENMASK(7, 6), DVS_RAMP3, + PCTRLSEL2, GENMASK(7, 4)), + s2mpg11_regulator_desc_buck_cm(6, s2mpg11_buck_vranges6, + OUT1, BIT(7), DVS_RAMP3), + s2mpg11_regulator_desc_buck_vm(7, s2mpg11_buck_vranges7, + OUT1, BIT(7), DVS_RAMP4), + s2mpg11_regulator_desc_buckn_cm_gpio(8, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP4, + PCTRLSEL3, GENMASK(3, 0)), + s2mpg11_regulator_desc_buckn_cm_gpio(9, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP5, + PCTRLSEL3, GENMASK(7, 4)), + s2mpg11_regulator_desc_buck_cm(10, s2mpg11_buck_vranges1, + OUT, BIT(7), DVS_RAMP5), + s2mpg11_regulator_desc_bucka(D, d, DVS_RAMP6, PCTRLSEL4, GENMASK(3, 0)), + s2mpg11_regulator_desc_bucka(A, a, DVS_RAMP6, PCTRLSEL4, GENMASK(7, 4)), + s2mpg11_regulator_desc_ldo_ramp(1, "vinl1s", s2mpg11_ldo_vranges1, + GENMASK(5, 4), DVS_SYNC_CTRL1, + PCTRLSEL5, GENMASK(3, 0)), + s2mpg11_regulator_desc_ldo_ramp(2, "vinl1s", s2mpg11_ldo_vranges1, + GENMASK(7, 6), DVS_SYNC_CTRL2, + PCTRLSEL5, GENMASK(7, 4)), + s2mpg11_regulator_desc_ldo(3, "vinl3s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo(4, "vinl5s", s2mpg11_ldo_vranges4), + s2mpg11_regulator_desc_ldo(5, "vinl3s", s2mpg11_ldo_vranges5), + s2mpg11_regulator_desc_ldo(6, "vinl5s", s2mpg11_ldo_vranges4), + s2mpg11_regulator_desc_ldo(7, "vinl3s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo_gpio(8, "vinl2s", s2mpg11_ldo_vranges8, + PCTRLSEL6, GENMASK(3, 0)), + s2mpg11_regulator_desc_ldo(9, "vinl2s", s2mpg11_ldo_vranges9), + s2mpg11_regulator_desc_ldo(10, "vinl4s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo(11, "vinl4s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo(12, "vinl4s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo_gpio(13, "vinl6s", s2mpg11_ldo_vranges13, + PCTRLSEL6, GENMASK(7, 4)), + s2mpg11_regulator_desc_ldo(14, "vinl4s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo(15, "vinl3s", s2mpg11_ldo_vranges3) +}; + static const struct regulator_ops s2mps11_ldo_ops =3D { .list_voltage =3D regulator_list_voltage_linear, .map_voltage =3D regulator_map_voltage_linear, @@ -1846,6 +2139,7 @@ static int s2mps11_handle_ext_control(struct s2mps11_= info *s2mps11, break; =20 case S2MPG10: + case S2MPG11: /* * If desc.enable_val is !=3D 0, then external control was * requested. We can not test s2mpg10_desc::ext_control, @@ -1892,6 +2186,16 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) s2mpg1x_regulators =3D &s2mpg10_regulators[cell->id]; BUILD_BUG_ON(ARRAY_SIZE(s2mpg10_regulators) > S2MPS_REGULATOR_MAX); break; + case S2MPG11: + if (cell->id >=3D ARRAY_SIZE(s2mpg11_regulators)) + return dev_err_probe(&pdev->dev, -ENODEV, + "Unsupported regulator ID %d\n", + cell->id); + + rdev_num =3D 1; + s2mpg1x_regulators =3D &s2mpg11_regulators[cell->id]; + BUILD_BUG_ON(ARRAY_SIZE(s2mpg11_regulators) > S2MPS_REGULATOR_MAX); + break; case S2MPS11X: rdev_num =3D ARRAY_SIZE(s2mps11_regulators); regulators =3D s2mps11_regulators; @@ -1971,6 +2275,7 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) =20 static const struct platform_device_id s2mps11_pmic_id[] =3D { { "s2mpg10-regulator", S2MPG10}, + { "s2mpg11-regulator", S2MPG11}, { "s2mps11-regulator", S2MPS11X}, { "s2mps13-regulator", S2MPS13X}, { "s2mps14-regulator", S2MPS14X}, --=20 2.51.2.1041.gc1ab5b90ca-goog From nobody Fri Dec 19 20:33:59 2025 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35E30336EFD for ; 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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf97d16esm1168178166b.35.2025.11.10.11.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 11:29:09 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 10 Nov 2025 19:29:03 +0000 Subject: [PATCH v4 20/20] regulator: s2mps11: more descriptive gpio consumer name Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251110-s2mpg1x-regulators-v4-20-94c9e726d4ba@linaro.org> References: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> In-Reply-To: <20251110-s2mpg1x-regulators-v4-0-94c9e726d4ba@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Currently, GPIOs claimed by this driver for external rail control all show up with "s2mps11-regulator" as consumer, which is not very informative. Switch to using the regulator name via desc->name instead, using the device name as fallback. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index f19140e97b9d7a5e7c07cdc5e002de345aad32d9..3e9da15081e680d7660c60270af= 54ba2a4f8da1d 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -363,7 +363,8 @@ static int s2mps11_of_parse_gpiod(struct device_node *n= p, ena_gpiod =3D fwnode_gpiod_get_index(of_fwnode_handle(np), con_id, 0, GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE, - "s2mps11-regulator"); + desc->name + ? : dev_name(config->dev)); if (IS_ERR(ena_gpiod)) { ret =3D PTR_ERR(ena_gpiod); =20 --=20 2.51.2.1041.gc1ab5b90ca-goog