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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7b0c9c09f22sm10565900b3a.20.2025.11.09.22.59.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Nov 2025 22:59:44 -0800 (PST) From: Qiang Yu Date: Sun, 09 Nov 2025 22:59:40 -0800 Subject: [PATCH 1/5] PCI: Add preceding capability position support and update drivers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251109-remove_cap-v1-1-2208f46f4dc2@oss.qualcomm.com> References: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> In-Reply-To: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762757982; l=9581; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=lheq4zqcXF0V+xUrX0TlihExRthP4vhu5nMZ8XNAZMg=; b=cVUy0eA5OZC/0i0rD7U0TQC5C3uBC8Ga+nIMqzU8VAMhvERqOTQRiC7EYLcbKX6EM1vsOAIID mshZgDqp2wFD0ub+NdYUe+8+Cnxok2mBNJrDzXD9AzwsC99mSKT5cFc X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=dMWrWeZb c=1 sm=1 tr=0 ts=69118d62 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ihv9QP4IZydUHuvoN0kA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: 5Mq3hjPRLye-lMPqNbh-IzvDiCUmd5-D X-Proofpoint-ORIG-GUID: 5Mq3hjPRLye-lMPqNbh-IzvDiCUmd5-D X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEwMDA1OSBTYWx0ZWRfX/tgxprk0br6b Ij+dzf+PH64TyCr52o8gc+ZSdoy8j0N9x2uwNED85Nzxf86JlKUP53wZf85zfPD40kkJxh7++o7 QNqnKlwpoCVofa6qDyVuZYPw/A0Dfv8dYF7kwLRiePaNOLKiE4olvN+mooc0WWvIbqegrZs/rWd dfBSzUR0H/REXuocwdwu9lp1meHnbD82bCfGLJZlYwvleBgbSTF1jQFewSHBkBK0Eoyi1oqIBLe txIh7/RCKHDCacZMRY9DyK2IkQ4KSqY8DuKTr8DWVYqixmDogoaTxG4sdNXom0Aj8K7chcGrFJR OEs4AHy6EHXDYfRrsC1UfJ+LE5YbLfFFxOPgzg1JyRG6o/VexqMuPkFR2PK84Qxe8qlAMHaK2qG jPHs+gy/+ZR6ocV5C3PE8sY6Wz+ZMw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-10_02,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511100059 Add support for finding the preceding capability position in PCI capability list by extending the capability finding macros with an additional parameter. This functionality is essential for modifying PCI capability list, as it provides the necessary information to update the "next" pointer of the predecessor capability when removing entries. Modify two macros to accept a new 'prev_ptr' parameter: - PCI_FIND_NEXT_CAP - Now accepts 'prev_ptr' parameter for standard capabilities - PCI_FIND_NEXT_EXT_CAP - Now accepts 'prev_ptr' parameter for extended capabilities When a capability is found, these macros: - Store the position of the preceding capability in *prev_ptr (if prev_ptr !=3D NULL) - Maintain all existing functionality when prev_ptr is NULL Update current callers to accommodate this API change: - Cadence PCIe controller: Pass NULL to cdns_pcie_find_capability() and cdns_pcie_find_ext_capability() calls - DesignWare PCIe controller: Pass NULL to all capability finding macro calls The drivers pass NULL as the prev_ptr parameter since they don't require knowledge of the preceding capability position for their current functionality. This ensures backward compatibility while enabling future capability list manipulation features. No functional changes to driver behavior result from this patch - it maintains the existing capability finding functionality while adding the infrastructure for future capability removal operations. Signed-off-by: Qiang Yu --- drivers/pci/controller/cadence/pcie-cadence.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- drivers/pci/controller/dwc/pcie-designware.c | 6 +++--- drivers/pci/pci.c | 8 ++++---- drivers/pci/pci.h | 23 +++++++++++++++++++--= -- 5 files changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index bd683d0fecb225f2134893faa7199d659157b3f1..d614452861f7755108b1220527d= c277a3754a76d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -13,13 +13,13 @@ u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) { return PCI_FIND_NEXT_CAP(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST, - cap, pcie); + cap, NULL, pcie); } EXPORT_SYMBOL_GPL(cdns_pcie_find_capability); =20 u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) { - return PCI_FIND_NEXT_EXT_CAP(cdns_pcie_read_cfg, 0, cap, pcie); + return PCI_FIND_NEXT_EXT_CAP(cdns_pcie_read_cfg, 0, cap, NULL, pcie); } EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); =20 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 7f2112c2fb21543d11e848a4a62d529cc3f4e8d0..e62665e228b9035f35c441bffd2= a5759ecf12546 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -72,7 +72,7 @@ EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar); static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8= cap) { return PCI_FIND_NEXT_CAP(dw_pcie_ep_read_cfg, PCI_CAPABILITY_LIST, - cap, ep, func_no); + cap, NULL, ep, func_no); } =20 /** diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c644216995f69cbf065e61a0392bf1e5e32cf56e..5585d3ed74316bd218572484f63= 20019db8d6a10 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -224,13 +224,13 @@ void dw_pcie_version_detect(struct dw_pcie *pci) u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { return PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, - pci); + NULL, pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); =20 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, pci); + return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, NULL, pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); =20 @@ -244,7 +244,7 @@ static u16 __dw_pcie_find_vsec_capability(struct dw_pci= e *pci, u16 vendor_id, return 0; =20 while ((vsec =3D PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, vsec, - PCI_EXT_CAP_ID_VNDR, pci))) { + PCI_EXT_CAP_ID_VNDR, NULL, pci))) { header =3D dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); if (PCI_VNDR_HEADER_ID(header) =3D=3D vsec_id) return vsec; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b14dd064006cca80ec5275e45a35d6dc2b4d0bbc..83e3252f6691f2289ab5cacc334= 6a37c69a13d59 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -426,7 +426,7 @@ static int pci_dev_str_match(struct pci_dev *dev, const= char *p, static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) { - return PCI_FIND_NEXT_CAP(pci_bus_read_config, pos, cap, bus, devfn); + return PCI_FIND_NEXT_CAP(pci_bus_read_config, pos, cap, NULL, bus, devfn); } =20 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) @@ -531,7 +531,7 @@ u16 pci_find_next_ext_capability(struct pci_dev *dev, u= 16 start, int cap) return 0; =20 return PCI_FIND_NEXT_EXT_CAP(pci_bus_read_config, start, cap, - dev->bus, dev->devfn); + NULL, dev->bus, dev->devfn); } EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); =20 @@ -600,7 +600,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u= 8 pos, int ht_cap) mask =3D HT_5BIT_CAP_MASK; =20 pos =3D PCI_FIND_NEXT_CAP(pci_bus_read_config, pos, - PCI_CAP_ID_HT, dev->bus, dev->devfn); + PCI_CAP_ID_HT, NULL, dev->bus, dev->devfn); while (pos) { rc =3D pci_read_config_byte(dev, pos + 3, &cap); if (rc !=3D PCIBIOS_SUCCESSFUL) @@ -611,7 +611,7 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u= 8 pos, int ht_cap) =20 pos =3D PCI_FIND_NEXT_CAP(pci_bus_read_config, pos + PCI_CAP_LIST_NEXT, - PCI_CAP_ID_HT, dev->bus, + PCI_CAP_ID_HT, NULL, dev->bus, dev->devfn); } =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4492b809094b5794bd94dfbc20102cb208c3fa2f..2a33356acc2e8cfe55801bcb7d0= cd6d2a336561b 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -103,17 +103,21 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev); * @read_cfg: Function pointer for reading PCI config space * @start: Starting position to begin search * @cap: Capability ID to find + * @prev_ptr: Pointer to store position of preceding capability (optional) * @args: Arguments to pass to read_cfg function * - * Search the capability list in PCI config space to find @cap. + * Search the capability list in PCI config space to find @cap. If + * found, update *prev_ptr with the position of the preceding capability + * (if prev_ptr !=3D NULL) * Implements TTL (time-to-live) protection against infinite loops. * * Return: Position of the capability if found, 0 otherwise. */ -#define PCI_FIND_NEXT_CAP(read_cfg, start, cap, args...) \ +#define PCI_FIND_NEXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ ({ \ int __ttl =3D PCI_FIND_CAP_TTL; \ - u8 __id, __found_pos =3D 0; \ + u8 __id, __found_pos =3D 0; \ + u8 __prev_pos =3D (start); \ u8 __pos =3D (start); \ u16 __ent; \ \ @@ -132,9 +136,12 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev); \ if (__id =3D=3D (cap)) { \ __found_pos =3D __pos; \ + if (prev_ptr !=3D NULL) \ + *(u8 *)prev_ptr =3D __prev_pos; \ break; \ } \ \ + __prev_pos =3D __pos; \ __pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ } \ __found_pos; \ @@ -146,21 +153,26 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev); * @read_cfg: Function pointer for reading PCI config space * @start: Starting position to begin search (0 for initial search) * @cap: Extended capability ID to find + * @prev_ptr: Pointer to store position of preceding capability (optional) * @args: Arguments to pass to read_cfg function * * Search the extended capability list in PCI config space to find @cap. + * If found, update *prev_ptr with the position of the preceding capability + * (if prev_ptr !=3D NULL) * Implements TTL protection against infinite loops using a calculated * maximum search count. * * Return: Position of the capability if found, 0 otherwise. */ -#define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, args...) \ +#define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ ({ \ u16 __pos =3D (start) ?: PCI_CFG_SPACE_SIZE; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7b0c9c09f22sm10565900b3a.20.2025.11.09.22.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Nov 2025 22:59:45 -0800 (PST) From: Qiang Yu Date: Sun, 09 Nov 2025 22:59:41 -0800 Subject: [PATCH 2/5] PCI: dwc: Add new APIs to remove standard and extended Capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251109-remove_cap-v1-2-2208f46f4dc2@oss.qualcomm.com> References: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> In-Reply-To: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Qiang Yu , Wenbin Yao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762757982; l=3697; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=/U0Ja6pIIORCOrQm8/mm85Ss8jUcFZsmQzXcPppHTe0=; b=J3FlWgLvdMzH2W746W95HHPNs+PK26TKJTJHqWKrZqsn14ptsuYN6yaflvHQCy/9ZBKICutuc dok8bavnWmTCQriP78o4FiLLIG8BeUmea5duUp0oB0jyo1dWjsSj1BQ X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-ORIG-GUID: 9S-oVuoXgXbOxE6SGDGr21m9kdcMf_rw X-Authority-Analysis: v=2.4 cv=BfDVE7t2 c=1 sm=1 tr=0 ts=69118d63 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=keqCWTWlQfiW9DbH:21 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=x49saZnIPM4AqZOLoEoA:9 a=0bXxn9q0MV6snEgNplNhOjQmxlI=:19 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: 9S-oVuoXgXbOxE6SGDGr21m9kdcMf_rw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEwMDA1OSBTYWx0ZWRfX3qg7Q71nWpR5 Ks/wOcklGdiR5a2renkMEVVAjfPuwZRlzmeO7T+s2+88nbJ+K9ZGiVF2MnzqyVozO1gOJ6CXUq2 OCE/Lf1RzCJpPya5I/vQv3hbdwvOed4MrSv34w7Gtb4FHGL9d3yWwfGea0skEoSYvuiSNmutwqa DvkhhOC4WsTxGeunVYNNp/KMIPXjHCwDtTBw3FHYOA3etVFVz7PUn/OGytlIuWcJkGC47LexmBw /COYBfUVi1viWxFmnmzJLL0Xah5Qi9/CIA1Ihd4Gy0zD2Q6/Bw39Feq96LDY8GVwTkssHXb2sFx yXUJiaIyI3LiK/bKnokKCRAHLPhIs4SWaklSpGy0ckTx6AePPSELCino1UoPEFUzlJ3LmsC3zxD mXw/0dMhtBmIkOEs8wj97fkMx7klTw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-10_02,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511100059 On some platforms, certain PCIe Capabilities may be present in hardware but are not fully implemented as defined in PCIe spec. These incomplete capabilities should be hidden from the PCI framework to prevent unexpected behavior. Introduce two APIs to remove a specific PCIe Capability and Extended Capability by updating the previous capability's next offset field to skip over the unwanted capability. These APIs allow RC drivers to easily hide unsupported or partially implemented capabilities from software. Co-developed-by: Wenbin Yao Signed-off-by: Wenbin Yao Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-designware.c | 53 ++++++++++++++++++++++++= ++++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 55 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 5585d3ed74316bd218572484f6320019db8d6a10..24f8e9959cb81ca41e91d27057c= c115d32e8d523 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -234,6 +234,59 @@ u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u= 8 cap) } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); =20 +void dw_pcie_remove_capability(struct dw_pcie *pci, u8 cap) +{ + u8 cap_pos, pre_pos, next_pos; + u16 reg; + + cap_pos =3D PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, + &pre_pos, pci); + if (!cap_pos) + return; + + reg =3D dw_pcie_readw_dbi(pci, cap_pos); + next_pos =3D (reg & 0xff00) >> 8; + + dw_pcie_dbi_ro_wr_en(pci); + if (pre_pos =3D=3D PCI_CAPABILITY_LIST) + dw_pcie_writeb_dbi(pci, PCI_CAPABILITY_LIST, next_pos); + else + dw_pcie_writeb_dbi(pci, pre_pos + 1, next_pos); + dw_pcie_dbi_ro_wr_dis(pci); +} +EXPORT_SYMBOL_GPL(dw_pcie_remove_capability); + +void dw_pcie_remove_ext_capability(struct dw_pcie *pci, u8 cap) +{ + int cap_pos, next_pos, pre_pos; + u32 pre_header, header; + + cap_pos =3D PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, &pre_pos, pci= ); + if (!cap_pos) + return; + + header =3D dw_pcie_readl_dbi(pci, cap_pos); + /* + * If the first cap at offset PCI_CFG_SPACE_SIZE is removed, + * only set it's capid to zero as it cannot be skipped. + */ + if (cap_pos =3D=3D PCI_CFG_SPACE_SIZE) { + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, cap_pos, header & 0xffff0000); + dw_pcie_dbi_ro_wr_dis(pci); + return; + } + + pre_header =3D dw_pcie_readl_dbi(pci, pre_pos); + next_pos =3D PCI_EXT_CAP_NEXT(header); + + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, pre_pos, + (pre_header & 0xfffff) | (next_pos << 20)); + dw_pcie_dbi_ro_wr_dis(pci); +} +EXPORT_SYMBOL_GPL(dw_pcie_remove_ext_capability); + static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_= id, u16 vsec_id) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index e995f692a1ecd10130d3be3358827f801811387f..b68dbc528001b63448db8b1a93b= f56a5e53bd33e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -552,6 +552,8 @@ void dw_pcie_version_detect(struct dw_pcie *pci); =20 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +void dw_pcie_remove_capability(struct dw_pcie *pci, u8 cap); +void dw_pcie_remove_ext_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci); u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci); =20 --=20 2.34.1 From nobody Sun Feb 8 05:40:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16EBD2EA156 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7b0c9c09f22sm10565900b3a.20.2025.11.09.22.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Nov 2025 22:59:46 -0800 (PST) From: Qiang Yu Date: Sun, 09 Nov 2025 22:59:42 -0800 Subject: [PATCH 3/5] PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251109-remove_cap-v1-3-2208f46f4dc2@oss.qualcomm.com> References: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> In-Reply-To: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762757982; l=2379; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=hqQvTcsdaEoA9+Xh3Z8OKwCXQnyyBaKEZqGjPB6mXCc=; b=a9TNQphv0olEWd4VZeZicZIvivZzIDMYwEDpaxxIOnLRVfiJaisq6pzmb71V78utdnylUOr5k l1B9B2hAcppCFWYavnsq836rkyolkarAOQc99T9xPK87VlrsLQifiEs X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEwMDA1OSBTYWx0ZWRfX+cFaA6YunZ0G vttRNbNWPe/BIy0YPKbY9O8padLfbHA8L9+eOV56UK9aG4LwGHY/QAeCfpMWAyLGfNQZ52sLelU K56czLNNhq/j0Zejm0FbApNKRYaqm0rfXtGUAogFor66fHS+bUPj9N76gHe9R17iz3lXv5S/Ik9 iSWeeLFmDOy1Tr/Uh41WKb9MzJuIk6uNCbfVDdqHKXCdCFo1XwXqbT2OIQTgvGj2vVHjaJZlZOU rI+XlQcOgIBrUXgptq5nU3ipf7BV5pqq4x9Vyo5Z71B97FOn9dJUZOowe4VtJIbqQrN3LwLCsD+ weI1Eh0qimeutH2XedyPK6+kIcGIoCwjW3a8EmNOxd+A/SiJ9doTs74S4K2KB6LmX9/UkqFa8lJ TIh3akn5IsNCqVLx09M2lm1cSqHEYA== X-Proofpoint-GUID: 8gkIaOKupBE3iiGu-MtsdLVQ-0BDE7eY X-Proofpoint-ORIG-GUID: 8gkIaOKupBE3iiGu-MtsdLVQ-0BDE7eY X-Authority-Analysis: v=2.4 cv=BOK+bVQG c=1 sm=1 tr=0 ts=69118d63 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=q7mzEFEhQNumAzJHHS8A:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-10_02,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 spamscore=0 malwarescore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511100059 Some platforms may not support ITS (Interrupt Translation Service) and MBI (Message Based Interrupt), or there are not enough available empty SPI lines for MBI, in which case the msi-map and msi-parent property will not be provided in device tree node. For those cases, the DWC PCIe driver defaults to using the iMSI-RX module as MSI controller. However, due to DWC IP design, iMSI-RX cannot generate MSI interrupts for Root Ports even when MSI is properly configured and supported as iMSI-RX will only monitor and intercept incoming MSI TLPs from PCIe link, but the memory write generated by Root Port are internal system bus transactions instead of PCIe TLPs, so they are ignored. This leads to interrupts such as PME, AER from the Root Port not received on the host and the users have to resort to workarounds such as passing "pcie_pme=3Dnomsi" cmdline parameter. To ensure reliable interrupt handling, remove MSI and MSI-X capabilities from Root Ports when using iMSI-RX as MSI controller, which is indicated by has_msi_ctrl =3D=3D true. This forces a fallback to INTx interrupts, eliminating the need for manual kernel command line workarounds. With this behavior: - Platforms with ITS/MBI support use ITS/MBI MSI for interrupts from all components. - Platforms without ITS/MBI support fall back to INTx for Root Ports and use iMSI-RX for other PCI devices. Signed-off-by: Qiang Yu Reviewed-by: Brian Norris Tested-by: Brian Norris --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 20c9333bcb1c4812e2fd96047a49944574df1e6f..3724aa7f9b356bfba33a6515e2c= 62a3170aef1e9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1083,6 +1083,16 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) =20 dw_pcie_dbi_ro_wr_dis(pci); =20 + /* + * If iMSI-RX module is used as the MSI controller, remove MSI and + * MSI-X capabilities from PCIe Root Ports to ensure fallback to INTx + * interrupt handling. + */ + if (pp->has_msi_ctrl) { + dw_pcie_remove_capability(pci, PCI_CAP_ID_MSI); + dw_pcie_remove_capability(pci, PCI_CAP_ID_MSIX); + } + return 0; } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); --=20 2.34.1 From nobody Sun Feb 8 05:40:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5BD02EAB61 for ; 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However, it omits the required MSI-X Table and PBA structures. This mismatch can lead to issues where the PCIe port driver requests MSI-X instead of MSI, causing the Root Port to trigger interrupts by writing to an uninitialized address, resulting in SMMU faults. To address this, remove MSI-X capability unconditionally for Root Ports. Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 805edbbfe7eba496bc99ca82051dee43d240f359..09443ffbb150e9c91bfd3b2adf1= 5286ef2f00a2a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1350,6 +1350,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) goto err_disable_phy; } =20 + dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); + qcom_ep_reset_deassert(pcie); =20 if (pcie->cfg->ops->config_sid) { --=20 2.34.1 From nobody Sun Feb 8 05:40:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C40932EA732 for ; Mon, 10 Nov 2025 06:59:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7b0c9c09f22sm10565900b3a.20.2025.11.09.22.59.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Nov 2025 22:59:47 -0800 (PST) From: Qiang Yu Date: Sun, 09 Nov 2025 22:59:44 -0800 Subject: [PATCH 5/5] PCI: qcom: Remove DPC Extended Capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251109-remove_cap-v1-5-2208f46f4dc2@oss.qualcomm.com> References: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> In-Reply-To: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Qiang Yu , Wenbin Yao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762757982; l=1170; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=FEATCEIhTHMz7b3SDtTSGozMG3s3HSCmKvUHkBi8n1w=; b=7LHbWxRs1CZJ6up1opRxZmF8nyfMw1R5TXGUaO+VWMOWI9Cdw76BRGYMkj2u2t6JT8UTIFEXQ woxRuWtw+t+DQ56tVmZCnsVjxR0YX7zCcTHOEddtozmDDVD+0lkXXrT X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-ORIG-GUID: M7BEc5m5IyyUTPIr0s2DY3CmABEJpCNu X-Authority-Analysis: v=2.4 cv=BfDVE7t2 c=1 sm=1 tr=0 ts=69118d65 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=LA3sOWcMmZYsM6F2gv0A:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: M7BEc5m5IyyUTPIr0s2DY3CmABEJpCNu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEwMDA1OSBTYWx0ZWRfX2lQKQCInRu+/ 2dOZYRpC93IlQlw7smw59t+6RTjs52UMmKAB9AU/1KBH8VzoeDzafOqo/PXkpkQX/aIs7SUYtIt zA1g3k2uqRYLGw5Y3VTdtKNJx0IBW3cBFDz4aa4F2Os8jr3AAwnf/OGTe/nKoKZju6vK+plCR4I FTHd5w/9X5VTPlEPnCiPkIJ2NVmMXBUib4YgcKPVbFb/oNvvfp9DDjTdEnC28E0JeajIVpfyyJm ghf98+d3AV58JrIU8tDPoAO4bVEOgBf8Ld1Ii5ThXoMdR7MMHUnjbCXfq22mEaClw7HptVDAPKB XOJ1wX4LnG673Mq7LVJKJnoBL0n82hDIY3qQMB0wh9ZT0fPn5FqrEXqTnt+8nDO7f+1kydikUEf IG0gZPVqq/ekdaqyIG4UL74VMdpDsg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-10_02,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511100059 Some platforms (e.g., X1E80100) expose Downstream Port Containment (DPC) Extended Capability registers in the PCIe Root Port config space, but do not fully support it. To prevent undefined behavior and ensure DPC cap is not visible to PCI framework and users, remove DPC Extended Capability unconditionally, since there is no qcom platform support DPC till now. Co-developed-by: Wenbin Yao Signed-off-by: Wenbin Yao Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 09443ffbb150e9c91bfd3b2adf15286ef2f00a2a..1b0f72bc38d912ab46739aa7f90= 4ceca617c668d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1351,6 +1351,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) } =20 dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); + dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); =20 qcom_ep_reset_deassert(pcie); =20 --=20 2.34.1