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[2a02:3100:a9b3:6600:1e86:bff:fe2f:57b7]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-6411f814164sm7642807a12.13.2025.11.08.15.13.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Nov 2025 15:13:22 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ulf.hansson@linaro.org, Martin Blumenstingl Subject: [PATCH v1 3/7] mmc: meson-mx-sdio: Refactor internal clock initialization Date: Sun, 9 Nov 2025 00:12:49 +0100 Message-ID: <20251108231253.1641927-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251108231253.1641927-1-martin.blumenstingl@googlemail.com> References: <20251108231253.1641927-1-martin.blumenstingl@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use modern common clock framework helpers for simplifying the clock controller management: - switch to struct clk_hw for internal clocks and only get the "cfg_div_clk" (which has to be managed at runtime) as struct clk using devm_clk_hw_get_clk() which is then the only clock used by struct meson_mx_mmc_host. - use CLK_HW_INIT_FW_NAME and CLK_HW_INIT_HW helper macros for simpler init data initialization - keep the clock controller memory allocation separate to prevent a potential use-after-free because struct meson_mx_mmc_host_clkc is free'd before controller_dev Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong --- drivers/mmc/host/meson-mx-sdio.c | 119 ++++++++++++++++--------------- 1 file changed, 61 insertions(+), 58 deletions(-) diff --git a/drivers/mmc/host/meson-mx-sdio.c b/drivers/mmc/host/meson-mx-s= dio.c index 1159cc911359..ce1828d915da 100644 --- a/drivers/mmc/host/meson-mx-sdio.c +++ b/drivers/mmc/host/meson-mx-sdio.c @@ -99,15 +99,15 @@ #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1) #define MESON_MX_SDIO_MAX_SLOTS 3 =20 +struct meson_mx_mmc_host_clkc { + struct clk_divider cfg_div; + struct clk_fixed_factor fixed_div2; +}; + struct meson_mx_mmc_host { struct device *controller_dev; =20 - struct clk *parent_clk; - struct clk_divider cfg_div; struct clk *cfg_div_clk; - struct clk_fixed_factor fixed_factor; - struct clk *fixed_factor_clk; - struct regmap *regmap; int irq; spinlock_t irq_lock; @@ -548,8 +548,7 @@ static int meson_mx_mmc_add_host(struct meson_mx_mmc_ho= st *host) =20 /* Get the min and max supported clock rates */ mmc->f_min =3D clk_round_rate(host->cfg_div_clk, 1); - mmc->f_max =3D clk_round_rate(host->cfg_div_clk, - clk_get_rate(host->parent_clk)); + mmc->f_max =3D clk_round_rate(host->cfg_div_clk, ULONG_MAX); =20 mmc->caps |=3D MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY; mmc->ops =3D &meson_mx_mmc_ops; @@ -565,54 +564,62 @@ static int meson_mx_mmc_add_host(struct meson_mx_mmc_= host *host) return 0; } =20 -static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host, - void __iomem *base) +static struct clk *meson_mx_mmc_register_clk(struct device *dev, + void __iomem *base) { - struct clk_init_data init; - const char *clk_div_parent, *clk_fixed_factor_parent; - - clk_fixed_factor_parent =3D __clk_get_name(host->parent_clk); - init.name =3D devm_kasprintf(host->controller_dev, GFP_KERNEL, - "%s#fixed_factor", - dev_name(host->controller_dev)); - if (!init.name) - return -ENOMEM; + const char *fixed_div2_name, *cfg_div_name; + struct meson_mx_mmc_host_clkc *host_clkc; + struct clk *clk; + int ret; =20 - init.ops =3D &clk_fixed_factor_ops; - init.flags =3D 0; - init.parent_names =3D &clk_fixed_factor_parent; - init.num_parents =3D 1; - host->fixed_factor.div =3D 2; - host->fixed_factor.mult =3D 1; - host->fixed_factor.hw.init =3D &init; - - host->fixed_factor_clk =3D devm_clk_register(host->controller_dev, - &host->fixed_factor.hw); - if (WARN_ON(IS_ERR(host->fixed_factor_clk))) - return PTR_ERR(host->fixed_factor_clk); - - clk_div_parent =3D __clk_get_name(host->fixed_factor_clk); - init.name =3D devm_kasprintf(host->controller_dev, GFP_KERNEL, - "%s#div", dev_name(host->controller_dev)); - if (!init.name) - return -ENOMEM; + /* use a dedicated memory allocation for the clock controller to + * prevent use-after-free as meson_mx_mmc_host is free'd before + * dev (controller dev, not mmc_host->dev) is free'd. + */ + host_clkc =3D devm_kzalloc(dev, sizeof(*host_clkc), GFP_KERNEL); + if (!host_clkc) + return ERR_PTR(-ENOMEM); + + fixed_div2_name =3D devm_kasprintf(dev, GFP_KERNEL, "%s#fixed_div2", + dev_name(dev)); + if (!fixed_div2_name) + return ERR_PTR(-ENOMEM); + + host_clkc->fixed_div2.div =3D 2; + host_clkc->fixed_div2.mult =3D 1; + host_clkc->fixed_div2.hw.init =3D CLK_HW_INIT_FW_NAME(fixed_div2_name, + "clkin", + &clk_fixed_factor_ops, + 0); + ret =3D devm_clk_hw_register(dev, &host_clkc->fixed_div2.hw); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Failed to register %s clock\n", + fixed_div2_name); + + cfg_div_name =3D devm_kasprintf(dev, GFP_KERNEL, "%s#div", dev_name(dev)); + if (!cfg_div_name) + return ERR_PTR(-ENOMEM); + + host_clkc->cfg_div.reg =3D base + MESON_MX_SDIO_CONF; + host_clkc->cfg_div.shift =3D MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT; + host_clkc->cfg_div.width =3D MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH; + host_clkc->cfg_div.hw.init =3D CLK_HW_INIT_HW(cfg_div_name, + &host_clkc->fixed_div2.hw, + &clk_divider_ops, + CLK_DIVIDER_ALLOW_ZERO); + ret =3D devm_clk_hw_register(dev, &host_clkc->cfg_div.hw); + if (ret) + return dev_err_ptr_probe(dev, ret, + "Failed to register %s clock\n", + cfg_div_name); =20 - init.ops =3D &clk_divider_ops; - init.flags =3D CLK_SET_RATE_PARENT; - init.parent_names =3D &clk_div_parent; - init.num_parents =3D 1; - host->cfg_div.reg =3D base + MESON_MX_SDIO_CONF; - host->cfg_div.shift =3D MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT; - host->cfg_div.width =3D MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH; - host->cfg_div.hw.init =3D &init; - host->cfg_div.flags =3D CLK_DIVIDER_ALLOW_ZERO; - - host->cfg_div_clk =3D devm_clk_register(host->controller_dev, - &host->cfg_div.hw); - if (WARN_ON(IS_ERR(host->cfg_div_clk))) - return PTR_ERR(host->cfg_div_clk); + clk =3D devm_clk_hw_get_clk(dev, &host_clkc->cfg_div.hw, "cfg_div_clk"); + if (IS_ERR(clk)) + return dev_err_ptr_probe(dev, PTR_ERR(clk), + "Failed to get the cfg_div clock\n"); =20 - return 0; + return clk; } =20 static int meson_mx_mmc_probe(struct platform_device *pdev) @@ -682,16 +689,12 @@ static int meson_mx_mmc_probe(struct platform_device = *pdev) goto error_free_mmc; } =20 - host->parent_clk =3D devm_clk_get(host->controller_dev, "clkin"); - if (IS_ERR(host->parent_clk)) { - ret =3D PTR_ERR(host->parent_clk); + host->cfg_div_clk =3D meson_mx_mmc_register_clk(&pdev->dev, base); + if (IS_ERR(host->cfg_div_clk)) { + ret =3D PTR_ERR(host->cfg_div_clk); goto error_free_mmc; } =20 - ret =3D meson_mx_mmc_register_clks(host, base); - if (ret) - goto error_free_mmc; - ret =3D clk_prepare_enable(host->cfg_div_clk); if (ret) { dev_err(host->controller_dev, "Failed to enable MMC clock\n"); --=20 2.51.2