From nobody Mon Feb 9 05:38:09 2026 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E71E52BE02D for ; Sat, 8 Nov 2025 19:42:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762630966; cv=none; b=frAVYhM66oafgvF8Sd35t8ZcsQuzZENtkinMnHtryDEgJFNCEl2Zoujbn6y4cr6B7h1xDgYqakZ6lEMDkDb6l4nxZczs6UeHYvtBRgE7pX92umMSkVxGJ4VY3EiZa+eQvf8k0jj/4XvkN3F1QnZJSbKtfnktCxGIa0VYPKWkrHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762630966; c=relaxed/simple; bh=/5P54JZsVoEIjyCnuoFOoFiiaakzGZYJndoJ6oDwTIc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DEyPxzVOF/amcLLkU/PW8aSH8Xpki1v+Qmri9xN22D45o/eoU+sK4RAEUaxmq7FyRWSTXRiPKSbDEL94knO4uElm0TCnlUSIsm/X1XuF3GmxltmvXv82KrfAwLltqEHKxRJ9YP6v3BbMezlQ7U3iJmJxTXoJUH3EpXoiOg1Nm3Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Fng0M7al; arc=none smtp.client-ip=209.85.208.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Fng0M7al" Received: by mail-lj1-f180.google.com with SMTP id 38308e7fff4ca-378d6fa5aebso15300561fa.2 for ; Sat, 08 Nov 2025 11:42:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1762630962; x=1763235762; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+bbYFW276/qh6UIEkMA7XQhtcFTp5iMt1YWKBt+vv1Y=; b=Fng0M7aleQDoiA0LNJU6sIAzkEmZy1qSiWJVp6QBssy2Nj8ecsdBvrW3w39MLrsTBX Iu9j449WhLlc+6eVlyliX11EtO1IZxKHjpb2g6onmut6Gyg3L/Nsk7f6ZQiLRU6Sq9+v u+52lsGCzllOWJHoXRnapULNQLE/Xz220h65D+EgPNzp6zSAbAbyeYZWpgcii9dY/cVJ Ugt4RnaCFE/lTig+DZyjQLpzMRv7PzGaq/Z8i9wZeEUwab+2au8XoJDN8POTaGJ8tEvc fhaU2LSAc6e34lA8A0ihI0D5ITIG1YBpC3BZCntkgqUnX7Fz1vlUiX4iTGEQWHILh0rh Wj2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762630962; x=1763235762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+bbYFW276/qh6UIEkMA7XQhtcFTp5iMt1YWKBt+vv1Y=; b=II2y016yI0WcrljEYMxcL+QyAbubRzioiysa6P7C4+FneFtWBQ0PK3eA0pytP/ER1H 3Sbzad3mBY1UPFtL/emDttXLnKnW6QNKR3PLuadeVC4XDlGB9f7lerRaJbIC4YK1lliz 69lvqg+Kr++ffzC4bpqcBHV1MYGENqP53q5YEvSILYKbPlvPeGjJ//qfRkCwr/qtcEfJ r6iE5WWIWjx+BZu5lb218VLBbFP+LkRzJhh9BvTcFYOSnrrAYyaJVXwcfHAfk3hlqqgl Q3xxniQzimUPY76ovnvSdBzjn/Og73WEMcvBJlGtHIXh5kPM1E2FdbsIFuWaVRffa5v+ 2YVw== X-Forwarded-Encrypted: i=1; AJvYcCXYuMGaesIj41hC6JkXnNpadIWmp1ckPckiKmeq3QXpe87Vai2xcVTv75rpHGeMFR/Khx22PKpvlwNAjjU=@vger.kernel.org X-Gm-Message-State: AOJu0Yy9+PW6aQZfsz+ZQvkmadmPChhU6x4B6LaALWluGrCUFR/LFmIO P7Ryv711WsRvK1dKvQRAJmfXPnL4MtpUHO3yoGh44tMszb/jCPKVzHv0 X-Gm-Gg: ASbGnctv8eQY5ZLyP/4F/VkizXOr4iORxLBku6pyI1/za3m79z/XKWJAjrwHAF62TqD 3JX6ucv5Ysgj3Xv2vD2CiZhTlBBldkWTfqAnonrnpP4XtHMgubU3faeP5e3Al870bgYLNL6qY+g 7JrfjG86U5Reex9yNa7BrYi776OJ2eVUJKTnDE06mpGVYGf212mnHWv6IelTsAQ/zXxEP24PsQK NtzPfGyBDvnQPnw7Aa3E3106UB6GwPBtM/PlsfrcrgR3lHrqcLZ+9a+AY7+itbpl+ufq0OuGs7W /AMvcADGa4UHpM0dYK8GmBsHTkAvASYlRTl80eR0QKNBMAkXHpxQleTH3ZfUWBCwYUFmEz9sXcQ uBGFUIEJVRA+OPdk3+SZAiMUosmnKx7Ltn7E4uFnPJYAfo29LmVC4flrgES50UZepYCSR8DLY6n +zfQ== X-Google-Smtp-Source: AGHT+IGbqfLpIHEmSZirHycm/m3Wf8olNlfmXdlwHAR/tE60r7C92aNsJU96025k0i2AD9bl/9coAw== X-Received: by 2002:a05:651c:e19:b0:37a:4d6a:313b with SMTP id 38308e7fff4ca-37a7b1d8abdmr5874861fa.17.1762630961836; Sat, 08 Nov 2025 11:42:41 -0800 (PST) Received: from curiosity ([5.188.167.4]) by smtp.googlemail.com with ESMTPSA id 38308e7fff4ca-37a5f0edac3sm22115421fa.38.2025.11.08.11.42.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Nov 2025 11:42:40 -0800 (PST) From: Sergey Matyukevich To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Oleg Nesterov , Shuah Khan , Thomas Huth , Charlie Jenkins , Andy Chiu , Samuel Holland , Joel Granados , Conor Dooley , Yong-Xuan Wang , Heiko Stuebner , Sergey Matyukevich Subject: [PATCH v4 7/9] selftests: riscv: verify ptrace rejects invalid vector csr inputs Date: Sat, 8 Nov 2025 22:41:46 +0300 Message-ID: <20251108194207.1257866-8-geomatsi@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251108194207.1257866-1-geomatsi@gmail.com> References: <20251108194207.1257866-1-geomatsi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a test to v_ptrace test suite to verify that ptrace rejects the invalid input combinations of vector csr registers. Use kselftest fixture variants to create multiple invalid inputs for the test. Signed-off-by: Sergey Matyukevich --- .../testing/selftests/riscv/vector/v_ptrace.c | 238 ++++++++++++++++++ 1 file changed, 238 insertions(+) diff --git a/tools/testing/selftests/riscv/vector/v_ptrace.c b/tools/testin= g/selftests/riscv/vector/v_ptrace.c index 9fea29f7b686..023e1faa84bf 100644 --- a/tools/testing/selftests/riscv/vector/v_ptrace.c +++ b/tools/testing/selftests/riscv/vector/v_ptrace.c @@ -183,4 +183,242 @@ TEST(ptrace_v_early_debug) } } =20 +FIXTURE(v_csr_invalid) +{ +}; + +FIXTURE_SETUP(v_csr_invalid) +{ +} + +FIXTURE_TEARDOWN(v_csr_invalid) +{ +} + +/* modifications of the initial vsetvli settings */ +FIXTURE_VARIANT(v_csr_invalid) +{ + unsigned long vstart; + unsigned long vl; + unsigned long vtype; + unsigned long vcsr; + unsigned long vlenb_mul; + unsigned long vlenb_min; + unsigned long vlenb_max; +}; + +/* unexpected vlenb value */ +FIXTURE_VARIANT_ADD(v_csr_invalid, new_vlenb) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x3, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x2, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* invalid reserved bits in vcsr */ +FIXTURE_VARIANT_ADD(v_csr_invalid, vcsr_invalid_reserved_bits) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x3, + .vcsr =3D 0x1UL << 8, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* invalid reserved bits in vtype */ +FIXTURE_VARIANT_ADD(v_csr_invalid, vtype_invalid_reserved_bits) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D (0x1UL << 8) | 0x3, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* set vill bit */ +FIXTURE_VARIANT_ADD(v_csr_invalid, invalid_vill_bit) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D (0x1UL << (__riscv_xlen - 1)) | 0x3, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* reserved vsew value: vsew > 3 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vsew) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x4UL << 3, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* reserved vlmul value: vlmul =3D=3D 4 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vlmul) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x4, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* invalid fractional LMUL for VLEN <=3D 256: LMUL=3D 1/8, SEW =3D 64 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, frac_lmul1) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x1d, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x20, +}; + +/* invalid integral LMUL for VLEN <=3D 16: LMUL=3D 2, SEW =3D 64 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, int_lmul1) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x19, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x2, +}; + +/* invalid VL for VLEN <=3D 128: LMUL=3D 2, SEW =3D 64, VL =3D 8 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, vl1) +{ + .vstart =3D 0x0, + .vl =3D 0x8, + .vtype =3D 0x19, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x10, +}; + +TEST_F(v_csr_invalid, ptrace_v_invalid_values) +{ + unsigned long vlenb; + pid_t pid; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + asm volatile("csrr %[vlenb], vlenb" : [vlenb] "=3Dr"(vlenb)); + if (variant->vlenb_min) { + if (vlenb < variant->vlenb_min) + SKIP(return, "This test does not support VLEN < %lu\n", + variant->vlenb_min * 8); + } + if (variant->vlenb_max) { + if (vlenb > variant->vlenb_max) + SKIP(return, "This test does not support VLEN > %lu\n", + variant->vlenb_max * 8); + } + + chld_lock =3D 1; + pid =3D fork(); + ASSERT_LE(0, pid) + TH_LOG("fork: %m"); + + if (pid =3D=3D 0) { + unsigned long vl; + + while (chld_lock =3D=3D 1) + asm volatile("" : : "g"(chld_lock) : "memory"); + + asm(".option arch, +zve32x\n"); + asm(".option arch, +c\n"); + + asm volatile("vsetvli %[new_vl], x0, e16, m2, tu, mu\n" + : [new_vl] "=3Dr"(vl) + : + :); + + while (1) { + asm volatile("c.ebreak"); + asm volatile("c.nop"); + } + } else { + struct __riscv_v_regset_state *regset_data; + size_t regset_size; + struct iovec iov; + int status; + int ret; + + /* attach */ + + ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL)); + ASSERT_EQ(pid, waitpid(pid, &status, 0)); + ASSERT_TRUE(WIFSTOPPED(status)); + + /* unlock */ + + ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0)); + + /* resume and wait for the 1st c.ebreak */ + + ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL)); + ASSERT_EQ(pid, waitpid(pid, &status, 0)); + ASSERT_TRUE(WIFSTOPPED(status)); + + /* read tracee vector csr regs using ptrace GETREGSET */ + + regset_size =3D sizeof(*regset_data) + vlenb * 32; + regset_data =3D calloc(1, regset_size); + + iov.iov_base =3D regset_data; + iov.iov_len =3D regset_size; + + ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov)); + + /* verify initial vsetvli settings */ + + EXPECT_EQ(regset_data->vlenb, regset_data->vl); + EXPECT_EQ(9UL, regset_data->vtype); + EXPECT_EQ(vlenb, regset_data->vlenb); + EXPECT_EQ(0UL, regset_data->vstart); + EXPECT_EQ(0UL, regset_data->vcsr); + + /* apply invalid settings from fixture variants */ + + regset_data->vlenb *=3D variant->vlenb_mul; + regset_data->vstart =3D variant->vstart; + regset_data->vtype =3D variant->vtype; + regset_data->vcsr =3D variant->vcsr; + regset_data->vl =3D variant->vl; + + iov.iov_base =3D regset_data; + iov.iov_len =3D regset_size; + + errno =3D 0; + ret =3D ptrace(PTRACE_SETREGSET, pid, NT_RISCV_VECTOR, &iov); + ASSERT_EQ(errno, EINVAL); + ASSERT_EQ(ret, -1); + + /* cleanup */ + + ASSERT_EQ(0, kill(pid, SIGKILL)); + } +} + TEST_HARNESS_MAIN --=20 2.51.0