From nobody Mon Feb 9 00:34:53 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C12C41AB6F1; Sat, 8 Nov 2025 01:05:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762563905; cv=none; b=dOKMB6ZuHmwm6Gdicmo/W/6Dw2j0zdnhWz9AESMJvLeEYsKTbIuGe/1TcI/Qnz1y9NS2I45Z/mKF59VagDPP71IoXmKPcutEWcQgaOqs5EcjB0MB903OB/MYYbCYP46kL4jdIyftG7lJxgLC/c2w2G0yjF8yyxlHKdyOmgjJ5qs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762563905; c=relaxed/simple; bh=StkRq8n4Fk6z8+fAS35iJvY72BBqJ82u4pK3/DXJicA=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=F/wb+RhmKPhD3KCssE4EFDvZLqkfEs8MqseWRxD0dv/kvkFLpm1QX2FQa+VqSbNut18tTgk4S2t1IZGOEmY3F88+RzjgW/bmToV6JnF/Mps5YnQjaSt5vaFJVggjRZ7MbPqWNtpWSh/A58P7HcVQ3bot5AH/1KhmLZUjaxeRQR8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=lvINEcdW; arc=none smtp.client-ip=210.118.77.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="lvINEcdW" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20251108010454euoutp0175b1ad0327b65a199402c22c6778bf22~14oXzLP4L2093120931euoutp01U; Sat, 8 Nov 2025 01:04:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20251108010454euoutp0175b1ad0327b65a199402c22c6778bf22~14oXzLP4L2093120931euoutp01U DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1762563894; bh=QPKOABNr+nSvn9PQTNle3vFMJNkD4N3hf3pKiqLT21I=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=lvINEcdWmcVtASBpvsheui6gsQ4SdwlNE9ew62E0uJgp6BdM1gCNhfhgqFt0V/QrD vlPs2aZDff0oW71VFOhLHmpM9OKMzBDRk3t2WkiLWP8GlvUGtsBLJNs9ZYbSAvKomJ LVO43hWuA3ZKp5r86xmEmyFNXPNO7jyWK+CfsAXQ= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20251108010453eucas1p2403ec0dd2c69ae7f3eabe19cf686f345~14oXAXk2y0323703237eucas1p2Z; Sat, 8 Nov 2025 01:04:53 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010451eusmtip2669791b6fd771047c3331027cb747f68~14oVmxMGY2515425154eusmtip2X; Sat, 8 Nov 2025 01:04:51 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:35 +0100 Subject: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-1-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010453eucas1p2403ec0dd2c69ae7f3eabe19cf686f345 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010453eucas1p2403ec0dd2c69ae7f3eabe19cf686f345 X-EPHeader: CA X-CMS-RootMailID: 20251108010453eucas1p2403ec0dd2c69ae7f3eabe19cf686f345 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Add the dt-binding documentation for the StarFive JH7110 Video Output (VOUT) subsystem. This node acts as a parent for all devices within the VOUT power domain, including the DC8200 display controller, the VOUTCRG clock generator, and the HDMI MFD block. Its driver is responsible for managing the shared power domain and top-level bus clocks for these children. It is a bit similar to the display subsystem qcom,sdm845-mdss DT node. Signed-off-by: Michal Wilczynski --- .../starfive/starfive,jh7110-vout-subsystem.yaml | 156 +++++++++++++++++= ++++ MAINTAINERS | 5 + 2 files changed, 161 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110= -vout-subsystem.yaml b/Documentation/devicetree/bindings/soc/starfive/starf= ive,jh7110-vout-subsystem.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4ad9423ea139a537b4cfea26b0e= d4ed263aa14a1 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-s= ubsystem.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-vout-subsy= stem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 VOUT (Video Output) Subsystem + +maintainers: + - Michal Wilczynski + +description: + The JH7110 video output subsystem is an IP block that contains + the display controller (DC8200), HDMI controller/PHY, and VOUT + clock generator (VOUTCRG). + +properties: + compatible: + const: starfive,jh7110-vout-subsystem + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + ranges: true + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + +patternProperties: + "^display@[0-9a-f]+$": + type: object + description: Verisilicon DC8200 Display Controller node. + + "^hdmi@[0-9a-f]+$": + type: object + description: StarFive HDMI MFD (PHY + Controller) node. + + "^clock-controller@[0-9a-f]+$": + type: object + description: StarFive VOUT Clock Generator (VOUTCRG) node. + + "^syscon@[0-9a-f]+$": + type: object + description: StarFive VOUT Syscon node. + +required: + - compatible + - reg + - power-domains + - clocks + - resets + - ranges + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + vout_subsystem: display-subsystem@29400000 { + compatible =3D "starfive,jh7110-vout-subsystem"; + reg =3D <0x0 0x29400000 0x0 0x200000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + power-domains =3D <&pwrc JH7110_PD_VOUT>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>; + resets =3D <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>; + + dc8200: display@29400000 { + compatible =3D "verisilicon,dc"; + reg =3D <0x0 0x29400000 0x0 0x2800>; + interrupts =3D <95>; + clocks =3D <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>; + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; + resets =3D <&voutcrg JH7110_VOUTRST_DC8200_AXI>, + <&voutcrg JH7110_VOUTRST_DC8200_AHB>, + <&voutcrg JH7110_VOUTRST_DC8200_CORE>; + reset-names =3D "axi", "ahb", "core"; + }; + + hdmi_mfd: hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-mfd"; + reg =3D <0x0 0x29590000 0x0 0x4000>; + interrupts =3D <99>; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + clocks =3D <&xin24m>; + clock-names =3D "refoclk"; + #clock-cells =3D <0>; + clock-output-names =3D "hdmi_pclk"; + #phy-cells =3D <0>; + }; + + hdmi_controller: controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + interrupts =3D <99>; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "sys", "mclk", "bclk", "pclk"; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + reset-names =3D "hdmi_tx"; + phys =3D <&hdmi_phy>; + phy-names =3D "hdmi-phy"; + }; + }; + + voutcrg: clock-controller@295c0000 { + compatible =3D "starfive,jh7110-voutcrg"; + reg =3D <0x0 0x295c0000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmi_phy>; + clock-names =3D "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets =3D <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + reset-names =3D "vout_top"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 348caaaa929a519bc0ec5c0c7b587468ef7532d5..99434e54dc39494153677a6ca35= 9d70f2ba2ddb3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24044,6 +24044,11 @@ S: Maintained F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c =20 +STARFIVE JH7110 DISPLAY SUBSYSTEM +M: Michal Wilczynski +S: Maintained +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-sub= system.yaml + STARFIVE JH7110 DPHY RX DRIVER M: Jack Zhu M: Changhuang Liang --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0646291C1F; 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Sat, 8 Nov 2025 01:04:54 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010453eusmtip2f17ee4f4ef809e0111d98d420ce81c1d~14oXEeKei0912409124eusmtip2R; Sat, 8 Nov 2025 01:04:53 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:36 +0100 Subject: [PATCH RFC 02/13] dt-bindings: clock: jh7110: Make power-domain optional Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-2-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010454eucas1p103697b195125d853bd9f4d40662b681e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010454eucas1p103697b195125d853bd9f4d40662b681e X-EPHeader: CA X-CMS-RootMailID: 20251108010454eucas1p103697b195125d853bd9f4d40662b681e References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> The voutcrg (Video Output Clock Generator) hardware resides within the PD_VOUT power domain. In the new display subsystem model, this power domain is managed by the top-level 'vout-subsystem' parent driver. Because the parent driver now handles power management, the voutcrg node in the device tree no longer needs a 'power-domains' property. This patch updates the voutcrg binding to reflect this by removing 'power-domains' from the list of required properties. This fixes a dtbs_check warning that would be triggered by the updated device tree. Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcr= g.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.ya= ml index af77bd8c86b12e667b79ffbaeae5f8a82e6d3f37..deff69037e5072002e06aa5a899= f4488b7264f47 100644 --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml @@ -61,7 +61,6 @@ required: - resets - '#clock-cells' - '#reset-cells' - - power-domains =20 additionalProperties: false =20 --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 313062BD02A; Sat, 8 Nov 2025 01:05:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 8 Nov 2025 01:04:56 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010454eusmtip2c99c393e840653a6a60f6de581bc622c~14oYiDJKP2515425154eusmtip2Y; Sat, 8 Nov 2025 01:04:54 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:37 +0100 Subject: [PATCH RFC 03/13] dt-bindings: phy: Add starfive,jh7110-inno-hdmi-phy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-3-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010456eucas1p2a8b17a5c7403ce133e8ed2dd3481c4f0 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010456eucas1p2a8b17a5c7403ce133e8ed2dd3481c4f0 X-EPHeader: CA X-CMS-RootMailID: 20251108010456eucas1p2a8b17a5c7403ce133e8ed2dd3481c4f0 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Add the dt-binding for the StarFive JH7110 Innosilicon HDMI PHY. This device is a child of the starfive,jh7110-hdmi-mfd node. It functions as both a PHY provider for the controller and as a clock provider for the variable pixel clock (hdmi_pclk), which it generates from its refoclk. Signed-off-by: Michal Wilczynski --- .../phy/starfive,jh7110-inno-hdmi-phy.yaml | 65 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 66 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdm= i-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdm= i-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a737ba767d4aa7c6cba197dc031= 4bdbb163930c8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.y= aml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-inno-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Innosilicon INNO HDMI PHY + +maintainers: + - Michal Wilczynski + +description: + The PHY portion of the StarFive JH7110 INNO HDMI IP. + +properties: + compatible: + const: starfive,jh7110-inno-hdmi-phy + + clocks: + maxItems: 1 + + clock-names: + const: refoclk + + '#clock-cells': + const: 0 + + clock-output-names: + const: hdmi_pclk + + '#phy-cells': + const: 0 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + - clock-output-names + - '#phy-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + hdmi_mfd: hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-mfd"; + reg =3D <0x29590000 0x4000>; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + clocks =3D <&xin24m>; + clock-names =3D "refoclk"; + #clock-cells =3D <0>; + clock-output-names =3D "hdmi_pclk"; + #phy-cells =3D <0>; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 99434e54dc39494153677a6ca359d70f2ba2ddb3..a75ba7a44ee84db6a75b91c1a08= 67a37db2ebcdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24047,6 +24047,7 @@ F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfi= ve.c STARFIVE JH7110 DISPLAY SUBSYSTEM M: Michal Wilczynski S: Maintained +F: Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-sub= system.yaml =20 STARFIVE JH7110 DPHY RX DRIVER --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43D782C0270; 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Sat, 8 Nov 2025 01:04:58 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010456eusmtip2b27901863ee07c5126f2c8becf11da34~14oaCLnXI0912409124eusmtip2S; Sat, 8 Nov 2025 01:04:56 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:38 +0100 Subject: [PATCH RFC 04/13] dt-bindings: display: bridge: Add starfive,jh7110-hdmi-controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-4-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010458eucas1p11d128a6dd0aab3171db7c001e69ecfc8 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010458eucas1p11d128a6dd0aab3171db7c001e69ecfc8 X-EPHeader: CA X-CMS-RootMailID: 20251108010458eucas1p11d128a6dd0aab3171db7c001e69ecfc8 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Add the dt-binding for the StarFive JH7110 Innosilicon HDMI controller (DRM bridge). This device is the second child of the starfive,jh7110-hdmi-mfd node. It consumes register access clocks (sys, mclk, bclk) from the voutcrg and both the pixel clock (pclk) and the PHY from its hdmi_phy sibling. Signed-off-by: Michal Wilczynski --- .../starfive,jh7110-inno-hdmi-controller.yaml | 123 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 124 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/starfive,jh71= 10-inno-hdmi-controller.yaml b/Documentation/devicetree/bindings/display/br= idge/starfive,jh7110-inno-hdmi-controller.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3707c9dbff9c9fdc0ed7db4720a= 6dd8eabeeb774 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno= -hdmi-controller.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/starfive,jh7110-inno-hdm= i-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Innosilicon HDMI Controller + +maintainers: + - Michal Wilczynski + +description: + The controller portion of the StarFive JH7110 INNO HDMI IP. + +properties: + compatible: + const: starfive,jh7110-inno-hdmi-controller + + interrupts: + maxItems: 1 + + clocks: + items: + - description: System clock for register access + - description: Module clock + - description: Bus clock + - description: Pixel clock from PHY + + clock-names: + items: + - const: sys + - const: mclk + - const: bclk + - const: pclk + + resets: + maxItems: 1 + + reset-names: + const: hdmi_tx + + phys: + maxItems: 1 + + phy-names: + const: hdmi-phy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: + A graph node with one input port and one output port. + +required: + - compatible + - interrupts + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + hdmi_mfd: hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-mfd"; + reg =3D <0x29590000 0x4000>; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + clocks =3D <&xin24m>; + clock-names =3D "refoclk"; + #clock-cells =3D <0>; + clock-output-names =3D "hdmi_pclk"; + #phy-cells =3D <0>; + }; + + hdmi_controller: controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + interrupts =3D <99>; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "sys", "mclk", "bclk", "pclk"; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + reset-names =3D "hdmi_tx"; + phys =3D <&hdmi_phy>; + phy-names =3D "hdmi-phy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + port@1 { + reg =3D <1>; + hdmi_out: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index a75ba7a44ee84db6a75b91c1a0867a37db2ebcdb..66fab45bbee8c1a5f73d09bb470= d28029b8c6139 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24047,6 +24047,7 @@ F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfi= ve.c STARFIVE JH7110 DISPLAY SUBSYSTEM M: Michal Wilczynski S: Maintained +F: Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-h= dmi-controller.yaml F: Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-sub= system.yaml =20 --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48E1228C849; Sat, 8 Nov 2025 01:05:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 8 Nov 2025 01:05:00 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010458eusmtip2e955a85f1244318229a3855f31124197~14obgPqD62515425154eusmtip2Z; Sat, 8 Nov 2025 01:04:58 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:39 +0100 Subject: [PATCH RFC 05/13] dt-bindings: mfd: Add starfive,jh7110-hdmi-mfd Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-5-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010500eucas1p1c8b73311765e359bea891ec783237910 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010500eucas1p1c8b73311765e359bea891ec783237910 X-EPHeader: CA X-CMS-RootMailID: 20251108010500eucas1p1c8b73311765e359bea891ec783237910 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Add the dt-binding for the StarFive JH7110 HDMI MFD (Multi-Function Device). The JH7110 HDMI IP is a monolithic block containing both the digital controller and analog PHY in a single register space. This binding defines the MFD parent device, which holds the shared register map and populates its two children: the PHY and the controller. This is necessary to resolve a circular clock dependency between the HDMI block and the VOUT clock generator. Signed-off-by: Michal Wilczynski --- .../bindings/mfd/starfive,jh7110-hdmi-mfd.yaml | 93 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd= .yaml b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2cbfb2b975083240575a0567b06= e6cafd542cf9b --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/starfive,jh7110-hdmi-mfd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 HDMI MFD (Controller+PHY) + +maintainers: + - Michal Wilczynski + +description: + The StarFive JH7110 HDMI block is a monolithic IP containing both + the digital controller logic and the analog PHY logic in a single + register space. + +properties: + compatible: + const: starfive,jh7110-hdmi-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +patternProperties: + "^phy(@[0-9a-f]+)?$": + $ref: ../phy/starfive,jh7110-inno-hdmi-phy.yaml# + "^controller(@[0-9a-f]+)?$": + $ref: ../display/bridge/starfive,jh7110-inno-hdmi-controller.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + hdmi_mfd: hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-mfd"; + reg =3D <0x29590000 0x4000>; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + clocks =3D <&xin24m>; + clock-names =3D "refoclk"; + #clock-cells =3D <0>; + clock-output-names =3D "hdmi_pclk"; + #phy-cells =3D <0>; + }; + + hdmi_controller: controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + interrupts =3D <99>; + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "sys", "mclk", "bclk", "pclk"; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + reset-names =3D "hdmi_tx"; + phys =3D <&hdmi_phy>; + phy-names =3D "hdmi-phy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + port@1 { + reg =3D <1>; + hdmi_out: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 66fab45bbee8c1a5f73d09bb470d28029b8c6139..052876c6538f980f75ff64e78b6= ebea460307904 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24048,6 +24048,7 @@ STARFIVE JH7110 DISPLAY SUBSYSTEM M: Michal Wilczynski S: Maintained F: Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-h= dmi-controller.yaml +F: Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml F: Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-sub= system.yaml =20 --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EC952BD001; Sat, 8 Nov 2025 01:05:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 8 Nov 2025 01:05:01 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010500eusmtip298823f1a54fe88f4dc14b973462869e9~14odaK2TJ0912409124eusmtip2T; Sat, 8 Nov 2025 01:05:00 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:40 +0100 Subject: [PATCH RFC 06/13] drm: bridge: inno_hdmi: Refactor to support regmap and probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-6-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010501eucas1p1357090a298d586f1843280ac7f37178a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010501eucas1p1357090a298d586f1843280ac7f37178a X-EPHeader: CA X-CMS-RootMailID: 20251108010501eucas1p1357090a298d586f1843280ac7f37178a References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Refactor the Innosilicon HDMI bridge driver into a library to support being called by MFD (Multi-Function Device) drivers. This is necessary for platforms like the StarFive JH7110, where the HDMI controller and PHY are part of a monolithic MFD block. This patch makes the following changes: - The core probing logic is moved into a new exported function, inno_hdmi_probe(). - A corresponding exported inno_hdmi_remove() is added. - The existing inno_hdmi_bind() function is updated to use the new inno_hdmi_probe() helper. - The driver now supports retrieving a shared regmap from a parent device, falling back to ioremap if one is not found. - The struct inno_hdmi definition is moved to a public header (include/drm/bridge/inno_hdmi.h) to be accessible by other drivers. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 99 +++++++++++++++++++++++++++-------= ---- include/drm/bridge/inno_hdmi.h | 25 +++++++++- 2 files changed, 96 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index e46ee4d85044f18407aaa624b4e3dd1a6c5af5cb..9a2370ed2f208caf3dafb4a4d88= 84516d489263c 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -395,12 +395,6 @@ enum inno_hdmi_dev_type { RK3128_HDMI, }; =20 -struct inno_hdmi_phy_config { - unsigned long pixelclock; - u8 pre_emphasis; - u8 voltage_level_control; -}; - struct inno_hdmi_variant { enum inno_hdmi_dev_type dev_type; struct inno_hdmi_phy_config *phy_configs; @@ -417,19 +411,6 @@ struct inno_hdmi_i2c { struct completion cmp; }; =20 -struct inno_hdmi { - struct device *dev; - struct drm_bridge bridge; - struct clk *pclk; - struct clk *refclk; - void __iomem *regs; - struct regmap *grf; - - struct inno_hdmi_i2c *i2c; - struct i2c_adapter *ddc; - const struct inno_hdmi_plat_data *plat_data; -}; - enum { CSC_RGB_0_255_TO_ITU601_16_235_8BIT, CSC_RGB_0_255_TO_ITU709_16_235_8BIT, @@ -496,11 +477,23 @@ static int inno_hdmi_find_phy_config(struct inno_hdmi= *hdmi, =20 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) { + u32 val; + + if (hdmi->regmap) { + regmap_read(hdmi->regmap, offset * 4, &val); + return val; + } + return readl_relaxed(hdmi->regs + (offset) * 0x04); } =20 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) { + if (hdmi->regmap) { + regmap_write(hdmi->regmap, offset * 4, val); + return; + } + writel_relaxed(val, hdmi->regs + (offset) * 0x04); } =20 @@ -1082,11 +1075,24 @@ static struct i2c_adapter *inno_hdmi_i2c_adapter(st= ruct inno_hdmi *hdmi) return adap; } =20 -struct inno_hdmi *inno_hdmi_bind(struct device *dev, - struct drm_encoder *encoder, - const struct inno_hdmi_plat_data *plat_data) +/** + * inno_hdmi_probe - Internal helper to perform common setup + * @pdev: platform device + * @plat_data: SoC-specific platform data + * + * This function handles all the common hardware setup: allocating the main + * struct, mapping registers, getting clocks, initializing the hardware, + * setting up the IRQ, and initializing the DDC adapter and bridge struct. + * It returns a pointer to the inno_hdmi struct on success, or an ERR_PTR + * on failure. + * + * This function is used by modern, decoupled MFD/glue drivers. It registe= rs + * the bridge but does not attach it. + */ +struct inno_hdmi *inno_hdmi_probe(struct platform_device *pdev, + const struct inno_hdmi_plat_data *plat_data) { - struct platform_device *pdev =3D to_platform_device(dev); + struct device *dev =3D &pdev->dev; struct inno_hdmi *hdmi; int irq; int ret; @@ -1103,9 +1109,21 @@ struct inno_hdmi *inno_hdmi_bind(struct device *dev, hdmi->dev =3D dev; hdmi->plat_data =3D plat_data; =20 - hdmi->regs =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(hdmi->regs)) - return ERR_CAST(hdmi->regs); + /* + * MFD Support: Check if parent provides a regmap. + * If so, use it. Otherwise, fall back to ioremap. + */ + if (dev->parent) + hdmi->regmap =3D dev_get_regmap(dev->parent, NULL); + + if (hdmi->regmap) { + dev_info(dev, "Using MFD regmap for registers\n"); + } else { + dev_info(dev, "Falling back to ioremap for registers\n"); + hdmi->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hdmi->regs)) + return ERR_CAST(hdmi->regs); + } =20 hdmi->pclk =3D devm_clk_get_enabled(hdmi->dev, "pclk"); if (IS_ERR(hdmi->pclk)) { @@ -1149,7 +1167,34 @@ struct inno_hdmi *inno_hdmi_bind(struct device *dev, if (ret) return ERR_PTR(ret); =20 - ret =3D drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH= _NO_CONNECTOR); + return hdmi; +} +EXPORT_SYMBOL_GPL(inno_hdmi_probe); + +/** + * inno_hdmi_remove - Remove a bridge created by inno_hdmi_probe + * @hdmi: The inno_hdmi instance to remove + */ +void inno_hdmi_remove(struct inno_hdmi *hdmi) +{ + drm_bridge_remove(&hdmi->bridge); +} +EXPORT_SYMBOL_GPL(inno_hdmi_remove); + +struct inno_hdmi *inno_hdmi_bind(struct device *dev, + struct drm_encoder *encoder, + const struct inno_hdmi_plat_data *plat_data) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct inno_hdmi *hdmi; + int ret; + + hdmi =3D inno_hdmi_probe(pdev, plat_data); + if (IS_ERR(hdmi)) + return hdmi; + + ret =3D drm_bridge_attach(encoder, &hdmi->bridge, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) return ERR_PTR(ret); =20 diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h index 8b39655212e247d9ca7b1f220f970df1fb6afe13..019680622324197e046a1c606ec= 25aabe95537b4 100644 --- a/include/drm/bridge/inno_hdmi.h +++ b/include/drm/bridge/inno_hdmi.h @@ -6,10 +6,13 @@ #ifndef __INNO_HDMI__ #define __INNO_HDMI__ =20 +#include + struct device; struct drm_encoder; struct drm_display_mode; -struct inno_hdmi; +struct i2c_adapter; +struct inno_hdmi_i2c; =20 struct inno_hdmi_plat_ops { void (*enable)(struct device *pdev, struct drm_display_mode *mode); @@ -27,7 +30,27 @@ struct inno_hdmi_plat_data { struct inno_hdmi_phy_config *default_phy_config; }; =20 +struct inno_hdmi { + struct device *dev; + struct drm_bridge bridge; + struct clk *pclk; + struct clk *refclk; + void __iomem *regs; + struct regmap *regmap; + struct regmap *grf; + + struct i2c_adapter *ddc; + struct inno_hdmi_i2c *i2c; + const struct inno_hdmi_plat_data *plat_data; +}; + struct inno_hdmi *inno_hdmi_bind(struct device *pdev, struct drm_encoder *encoder, const struct inno_hdmi_plat_data *plat_data); + +struct inno_hdmi *inno_hdmi_probe(struct platform_device *pdev, + const struct inno_hdmi_plat_data *plat_data); + +void inno_hdmi_remove(struct inno_hdmi *hdmi); + #endif /* __INNO_HDMI__ */ --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ED092BD00C; Sat, 8 Nov 2025 01:05:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762563908; 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Sat, 8 Nov 2025 01:05:03 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010501eusmtip2aea0981d662f58554103fd4806fde1fb~14oe4RNVP2515425154eusmtip2b; Sat, 8 Nov 2025 01:05:01 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:41 +0100 Subject: [PATCH RFC 07/13] drm: bridge: inno_hdmi: Add .disable platform operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-7-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010503eucas1p1be26568a176a11990d8d89487531803d X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010503eucas1p1be26568a176a11990d8d89487531803d X-EPHeader: CA X-CMS-RootMailID: 20251108010503eucas1p1be26568a176a11990d8d89487531803d References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> The Innosilicon HDMI driver supports platform-specific behavior through the `inno_hdmi_plat_ops`. While it provides an `.enable` hook for platform-specific power up sequences (like enabling PHYs), it lacks a corresponding hook for power down. This patch adds a new `.disable` op to the `inno_hdmi_plat_ops` struct and calls it at the beginning of `inno_hdmi_bridge_atomic_disable()`. This allows platform specific drivers, such as the StarFive JH7110, to implement their own power down sequence (e.g., calling phy_power_off() and clk_disable_unprepare()). Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/bridge/inno-hdmi.c | 4 ++++ include/drm/bridge/inno_hdmi.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/in= no-hdmi.c index 9a2370ed2f208caf3dafb4a4d8884516d489263c..37ed7169bfce755cc5bddca16c7= 8d4f112ea33e6 100644 --- a/drivers/gpu/drm/bridge/inno-hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -887,6 +887,10 @@ static void inno_hdmi_bridge_atomic_disable(struct drm= _bridge *bridge, struct drm_atomic_state *state) { struct inno_hdmi *hdmi =3D bridge_to_inno_hdmi(bridge); + const struct inno_hdmi_plat_ops *plat_ops =3D hdmi->plat_data->ops; + + if (plat_ops && plat_ops->disable) + plat_ops->disable(hdmi->dev); =20 inno_hdmi_standby(hdmi); } diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h index 019680622324197e046a1c606ec25aabe95537b4..ca554c525fd6bf63a4a8b9721e9= 67bc473492f0a 100644 --- a/include/drm/bridge/inno_hdmi.h +++ b/include/drm/bridge/inno_hdmi.h @@ -16,6 +16,7 @@ struct inno_hdmi_i2c; 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Sat, 8 Nov 2025 01:05:03 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:42 +0100 Subject: [PATCH RFC 08/13] soc: starfive: Add jh7110-vout-subsystem driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-8-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010504eucas1p26e8ee9aa88ab75bebd832eaea81720e9 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010504eucas1p26e8ee9aa88ab75bebd832eaea81720e9 X-EPHeader: CA X-CMS-RootMailID: 20251108010504eucas1p26e8ee9aa88ab75bebd832eaea81720e9 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Add the wrapper driver for the StarFive JH7110 VOUT subsystem. This driver is responsible for managing the shared resources for all video output devices. It enables the PD_VOUT power domain, enables the top-level NoC bus clock, and deasserts the main bus reset. Once these resources are active, it calls of_platform_populate() to create and probe the child devices (DC8200, VOUTCRG, HDMI MFD) that reside within this subsystem. Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/starfive/Kconfig | 25 ++++++ drivers/soc/starfive/Makefile | 2 + drivers/soc/starfive/jh7110-vout-subsystem.c | 117 +++++++++++++++++++++++= ++++ 6 files changed, 147 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 052876c6538f980f75ff64e78b6ebea460307904..74e562a6b57ac9f776c4be2d6f0= 977c62bc03d46 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24051,6 +24051,7 @@ F: Documentation/devicetree/bindings/display/bridge= /starfive,jh7110-inno-hdmi-co F: Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml F: Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-sub= system.yaml +F: drivers/soc/starfive/jh7110-vout-subsystem.c =20 STARFIVE JH7110 DPHY RX DRIVER M: Jack Zhu diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index a2d65adffb8052c0ac5a6b60bf33fa9c644701bb..b3b01fc38139d98076c14f626a4= 2ae3b7ef7c5d6 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" source "drivers/soc/sophgo/Kconfig" +source "drivers/soc/starfive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index c9e689080ceb759384f690c2b65a82b3cb451c74..009f85ff891a15e0455f92c5d5a= 4059d8b1fcd3f 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -30,6 +30,7 @@ obj-y +=3D renesas/ obj-y +=3D rockchip/ obj-$(CONFIG_SOC_SAMSUNG) +=3D samsung/ obj-y +=3D sophgo/ +obj-y +=3D starfive/ obj-y +=3D sunxi/ obj-$(CONFIG_ARCH_TEGRA) +=3D tegra/ obj-y +=3D ti/ diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..47e82aaaa7e0af9d5c718166601= c59c1ca683d3a --- /dev/null +++ b/drivers/soc/starfive/Kconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Starfive SoC drivers +# + +if ARCH_STARFIVE || COMPILE_TEST +menu "Starfive SoC drivers" + +config SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM + tristate "StarFive JH7110 VOUT Subsystem Manager" + help + Enable this option to support the VOUT (Video Output) subsystem on + the StarFive JH7110 SoC. + + This driver acts as a parent wrapper for all display related + hardware blocks (DC8200, VOUTCRG, HDMI MFD). Its primary + responsibility is to manage the shared PD_VOUT power domain, + enabling power, clocks, and resets for the entire subsystem + before the individual child drivers are probed. + + This is essential for the display hardware to be detected and + to function correctly. + +endmenu +endif diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..17081cd67635b02f495230b117c= 9acb691ef33ba --- /dev/null +++ b/drivers/soc/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM) +=3D jh7110-vout-subsyste= m.o diff --git a/drivers/soc/starfive/jh7110-vout-subsystem.c b/drivers/soc/sta= rfive/jh7110-vout-subsystem.c new file mode 100644 index 0000000000000000000000000000000000000000..a67fd1cbac6b97c0c78c5dff444= 450579beca91d --- /dev/null +++ b/drivers/soc/starfive/jh7110-vout-subsystem.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include +#include +#include + +static void devm_clk_disable_unprepare(void *data) +{ + struct clk *clk =3D data; + + clk_disable_unprepare(clk); +} + +static void devm_reset_control_assert(void *data) +{ + struct reset_control *rst =3D data; + + reset_control_assert(rst); +} + +static int jh7110_vout_subsystem_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct clk *bus_clk; + struct reset_control *bus_rst; + int ret; + + bus_clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(bus_clk)) + return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n"); + + bus_rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(bus_rst)) + return dev_err_probe(dev, PTR_ERR(bus_rst), "Failed to get bus reset\n"); + + pm_runtime_enable(dev); + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable power domain: %d\n", ret); + pm_runtime_disable(dev); + return ret; + } + + ret =3D clk_prepare_enable(bus_clk); + if (ret) { + dev_err(dev, "Failed to enable bus clock: %d\n", ret); + goto err_pm_put; + } + + ret =3D devm_add_action_or_reset(dev, devm_clk_disable_unprepare, bus_clk= ); + if (ret) { + dev_err(dev, "Failed to register clk disable action: %d\n", ret); + goto err_pm_put; + } + + ret =3D reset_control_deassert(bus_rst); + if (ret) { + dev_err(dev, "Failed to deassert bus reset: %d\n", ret); + goto err_pm_put; + } + + ret =3D devm_add_action_or_reset(dev, devm_reset_control_assert, bus_rst); + if (ret) { + dev_err(dev, "Failed to register reset assert action: %d\n", ret); + goto err_pm_put; + } + + dev_info(dev, "VOUT subsystem bus interface is powered on\n"); + + ret =3D of_platform_populate(dev->of_node, NULL, NULL, dev); + if (ret) { + dev_err(dev, "Failed to populate child devices: %d\n", ret); + goto err_pm_put; + } + + return 0; + +err_pm_put: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + return ret; +} + +static void jh7110_vout_subsystem_remove(struct platform_device *pdev) +{ + of_platform_depopulate(&pdev->dev); + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id vout_subsystem_of_match[] =3D { + { .compatible =3D "starfive,jh7110-vout-subsystem", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vout_subsystem_of_match); + +static struct platform_driver jh7110_vout_subsystem_driver =3D { + .probe =3D jh7110_vout_subsystem_probe, + .remove =3D jh7110_vout_subsystem_remove, + .driver =3D { + .name =3D "jh7110-vout-subsystem", + .of_match_table =3D vout_subsystem_of_match, + }, +}; +module_platform_driver(jh7110_vout_subsystem_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive JH7110 VOUT Subsystem Manager"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50F982D3A9E; Sat, 8 Nov 2025 01:05:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762563911; 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Sat, 8 Nov 2025 01:05:06 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010504eusmtip212ee682d719b3e6e6c819a3c19a4a346~14oh0FAJw0912409124eusmtip2W; Sat, 8 Nov 2025 01:05:04 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:43 +0100 Subject: [PATCH RFC 09/13] soc: starfive: Add jh7110-hdmi-mfd driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-9-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010506eucas1p233e03b70f074720a659b5e3862f61905 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010506eucas1p233e03b70f074720a659b5e3862f61905 X-EPHeader: CA X-CMS-RootMailID: 20251108010506eucas1p233e03b70f074720a659b5e3862f61905 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Add the MFD parent driver for the monolithic JH7110 HDMI IP block. This driver binds to the starfive,jh7110-hdmi-mfd node. Its sole responsibility is to map the entire shared register block, create a regmap with the correct configuration, and then call devm_of_platform_populate() to create its hdmi_phy and hdmi_controller child devices. The child drivers will retrieve the shared regmap from this parent driver. Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/soc/starfive/Kconfig | 17 +++++++++ drivers/soc/starfive/Makefile | 1 + drivers/soc/starfive/jh7110-hdmi-mfd.c | 67 ++++++++++++++++++++++++++++++= ++++ 4 files changed, 86 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 74e562a6b57ac9f776c4be2d6f0977c62bc03d46..f1867018ee92fb754689934f6d2= 38f9c9f185161 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24051,6 +24051,7 @@ F: Documentation/devicetree/bindings/display/bridge= /starfive,jh7110-inno-hdmi-co F: Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml F: Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-sub= system.yaml +F: drivers/soc/starfive/jh7110-hdmi-mfd.c F: drivers/soc/starfive/jh7110-vout-subsystem.c =20 STARFIVE JH7110 DPHY RX DRIVER diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig index 47e82aaaa7e0af9d5c718166601c59c1ca683d3a..e0232988050bd250529e373243f= 5ae1851b26135 100644 --- a/drivers/soc/starfive/Kconfig +++ b/drivers/soc/starfive/Kconfig @@ -21,5 +21,22 @@ config SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM This is essential for the display hardware to be detected and to function correctly. =20 +config SOC_STARFIVE_JH7110_HDMI_MFD + tristate "StarFive JH7110 HDMI MFD Driver" + depends on OF + help + This option enables the MFD (Multi-Function Device) parent driver + for the monolithic StarFive JH7110 HDMI peripheral. + + The JH7110 HDMI IP block contains both the digital controller + (DRM bridge) and the analog PHY (clock/phy provider) logic within + a single shared register space. + + This MFD driver acts as a wrapper. Its only job is to map the + shared registers and create separate logical child devices + for the "PHY" and the "controller". This is required to + correctly manage resources and break a circular clock dependency + between the PHY and the VOUT clock generator at probe time. + endmenu endif diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile index 17081cd67635b02f495230b117c9acb691ef33ba..15a4e8ca358f2bfe3ed0d00fea9= 48edac4ccbd75 100644 --- a/drivers/soc/starfive/Makefile +++ b/drivers/soc/starfive/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM) +=3D jh7110-vout-subsyste= m.o +obj-$(CONFIG_SOC_STARFIVE_JH7110_HDMI_MFD) +=3D jh7110-hdmi-mfd.o diff --git a/drivers/soc/starfive/jh7110-hdmi-mfd.c b/drivers/soc/starfive/= jh7110-hdmi-mfd.c new file mode 100644 index 0000000000000000000000000000000000000000..73f1d58b280d3efb770c2dcf1ac= 934e7a6a51c64 --- /dev/null +++ b/drivers/soc/starfive/jh7110-hdmi-mfd.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MFD Driver for StarFive JH7110 HDMI + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * This driver binds to the monolithic HDMI block and creates separate + * logical platform devices for the HDMI Controller (bridge) and the + * HDMI PHY (clock/phy provider), allowing them to share a single regmap + * and breaking the probing circular dependency. + */ + +#include +#include +#include +#include +#include + +static const struct regmap_config starfive_hdmi_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 8, + .max_register =3D 0x4000, +}; + +static int starfive_hdmi_mfd_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + void __iomem *regs; + struct regmap *regmap; + int ret; + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + regmap =3D devm_regmap_init_mmio(dev, regs, + &starfive_hdmi_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "Failed to init shared regmap\n"); + + ret =3D devm_of_platform_populate(dev); + if (ret) + dev_err(dev, "Failed to populate child devices: %d\n", ret); + + return ret; +} + +static const struct of_device_id starfive_hdmi_mfd_of_match[] =3D { + { .compatible =3D "starfive,jh7110-hdmi-mfd", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_mfd_of_match); + +static struct platform_driver starfive_hdmi_mfd_driver =3D { + .probe =3D starfive_hdmi_mfd_probe, + .driver =3D { + .name =3D "starfive-hdmi-mfd", + .of_match_table =3D starfive_hdmi_mfd_of_match, + }, +}; +module_platform_driver(starfive_hdmi_mfd_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive JH7110 HDMI MFD Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09FAE2D7387; Sat, 8 Nov 2025 01:05:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762563912; cv=none; b=Ona9lDzz+zkw1VFFDSmrtoCBhhg6l9uiaRySde3sOSXusQZgkRNI721qSfaCbK1hkPsb5Xz8Ots82xrAxR8r2CjcSDpTsWEtl7304rV23x9ZJdNfgCF7kJULoeV+gbPHuCe1gVs7fSUD8KYTP8ZSxyNBRyGKNWHhxgqpWZqB094= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762563912; c=relaxed/simple; bh=LMniwZ26FDFefJthbZ7HeB6W0xw5Fc/w/MuIcbQ+x5Y=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1762563908; bh=/eyZIya/HIfK89auuWlHX84i/8cBpJh5L9ub7bFaqG8=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=cBUBWn8uVSJzCxa4NgR1ygGTnu5WDyC0HEYLj8v4mSTykTOhQ8I7I0CstTkcIxWkv 3Oh9ZW3bVZNK7uAEMhxhjo4JEz8yZXkVSMoxF6xRnOw1R8cYMwAfE4+weO/q5rfsEi ax3PSVUCVIW/hakc7ilTrtOnh0KYywO24WGl73XE= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20251108010507eucas1p2aa5a2604f24e4cee2c116dd35f1132d5~14okorMVd2536425364eucas1p2w; Sat, 8 Nov 2025 01:05:07 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010506eusmtip2847c7391dcf190be3df6da4bb4c52597~14ojQJ1QU0912409124eusmtip2X; Sat, 8 Nov 2025 01:05:06 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:44 +0100 Subject: [PATCH RFC 10/13] clk: starfive: voutcrg: Update the voutcrg Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-10-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010507eucas1p2aa5a2604f24e4cee2c116dd35f1132d5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010507eucas1p2aa5a2604f24e4cee2c116dd35f1132d5 X-EPHeader: CA X-CMS-RootMailID: 20251108010507eucas1p2aa5a2604f24e4cee2c116dd35f1132d5 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Update the voutcrg driver to support the new MFD HDMI model. The hdmitx0_pixelclk is now supplied by the starfive-inno-hdmi-phy driver. This patch updates the MUX definitions for dc8200_pix0 and dc8200_pix1 to add the CLK_SET_RATE_PARENT flag. This allows the dc8200 driver to set the pixel clock rate, which will be correctly propagated to the parent. Remove the pm_runtime calls, as power management is now handled by the vout-subsystem parent wrapper. Signed-off-by: Michal Wilczynski --- drivers/clk/starfive/clk-starfive-jh7110-vout.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/= starfive/clk-starfive-jh7110-vout.c index bad20d5d794a72f071b4d547b7304786a8ba9afa..6175f94ff4113088696ba1dfbe5= 080609733fb76 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c @@ -9,7 +9,6 @@ #include #include #include -#include #include =20 #include @@ -40,10 +39,10 @@ static const struct jh71x0_clk_data jh7110_voutclk_data= [] =3D { JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VO= UT_TOP_AXI), JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_= VOUT_TOP_AXI), JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VO= UT_TOP_AHB), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", CLK_SET_RATE_PAREN= T, 2, JH7110_VOUTCLK_DC8200_PIX, JH7110_VOUTCLK_HDMITX0_PIXELCLK), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", CLK_SET_RATE_PAREN= T, 2, JH7110_VOUTCLK_DC8200_PIX, JH7110_VOUTCLK_HDMITX0_PIXELCLK), /* LCD */ @@ -133,12 +132,6 @@ static int jh7110_voutcrg_probe(struct platform_device= *pdev) return dev_err_probe(priv->dev, ret, "failed to get top clocks\n"); dev_set_drvdata(priv->dev, top); =20 - /* enable power domain and clocks */ - pm_runtime_enable(priv->dev); - ret =3D pm_runtime_resume_and_get(priv->dev); - if (ret < 0) - return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); - ret =3D jh7110_vout_top_rst_init(priv); if (ret) goto err_exit; @@ -194,17 +187,9 @@ static int jh7110_voutcrg_probe(struct platform_device= *pdev) return 0; =20 err_exit: - pm_runtime_put_sync(priv->dev); - pm_runtime_disable(priv->dev); return ret; } =20 -static void jh7110_voutcrg_remove(struct platform_device *pdev) -{ - pm_runtime_put_sync(&pdev->dev); - pm_runtime_disable(&pdev->dev); -} - static const struct of_device_id jh7110_voutcrg_match[] =3D { { .compatible =3D "starfive,jh7110-voutcrg" }, { /* sentinel */ } @@ -213,7 +198,6 @@ MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match); =20 static struct platform_driver jh7110_voutcrg_driver =3D { .probe =3D jh7110_voutcrg_probe, - .remove =3D jh7110_voutcrg_remove, .driver =3D { .name =3D "clk-starfive-jh7110-vout", .of_match_table =3D jh7110_voutcrg_match, --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 521302BD02A; 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Sat, 8 Nov 2025 01:05:09 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010507eusmtip2838c4b5c39cde625fda213dbbe3397b9~14oks0YLk2515425154eusmtip2g; Sat, 8 Nov 2025 01:05:07 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:45 +0100 Subject: [PATCH RFC 11/13] drm: bridge: starfive: Add hdmi-controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-11-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010509eucas1p1cabce45ee13f19249da4898088088146 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010509eucas1p1cabce45ee13f19249da4898088088146 X-EPHeader: CA X-CMS-RootMailID: 20251108010509eucas1p1cabce45ee13f19249da4898088088146 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Add the HDMI controller (bridge) driver for the StarFive JH7110. This driver binds to the starfive,jh7110-inno-hdmi-controller MFD child. It gets its shared regmap from the MFD parent and its clocks (sys, mclk, bclk) from voutcrg. It consumes the pclk (pixel clock) and PHY from its hdmi_phy sibling. The driver calls the generic inno_hdmi_probe function and passes the shared regmap to it, registering as a DRM bridge. The .enable hook is responsible for setting the PHY's pixel clock rate via clk_set_rate() and powering on the PHY via phy_power_on(). Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/gpu/drm/bridge/Kconfig | 11 ++ drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/jh7110-inno-hdmi.c | 190 ++++++++++++++++++++++++++= ++++ 4 files changed, 203 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f1867018ee92fb754689934f6d238f9c9f185161..5984b83e55aeadb59c25a6e8f01= 057fb9d982d81 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24053,6 +24053,7 @@ F: Documentation/devicetree/bindings/phy/starfive,j= h7110-inno-hdmi-phy.yaml F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-sub= system.yaml F: drivers/soc/starfive/jh7110-hdmi-mfd.c F: drivers/soc/starfive/jh7110-vout-subsystem.c +F: drivers/gpu/drm/bridge/jh7110-inno-hdmi.c =20 STARFIVE JH7110 DPHY RX DRIVER M: Jack Zhu diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index a5b8df9655ba70c6d653183780089258946b0e5a..2bf97ec0096ed093ed078b48300= d9aa12088c486 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -323,6 +323,17 @@ config DRM_SIMPLE_BRIDGE Support for non-programmable DRM bridges, such as ADI ADV7123, TI THS8134 and THS8135 or passive resistor ladder DACs. =20 +config DRM_STARFIVE_JH7110_INNO_HDMI + tristate "Starfive JH7110 Innosilicon HDMI bridge" + depends on OF + depends on ARCH_STARFIVE || COMPILE_TEST + select DRM_INNO_HDMI + help + Enable support for the StarFive JH7110 specific implementation + of the Innosilicon HDMI controller. + This driver acts as a glue layer between the JH7110 HDMI MFD + parent driver and the generic Innosilicon HDMI bridge driver. + config DRM_THINE_THC63LVD1024 tristate "Thine THC63LVD1024 LVDS decoder bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makef= ile index 4bc2236c8ae9169ac998e9d0448badff457cabaa..b2f5835ec05bcbb4367499d1ceb= b5403d7b9f247 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) +=3D sil-sii8620.o obj-$(CONFIG_DRM_SII902X) +=3D sii902x.o obj-$(CONFIG_DRM_SII9234) +=3D sii9234.o obj-$(CONFIG_DRM_SIMPLE_BRIDGE) +=3D simple-bridge.o +obj-$(CONFIG_DRM_STARFIVE_JH7110_INNO_HDMI) +=3D jh7110-inno-hdmi.o obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) +=3D th1520-dw-hdmi.o obj-$(CONFIG_DRM_THINE_THC63LVD1024) +=3D thc63lvd1024.o obj-$(CONFIG_DRM_TOSHIBA_TC358762) +=3D tc358762.o diff --git a/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c b/drivers/gpu/drm/br= idge/jh7110-inno-hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..8d3e1c3e736b801882b1b057199= fc341142bba52 --- /dev/null +++ b/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) StarFive Technology Co., Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * HDMI Controller (bridge) driver for StarFive JH7110 MFD. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +enum stf_hdmi_ctrl_clocks { CLK_SYS =3D 0, CLK_M, CLK_B, CLK_PCLK, CLK_CTR= L_NUM }; + +struct stf_inno_hdmi_controller { + struct inno_hdmi *inno; + struct device *dev; + struct clk_bulk_data clks[CLK_CTRL_NUM]; + struct reset_control *tx_rst; + struct phy *phy; +}; + +static void inno_hdmi_starfive_enable(struct device *dev, + struct drm_display_mode *mode) +{ + struct stf_inno_hdmi_controller *ctrl =3D dev_get_drvdata(dev); + int ret; + + /* + * 1. Set the pixel clock rate. This calls the PHY driver's .set_rate op. + */ + ret =3D clk_set_rate(ctrl->clks[CLK_PCLK].clk, mode->clock * 1000); + if (ret) { + dev_err(dev, "Failed to set pclk rate %d: %d\n", + mode->clock * 1000, ret); + return; + } + + /* + * 2. Enable the pixel clock. This calls the PHY driver's .prepare op. + */ + ret =3D clk_prepare_enable(ctrl->clks[CLK_PCLK].clk); + if (ret) { + dev_err(dev, "Failed to enable pclk: %d\n", ret); + return; + } + + /* + * 3. Power on the PHY. This calls the PHY driver's .power_on op, + * which configures the Post-PLL and analog blocks. + */ + ret =3D phy_power_on(ctrl->phy); + if (ret) { + dev_err(dev, "Failed to power on PHY: %d\n", ret); + clk_disable_unprepare(ctrl->clks[CLK_PCLK].clk); + return; + } +} + +static void inno_hdmi_starfive_disable(struct device *dev) +{ + struct stf_inno_hdmi_controller *ctrl =3D dev_get_drvdata(dev); + + phy_power_off(ctrl->phy); + clk_disable_unprepare(ctrl->clks[CLK_PCLK].clk); +} + +static int starfive_inno_hdmi_controller_probe(struct platform_device *pde= v) +{ + struct device *dev =3D &pdev->dev; + struct device *parent =3D dev->parent; + struct stf_inno_hdmi_controller *ctrl; + const struct inno_hdmi_plat_data *plat_data; + struct regmap *mfd_regmap; + int ret; + + ctrl =3D devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->dev =3D dev; + platform_set_drvdata(pdev, ctrl); + + /* Get the shared regmap from the MFD parent */ + mfd_regmap =3D dev_get_regmap(parent, NULL); + if (!mfd_regmap) { + dev_err(dev, "Failed to get parent regmap\n"); + return -ENODEV; + } + + ctrl->phy =3D devm_phy_get(dev, "hdmi-phy"); + if (IS_ERR(ctrl->phy)) + return dev_err_probe(dev, PTR_ERR(ctrl->phy), "Failed to get PHY\n"); + + ctrl->tx_rst =3D devm_reset_control_get_exclusive(dev, "hdmi_tx"); + if (IS_ERR(ctrl->tx_rst)) + return dev_err_probe(dev, PTR_ERR(ctrl->tx_rst), "failed to get tx reset= \n"); + + /* Populate the clock names this controller *consumes* */ + ctrl->clks[CLK_SYS].id =3D "sys"; + ctrl->clks[CLK_M].id =3D "mclk"; + ctrl->clks[CLK_B].id =3D "bclk"; + ctrl->clks[CLK_PCLK].id =3D "pclk"; /* Pixel clock *from* PHY */ + + ret =3D devm_clk_bulk_get(dev, CLK_CTRL_NUM, ctrl->clks); + if (ret) + return dev_err_probe(dev, ret, "Unable to get controller clocks\n"); + + /* pclk is enabled on demand during modeset */ + ret =3D clk_bulk_prepare_enable(CLK_CTRL_NUM - 1, ctrl->clks); + if (ret) + return ret; + + ret =3D reset_control_deassert(ctrl->tx_rst); + if (ret) { + clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks); + return ret; + } + + plat_data =3D of_device_get_match_data(dev); + + /* Hand off to the generic library to create the bridge. */ + ctrl->inno =3D inno_hdmi_probe(pdev, plat_data); + if (IS_ERR(ctrl->inno)) { + reset_control_assert(ctrl->tx_rst); + clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks); + return PTR_ERR(ctrl->inno); + } + + return 0; +} + +static void starfive_inno_hdmi_controller_remove(struct platform_device *p= dev) +{ + struct stf_inno_hdmi_controller *ctrl =3D platform_get_drvdata(pdev); + + inno_hdmi_remove(ctrl->inno); + + reset_control_assert(ctrl->tx_rst); + clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks); +} + +/* + * This table is now only used for the generic .mode_valid check. + * The real validation happens in the PHY driver's .round_rate. + */ +static struct inno_hdmi_phy_config stf_hdmi_phy_configs[] =3D { + { 297000000, 0x00, 0x00 }, + { ~0UL, 0x00, 0x00 }, /* Sentinel */ +}; + +static const struct inno_hdmi_plat_ops stf_inno_hdmi_plat_ops =3D { + .enable =3D inno_hdmi_starfive_enable, + .disable =3D inno_hdmi_starfive_disable, +}; + +static const struct inno_hdmi_plat_data stf_inno_hdmi_plat_data =3D { + .ops =3D &stf_inno_hdmi_plat_ops, + .phy_configs =3D stf_hdmi_phy_configs, + .default_phy_config =3D &stf_hdmi_phy_configs[0], +}; + +static const struct of_device_id starfive_hdmi_controller_dt_ids[] =3D { + { .compatible =3D "starfive,jh7110-inno-hdmi-controller", + .data =3D &stf_inno_hdmi_plat_data }, + {} +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_controller_dt_ids); + +struct platform_driver starfive_inno_hdmi_controller_driver =3D { + .probe =3D starfive_inno_hdmi_controller_probe, + .remove =3D starfive_inno_hdmi_controller_remove, + .driver =3D { + .name =3D "starfive-inno-hdmi-controller", + .of_match_table =3D starfive_hdmi_controller_dt_ids, + }, +}; +module_platform_driver(starfive_inno_hdmi_controller_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("StarFive INNO HDMI Controller Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Feb 9 00:34:53 2026 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 300292DF706; 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Sat, 8 Nov 2025 01:05:11 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251108010509eusmtip2fe40cdbb26fa70dff36437c66568c1ab~14omMBOQG0912409124eusmtip2b; Sat, 8 Nov 2025 01:05:09 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:46 +0100 Subject: [PATCH RFC 12/13] phy: starfive: Add jh7110-inno-hdmi-phy driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-12-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010511eucas1p19bca04c74545fd6019de671cbf0413f5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010511eucas1p19bca04c74545fd6019de671cbf0413f5 X-EPHeader: CA X-CMS-RootMailID: 20251108010511eucas1p19bca04c74545fd6019de671cbf0413f5 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> [WARNING: This is mostly a duplicate of Rockchip RK3328 PHY driver, I would like properly refactor common parts, maybe to some inno-phy library, not 100% sure how this would look like so would happy to take advice] Add the HDMI PHY driver for the StarFive JH7110. This driver binds to the starfive,jh7110-inno-hdmi-phy MFD child and gets its regmap from the parent. It has no dependencies on voutcrg, only on its refoclk (xin24m), which breaks the probe-time circular dependency. This driver provides two main functions: - Clock Provider: It registers clk_ops to provide the variable pixel clock (hdmi_pclk). The .set_rate operation configures the Pre-PLL registers (0x1a0+) based on the requested rate. - PHY Provider: It registers phy_ops for the controller. The .power_on op configures and enables the Post-PLL and other analog blocks (BIAS, LDO, Serializer, etc.). The register level logic is based on the Rockchip RK3328 PHY driver, as they share the same Innosilicon IP, but is adapted for the JH7110's 0x100 register offset. Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/phy/starfive/Kconfig | 19 + drivers/phy/starfive/Makefile | 1 + drivers/phy/starfive/phy-jh7110-inno-hdmi.c | 762 ++++++++++++++++++++++++= ++++ 4 files changed, 783 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5984b83e55aeadb59c25a6e8f01057fb9d982d81..765b155574b2a0649f2df6b89a1= 7eaf111d912bf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24054,6 +24054,7 @@ F: Documentation/devicetree/bindings/soc/starfive/s= tarfive,jh7110-vout-subsystem F: drivers/soc/starfive/jh7110-hdmi-mfd.c F: drivers/soc/starfive/jh7110-vout-subsystem.c F: drivers/gpu/drm/bridge/jh7110-inno-hdmi.c +F: drivers/phy/starfive/phy-jh7110-inno-hdmi.c =20 STARFIVE JH7110 DPHY RX DRIVER M: Jack Zhu diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig index d0cdd7cb4a13de22ff643c89a79d99cce57284d7..9f0c330c1dd52f38a51ff9e2113= 40ecdf091fce1 100644 --- a/drivers/phy/starfive/Kconfig +++ b/drivers/phy/starfive/Kconfig @@ -25,6 +25,25 @@ config PHY_STARFIVE_JH7110_DPHY_TX system. If M is selected, the module will be called phy-jh7110-dphy-tx.ko. =20 +config PHY_STARFIVE_JH7110_INNO_HDMI + tristate "Starfive JH7110 INNO HDMI PHY" + depends on COMMON_CLK + select GENERIC_PHY + help + This option enables the driver for the analog HDMI PHY (Physical + Layer) on the StarFive JH7110 SoC. + + This driver binds to a child node of the 'starfive,jh7110-hdmi-mfd' + parent driver and gets its register map from that parent. + + It is responsible for two main functions: + 1. PHY Provider: It provides standard PHY operations (.power_on, + .power_off) for the HDMI controller (bridge) driver. This + involves configuring the Post-PLL and analog TMDS blocks. + 2. Clock Provider: It registers as a clock provider to supply the + variable pixel clock (hdmi_pclk) to the HDMI controller and + the VOUT subsystem, which it generates using the Pre-PLL. + config PHY_STARFIVE_JH7110_PCIE tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support" depends on HAS_IOMEM diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile index eedc4a6fec156320c99ac0a0da609083b6a6a695..e7b13f00880b500f933f21b6037= 384d5c6884e3e 100644 --- a/drivers/phy/starfive/Makefile +++ b/drivers/phy/starfive/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) +=3D phy-jh7110-dphy-rx.o obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_TX) +=3D phy-jh7110-dphy-tx.o +obj-$(CONFIG_PHY_STARFIVE_JH7110_INNO_HDMI) +=3D phy-jh7110-inno-hdmi.o obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) +=3D phy-jh7110-pcie.o obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) +=3D phy-jh7110-usb.o diff --git a/drivers/phy/starfive/phy-jh7110-inno-hdmi.c b/drivers/phy/star= five/phy-jh7110-inno-hdmi.c new file mode 100644 index 0000000000000000000000000000000000000000..a74893cbcfad245ec325b1e399b= d8ded829376fa --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-inno-hdmi.c @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * This driver handles the PHY portion of the StarFive Innosilicon HDMI IP, + * which is part of a monolithic MFD block. It provides the variable pixel + * clock (from the Pre-PLL) and the PHY operations (for the Post-PLL/analo= g). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) + +/* + * StarFive (JH7110) Innosilicon HDMI PHY Register Definitions + */ + +/* REG: 0x1a0 */ +#define STF_INNO_PRE_PLL_CONTROL 0x1a0 +#define STF_INNO_PRE_PLL_POWER_DOWN BIT(0) +#define STF_INNO_PCLK_VCO_DIV_5_MASK BIT(1) +#define STF_INNO_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1) + +/* REG: 0x1a1 */ +#define STF_INNO_PRE_PLL_DIV_1 0x1a1 +#define STF_INNO_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0) +#define STF_INNO_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0) + +/* REG: 0x1a2 */ +#define STF_INNO_PRE_PLL_DIV_2 0x1a2 +#define STF_INNO_SPREAD_SPECTRUM_MOD_DOWN BIT(7) +#define STF_INNO_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) +#define STF_INNO_PRE_PLL_FRAC_DIV_DISABLE FIELD_PREP(GENMASK(5, 4), 3) +#define STF_INNO_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define STF_INNO_PRE_PLL_FB_DIV_11_8(x) FIELD_PREP(STF_INNO_PRE_PLL_FB_DIV= _11_8_MASK, (x) >> 8) + +/* REG: 0x1a3 */ +#define STF_INNO_PRE_PLL_DIV_3 0x1a3 +#define STF_INNO_PRE_PLL_FB_DIV_7_0(x) FIELD_PREP(GENMASK(7, 0), x) + +/* REG: 0x1a4 -- TMDSCLK Divs, needed by set_rate */ +#define STF_INNO_PRE_PLL_TMDSCLK_DIV 0x1a4 +#define STF_INNO_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0) +#define STF_INNO_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0) +#define STF_INNO_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2) +#define STF_INNO_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2) +#define STF_INNO_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4) +#define STF_INNO_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4) + +/* REG: 0x1a5 */ +#define STF_INNO_PCLK_DIV_AB_REG 0x1a5 +#define STF_INNO_PCLK_DIV_B_SHIFT 5 +#define STF_INNO_PCLK_DIV_B_MASK GENMASK(6, 5) +#define STF_INNO_PCLK_DIV_B(x) UPDATE(x, 6, 5) +#define STF_INNO_PCLK_DIV_A_MASK GENMASK(4, 0) +#define STF_INNO_PCLK_DIV_A(x) UPDATE(x, 4, 0) + +/* REG: 0x1a6 */ +#define STF_INNO_PCLK_DIV_CD_REG 0x1a6 +#define STF_INNO_PCLK_DIV_C_SHIFT 5 +#define STF_INNO_PCLK_DIV_C_MASK GENMASK(6, 5) +#define STF_INNO_PCLK_DIV_C(x) UPDATE(x, 6, 5) +#define STF_INNO_PCLK_DIV_D_MASK GENMASK(4, 0) +#define STF_INNO_PCLK_DIV_D(x) UPDATE(x, 4, 0) + +/* REG: 0x1a9 */ +#define STF_INNO_PRE_PLL_LOCK_STATUS 0x1a9 +#define STF_INNO_PRE_PLL_LOCK BIT(0) + +/* REG: 0x1aa */ +#define STF_INNO_POST_PLL_DIV_1 0x1aa +#define STF_INNO_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2) +#define STF_INNO_POST_PLL_REFCLK_SEL_TMDS BIT(1) +#define STF_INNO_POST_PLL_POWER_DOWN BIT(0) + +/* REG: 0x1ab */ +#define STF_INNO_POST_PLL_DIV_2 0x1ab +#define STF_INNO_POST_PLL_PRE_DIV(x) FIELD_PREP(GENMASK(5, 0), x) +#define STF_INNO_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7) + +/* REG: 0x1ac */ +#define STF_INNO_POST_PLL_DIV_3 0x1ac +#define STF_INNO_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) + +/* REG: 0x1ad */ +#define STF_INNO_POST_PLL_DIV_4 0x1ad +#define STF_INNO_POST_PLL_POST_DIV_MASK GENMASK(1, 0) + +/* REG: 0x1af */ +#define STF_INNO_POST_PLL_LOCK_STATUS 0x1af +#define STF_INNO_POST_PLL_LOCK BIT(0) + +/* REG: 0x1b0 */ +#define STF_INNO_BIAS_CONTROL 0x1b0 +#define STF_INNO_BIAS_ENABLE BIT(2) + +/* REG: 0x1b2 */ +#define STF_INNO_TMDS_CONTROL 0x1b2 +#define STF_INNO_TMDS_CLK_DRIVER_EN BIT(3) +#define STF_INNO_TMDS_D2_DRIVER_EN BIT(2) +#define STF_INNO_TMDS_D1_DRIVER_EN BIT(1) +#define STF_INNO_TMDS_D0_DRIVER_EN BIT(0) +#define STF_INNO_TMDS_DRIVER_ENABLE (STF_INNO_TMDS_CLK_DRIVER_EN | \ + STF_INNO_TMDS_D2_DRIVER_EN | \ + STF_INNO_TMDS_D1_DRIVER_EN | \ + STF_INNO_TMDS_D0_DRIVER_EN) + +/* REG: 0x1b4 */ +#define STF_INNO_LDO_CONTROL 0x1b4 +#define STF_INNO_LDO_ENABLE (BIT(2) | BIT(1) | BIT(0)) + +/* REG: 0x1be */ +#define STF_INNO_SERIALIER_CONTROL 0x1be +#define STF_INNO_SERIALIER_ENABLE (BIT(6) | BIT(5) | BIT(4) | BIT(0)) + +/* REG: 0x1cc */ +#define STF_INNO_RX_CONTROL 0x1cc +#define STF_INNO_RX_ENABLE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +/* REG: 0x1d1 */ +#define STF_INNO_PRE_PLL_FRAC_DIV_H 0x1d1 +#define STF_INNO_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0) +/* REG: 0x1d2 */ +#define STF_INNO_PRE_PLL_FRAC_DIV_M 0x1d2 +#define STF_INNO_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0) +/* REG: 0x1d3 */ +#define STF_INNO_PRE_PLL_FRAC_DIV_L 0x1d3 +#define STF_INNO_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0) + +/* + * These tables are copied from the monolithic driver. + * They match the Rockchip PHY driver tables. + */ +struct pre_pll_config { + unsigned long pixclock; + unsigned long tmdsclock; + u8 prediv; + u16 fbdiv; + u8 tmds_div_a; + u8 tmds_div_b; + u8 tmds_div_c; + u8 pclk_div_a; + u8 pclk_div_b; + u8 pclk_div_c; + u8 pclk_div_d; + u8 vco_div_5_en; + u32 fracdiv; +}; + +struct post_pll_config { + unsigned long tmdsclock; + u8 prediv; + u16 fbdiv; + u8 postdiv; + u8 post_div_en; + u8 version; +}; + +static const struct pre_pll_config pre_pll_cfg_table[] =3D { + { 25175000, 25175000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0xF55555 }, + { 25200000, 25200000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0 }, + { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0 }, + { 27027000, 27027000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0x170A3D }, + { 28320000, 28320000, 1, 28, 2, 1, 1, 3, 0, 3, 4, 0, 0x51EB85 }, + { 30240000, 30240000, 1, 30, 2, 1, 1, 3, 0, 3, 4, 0, 0x3D70A3 }, + { 31500000, 31500000, 1, 31, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 33750000, 33750000, 1, 33, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 36000000, 36000000, 1, 36, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0 }, + { 46970000, 46970000, 1, 46, 2, 1, 1, 3, 0, 3, 4, 0, 0xF851EB }, + { 49500000, 49500000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 49000000, 49000000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 50000000, 50000000, 1, 50, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 54000000, 54000000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 54054000, 54054000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0x0DD2F1 }, + { 57284000, 57284000, 1, 57, 2, 1, 1, 3, 0, 3, 4, 0, 0x48B439 }, + { 58230000, 58230000, 1, 58, 2, 1, 1, 3, 0, 3, 4, 0, 0x3AE147 }, + { 59341000, 59341000, 1, 59, 2, 1, 1, 3, 0, 3, 4, 0, 0x574BC6 }, + { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0 }, + { 65000000, 65000000, 1, 130, 2, 2, 2, 12, 0, 2, 2, 0, 0 }, + { 68250000, 68250000, 1, 68, 2, 1, 1, 3, 0, 3, 4, 0, 0x3FFFFF }, + { 71000000, 71000000, 1, 71, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B }, + { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0 }, + { 75000000, 75000000, 1, 75, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 78750000, 78750000, 1, 78, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 79500000, 79500000, 1, 79, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0 }, + { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000 }, + { 85500000, 85500000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 85750000, 85750000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 85800000, 85800000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xCCCCCC }, + { 88750000, 88750000, 1, 88, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 89910000, 89910000, 1, 89, 2, 1, 1, 3, 0, 3, 4, 0, 0xE8F5C1 }, + { 90000000, 90000000, 1, 90, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 101000000, 101000000, 1, 101, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 102250000, 102250000, 1, 102, 2, 1, 1, 3, 0, 3, 4, 0, 0x3FFFFF }, + { 106500000, 106500000, 1, 106, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 108000000, 108000000, 1, 90, 3, 0, 0, 5, 0, 2, 2, 0, 0 }, + { 119000000, 119000000, 1, 119, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 131481000, 131481000, 1, 131, 2, 1, 1, 3, 0, 3, 4, 0, 0x7B22D1 }, + { 135000000, 135000000, 1, 135, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 136750000, 136750000, 1, 136, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 147180000, 147180000, 1, 147, 2, 1, 1, 3, 0, 3, 4, 0, 0x2E147A }, + { 148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B }, + { 148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0 }, + { 154000000, 154000000, 1, 154, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 156000000, 156000000, 1, 156, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 157000000, 157000000, 1, 157, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 162000000, 162000000, 1, 162, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 174250000, 174250000, 1, 145, 3, 0, 0, 5, 0, 2, 2, 0, 0x355555 }, + { 174500000, 174500000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 174570000, 174570000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x91EB84 }, + { 175500000, 175500000, 1, 175, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 185590000, 185590000, 1, 185, 2, 1, 1, 3, 0, 3, 4, 0, 0x970A3C }, + { 187000000, 187000000, 1, 187, 2, 1, 1, 3, 0, 3, 4, 0, 0 }, + { 241500000, 241500000, 1, 161, 1, 1, 1, 4, 0, 2, 2, 0, 0 }, + { 241700000, 241700000, 1, 241, 2, 1, 1, 3, 0, 3, 4, 0, 0xB33332 }, + { 262750000, 262750000, 1, 262, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF }, + { 296500000, 296500000, 1, 296, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF }, + { 296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B }, + { 297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0 }, + { 594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; + +static const struct post_pll_config post_pll_cfg_table[] =3D { + { 25200000, 1, 80, 13, 3, 1 }, + { 27000000, 1, 40, 11, 3, 1 }, + { 27027000, 1, 40, 11, 3, 1 }, + { 33750000, 1, 40, 11, 3, 1 }, + { 49000000, 1, 20, 1, 3, 3 }, + { 65000000, 1, 20, 1, 3, 3 }, + { 74250000, 1, 20, 1, 3, 3 }, + { 88750000, 1, 20, 1, 3, 3 }, + { 108000000, 1, 20, 1, 3, 3 }, + { 148500000, 1, 20, 1, 3, 3 }, + { 162000000, 1, 20, 1, 3, 3 }, + { 174250000, 1, 20, 1, 3, 3 }, + { 187000000, 1, 20, 1, 3, 3 }, + { 241700000, 1, 20, 1, 3, 3 }, + { 297000000, 4, 20, 0, 0, 3 }, + { 594000000, 4, 20, 0, 0, 0 }, /* postpll_postdiv_en =3D 0 */ + { /* sentinel */ } +}; + +struct starfive_hdmi_phy { + struct device *dev; + struct regmap *regmap; + struct phy *phy; + struct clk *refoclk; + + struct clk_hw hw; + struct clk *phyclk; + unsigned long pixclock; + unsigned long tmdsclock; + + const struct pre_pll_config *pre_cfg; + const struct post_pll_config *post_cfg; +}; + +static inline void inno_write(struct starfive_hdmi_phy *inno, u32 reg, u8 = val) +{ + regmap_write(inno->regmap, reg * 4, val); +} + +static inline u8 inno_read(struct starfive_hdmi_phy *inno, u32 reg) +{ + u32 val; + + regmap_read(inno->regmap, reg * 4, &val); + return val; +} + +static inline void inno_update_bits(struct starfive_hdmi_phy *inno, u16 re= g, + u8 mask, u8 val) +{ + regmap_update_bits(inno->regmap, reg * 4, mask, val); +} + +#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ + regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \ + sleep_us, timeout_us) + +static const +struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct starfive_hdmi_= phy *inno, + unsigned long rate) +{ + const struct pre_pll_config *cfg =3D pre_pll_cfg_table; + + /* Round rate to nearest 1000Hz for matching */ + rate =3D DIV_ROUND_CLOSEST(rate, 1000) * 1000; + + for (; cfg->pixclock !=3D 0; cfg++) + if (cfg->pixclock =3D=3D rate) + break; + + if (cfg->pixclock =3D=3D 0) + return ERR_PTR(-EINVAL); + + return cfg; +} + +static inline struct starfive_hdmi_phy *to_starfive_hdmi_phy(struct clk_hw= *hw) +{ + return container_of(hw, struct starfive_hdmi_phy, hw); +} + +static int starfive_hdmi_phy_clk_prepare(struct clk_hw *hw) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + u32 val; + int ret; + + /* Ensure Pre-PLL is powered up */ + inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL, + STF_INNO_PRE_PLL_POWER_DOWN, 0); + + /* Wait for Pre-PLL lock if not already locked */ + val =3D inno_read(inno, STF_INNO_PRE_PLL_LOCK_STATUS); + if (val & STF_INNO_PRE_PLL_LOCK_STATUS) + return 0; /* Already locked */ + + ret =3D inno_poll(inno, STF_INNO_PRE_PLL_LOCK_STATUS, val, + val & STF_INNO_PRE_PLL_LOCK_STATUS, 1000, 100000); + if (ret < 0) { + dev_err(inno->dev, "Timeout waiting for pre-PLL lock\n"); + inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL, + STF_INNO_PRE_PLL_POWER_DOWN, + STF_INNO_PRE_PLL_POWER_DOWN); + return ret; + } + return 0; +} + +static void starfive_hdmi_phy_clk_unprepare(struct clk_hw *hw) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + + /* Power down Pre-PLL */ + inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL, + STF_INNO_PRE_PLL_POWER_DOWN, + STF_INNO_PRE_PLL_POWER_DOWN); + inno->pixclock =3D 0; /* Invalidate cached rate */ +} + +static int starfive_hdmi_phy_clk_is_prepared(struct clk_hw *hw) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + u8 status; + + status =3D inno_read(inno, STF_INNO_PRE_PLL_CONTROL); + if (status & STF_INNO_PRE_PLL_POWER_DOWN) + return 0; + + return !!(inno_read(inno, STF_INNO_PRE_PLL_LOCK_STATUS) & + STF_INNO_PRE_PLL_LOCK_STATUS); +} + +static unsigned long starfive_hdmi_phy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + unsigned long frac; + u8 nd, no_a, no_b, no_d; + u64 vco; + u16 nf; + + if (!starfive_hdmi_phy_clk_is_prepared(hw)) + return inno->pixclock; + + nd =3D inno_read(inno, STF_INNO_PRE_PLL_DIV_1) & STF_INNO_PRE_PLL_PRE_DIV= _MASK; + nf =3D ((inno_read(inno, STF_INNO_PRE_PLL_DIV_2) & STF_INNO_PRE_PLL_FB_DI= V_11_8_MASK) << 8); + nf |=3D inno_read(inno, STF_INNO_PRE_PLL_DIV_3); + vco =3D parent_rate * nf; + + if (!(inno_read(inno, STF_INNO_PRE_PLL_DIV_2) & STF_INNO_PRE_PLL_FRAC_DIV= _DISABLE)) { + frac =3D inno_read(inno, STF_INNO_PRE_PLL_FRAC_DIV_L) | + (inno_read(inno, STF_INNO_PRE_PLL_FRAC_DIV_M) << 8) | + (inno_read(inno, STF_INNO_PRE_PLL_FRAC_DIV_H) << 16); + vco +=3D DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); + } + + if (inno_read(inno, STF_INNO_PRE_PLL_CONTROL) & STF_INNO_PCLK_VCO_DIV_5_M= ASK) { + do_div(vco, nd * 5); + } else { + no_a =3D inno_read(inno, STF_INNO_PCLK_DIV_AB_REG) & STF_INNO_PCLK_DIV_A= _MASK; + no_b =3D inno_read(inno, STF_INNO_PCLK_DIV_AB_REG) & STF_INNO_PCLK_DIV_B= _MASK; + no_b >>=3D STF_INNO_PCLK_DIV_B_SHIFT; + no_b +=3D 2; + no_d =3D inno_read(inno, STF_INNO_PCLK_DIV_CD_REG) & STF_INNO_PCLK_DIV_D= _MASK; + + do_div(vco, (nd * (no_a =3D=3D 1 ? no_b : no_a) * no_d * 2)); + } + + inno->pixclock =3D DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; + + dev_dbg(inno->dev, "%s rate %lu vco %llu\n", + __func__, inno->pixclock, vco); + + return inno->pixclock; +} + +static long starfive_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned l= ong rate, + unsigned long *parent_rate) +{ + const struct pre_pll_config *cfg =3D pre_pll_cfg_table; + + rate =3D (rate / 1000) * 1000; + + for (; cfg->pixclock !=3D 0; cfg++) + if (cfg->pixclock =3D=3D rate) + break; + + if (cfg->pixclock =3D=3D 0) + return -EINVAL; + + return cfg->pixclock; +} + +static int starfive_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long= rate, + unsigned long parent_rate) +{ + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); + const struct pre_pll_config *cfg; + unsigned long tmdsclock; + u32 val; + + /* + * Find the config entry for the requested pixclock (rate). + * This cfg entry also contains the required tmdsclock. + */ + cfg =3D inno_hdmi_phy_get_pre_pll_cfg(inno, rate); + if (IS_ERR(cfg)) + return PTR_ERR(cfg); + + tmdsclock =3D cfg->tmdsclock; + + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", + __func__, rate, tmdsclock); + + if (inno->pixclock =3D=3D rate && inno->tmdsclock =3D=3D tmdsclock) + return 0; + + inno->pre_cfg =3D cfg; + + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, + STF_INNO_BIAS_ENABLE, STF_INNO_BIAS_ENABLE); + inno_write(inno, STF_INNO_RX_CONTROL, STF_INNO_RX_ENABLE); + + /* Power down Pre-PLL before re-configuring */ + inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL, + STF_INNO_PRE_PLL_POWER_DOWN, + STF_INNO_PRE_PLL_POWER_DOWN); + + /* Configure pre-pll */ + inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL, + STF_INNO_PCLK_VCO_DIV_5_MASK, + STF_INNO_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); + inno_write(inno, STF_INNO_PRE_PLL_DIV_1, + STF_INNO_PRE_PLL_PRE_DIV(cfg->prediv)); + + val =3D STF_INNO_SPREAD_SPECTRUM_MOD_DISABLE; + if (!cfg->fracdiv) + val |=3D STF_INNO_PRE_PLL_FRAC_DIV_DISABLE; + + inno_write(inno, STF_INNO_PRE_PLL_DIV_2, + STF_INNO_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); + inno_write(inno, STF_INNO_PRE_PLL_DIV_3, + STF_INNO_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); + + /* Write PCLK dividers */ + inno_write(inno, STF_INNO_PCLK_DIV_AB_REG, + STF_INNO_PCLK_DIV_A(cfg->pclk_div_a) | + STF_INNO_PCLK_DIV_B(cfg->pclk_div_b)); + inno_write(inno, STF_INNO_PCLK_DIV_CD_REG, + STF_INNO_PCLK_DIV_C(cfg->pclk_div_c) | + STF_INNO_PCLK_DIV_D(cfg->pclk_div_d)); + + /* Write TMDSCLK dividers */ + inno_write(inno, STF_INNO_PRE_PLL_TMDSCLK_DIV, + STF_INNO_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | + STF_INNO_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | + STF_INNO_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b)); + + /* Write fractional divider registers */ + inno_write(inno, STF_INNO_PRE_PLL_FRAC_DIV_L, + STF_INNO_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv)); + inno_write(inno, STF_INNO_PRE_PLL_FRAC_DIV_M, + STF_INNO_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv)); + inno_write(inno, STF_INNO_PRE_PLL_FRAC_DIV_H, + STF_INNO_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv)); + + /* Power up Pre-PLL */ + inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL, + STF_INNO_PRE_PLL_POWER_DOWN, 0); + + inno->pixclock =3D rate; + inno->tmdsclock =3D tmdsclock; + + return 0; +} + +static const struct clk_ops starfive_hdmi_phy_clk_ops =3D { + .prepare =3D starfive_hdmi_phy_clk_prepare, + .unprepare =3D starfive_hdmi_phy_clk_unprepare, + .is_prepared =3D starfive_hdmi_phy_clk_is_prepared, + .recalc_rate =3D starfive_hdmi_phy_clk_recalc_rate, + .round_rate =3D starfive_hdmi_phy_clk_round_rate, + .set_rate =3D starfive_hdmi_phy_clk_set_rate, +}; + +static int starfive_hdmi_phy_power_on(struct phy *phy) +{ + struct starfive_hdmi_phy *inno =3D phy_get_drvdata(phy); + const struct post_pll_config *cfg =3D post_pll_cfg_table; + unsigned long tmdsclock =3D inno->tmdsclock; + u8 reg_1ad_value; + u8 reg_1aa_value; + + u32 v; + int ret; + + if (!tmdsclock) { + dev_err(inno->dev, "TMDS clock is zero (pixclock not set?)\n"); + return -EINVAL; + } + + /* Find Post-PLL config */ + for (; cfg->tmdsclock !=3D 0; cfg++) + if (tmdsclock <=3D cfg->tmdsclock) + break; + + if (cfg->tmdsclock =3D=3D 0) { + dev_err(inno->dev, "Failed to find Post-PLL config\n"); + return -EINVAL; + } + inno->post_cfg =3D cfg; + + dev_dbg(inno->dev, "Inno HDMI PHY Power On: pixclk %lu, tmdsclk %lu\n", + inno->pixclock, tmdsclock); + + reg_1ad_value =3D cfg->post_div_en ? cfg->postdiv : 0x00; + reg_1aa_value =3D cfg->post_div_en ? 0x0e : 0x02; + + /* + * Pre-PLL is already prepared and running at inno->pixclock + * via the clk_set_rate and prepare calls from the controller/bridge. + * Now, configure and enable the Post-PLL and TMDS outputs. + */ + + inno_write(inno, STF_INNO_POST_PLL_DIV_2, + STF_INNO_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, STF_INNO_POST_PLL_DIV_3, cfg->fbdiv & 0xff); + inno_write(inno, STF_INNO_POST_PLL_DIV_4, reg_1ad_value); + + /* Power up Post-PLL */ + inno_write(inno, STF_INNO_POST_PLL_DIV_1, reg_1aa_value); + + /* Wait for post PLL lock */ + ret =3D inno_poll(inno, STF_INNO_POST_PLL_LOCK_STATUS, v, + v & STF_INNO_POST_PLL_LOCK_STATUS, 1000, 100000); + if (ret) { + dev_err(inno->dev, "Post-PLL locking failed\n"); + return ret; + } + + inno_write(inno, STF_INNO_LDO_CONTROL, STF_INNO_LDO_ENABLE); + inno_write(inno, STF_INNO_SERIALIER_CONTROL, + STF_INNO_SERIALIER_ENABLE); + inno_write(inno, STF_INNO_TMDS_CONTROL, 0x8f); + + return 0; +} + +static int starfive_hdmi_phy_power_off(struct phy *phy) +{ + struct starfive_hdmi_phy *inno =3D phy_get_drvdata(phy); + + dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); + + inno_write(inno, STF_INNO_TMDS_CONTROL, 0x00); + inno_write(inno, STF_INNO_SERIALIER_CONTROL, 0x00); + inno_write(inno, STF_INNO_LDO_CONTROL, 0x00); + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, + STF_INNO_BIAS_ENABLE, 0x00); + inno_write(inno, STF_INNO_RX_CONTROL, 0x00); + + /* Power down Post-PLL */ + inno_update_bits(inno, STF_INNO_POST_PLL_DIV_1, + STF_INNO_POST_PLL_POWER_DOWN, + STF_INNO_POST_PLL_POWER_DOWN); + + /* + * Pre-PLL (our clock) is powered down by the + * clock framework via .unprepare (clk_disable_unprepare) + */ + clk_disable_unprepare(inno->phyclk); + + inno->tmdsclock =3D 0; + inno->pixclock =3D 0; + + return 0; +} + +static int starfive_hdmi_phy_init(struct phy *phy) +{ + return 0; +} + +static const struct phy_ops starfive_hdmi_phy_ops =3D { + .owner =3D THIS_MODULE, + .init =3D starfive_hdmi_phy_init, + .power_on =3D starfive_hdmi_phy_power_on, + .power_off =3D starfive_hdmi_phy_power_off, +}; + +static int starfive_hdmi_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device *parent =3D dev->parent; + struct starfive_hdmi_phy *inno; + struct phy_provider *phy_provider; + struct regmap *mfd_regmap; + struct clk_init_data init =3D {}; + const char *refoclk_name; + int ret; + + inno =3D devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL); + if (!inno) + return -ENOMEM; + + inno->dev =3D dev; + + /* Get the regmap from the MFD parent device */ + mfd_regmap =3D dev_get_regmap(parent, NULL); + if (!mfd_regmap) { + dev_err(dev, "Failed to get parent regmap\n"); + return -ENODEV; + } + inno->regmap =3D mfd_regmap; + + /* Get the input reference clock */ + inno->refoclk =3D devm_clk_get(inno->dev, "refoclk"); + if (IS_ERR(inno->refoclk)) { + ret =3D PTR_ERR(inno->refoclk); + dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n", + ret); + return ret; + } + + /* We must prepare/enable refoclk here so .set_rate/.recalc_rate work */ + ret =3D clk_prepare_enable(inno->refoclk); + if (ret) { + dev_err(dev, "Failed to enable refoclk: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, inno); + + /* Initialize and register the clock provider */ + refoclk_name =3D __clk_get_name(inno->refoclk); + init.parent_names =3D &refoclk_name; + init.num_parents =3D 1; + init.flags =3D 0; + init.name =3D "hdmi_pclk"; + init.ops =3D &starfive_hdmi_phy_clk_ops; + + of_property_read_string(dev->of_node, "clock-output-names", &init.name); + + inno->hw.init =3D &init; + inno->phyclk =3D devm_clk_register(dev, &inno->hw); + if (IS_ERR(inno->phyclk)) { + ret =3D PTR_ERR(inno->phyclk); + dev_err(dev, "Failed to register clock provider: %d\n", ret); + goto err_disable_refoclk; + } + + ret =3D of_clk_add_provider(dev->of_node, of_clk_src_simple_get, inno->ph= yclk); + if (ret) { + dev_err(dev, "Failed to add clock provider: %d\n", ret); + goto err_disable_refoclk; + } + + ret =3D clk_set_rate(inno->phyclk, 297000000); + if (ret) { + dev_err(dev, "Failed to set default rate: %d\n", ret); + goto err_disable_refoclk; + } + + /* Create and register the PHY provider */ + inno->phy =3D devm_phy_create(inno->dev, NULL, &starfive_hdmi_phy_ops); + if (IS_ERR(inno->phy)) { + ret =3D PTR_ERR(inno->phy); + dev_err(inno->dev, "failed to create HDMI PHY: %d\n", ret); + goto err_del_clk_provider; + } + + phy_set_drvdata(inno->phy, inno); + + /* Run PHY init */ + ret =3D starfive_hdmi_phy_init(inno->phy); + if (ret) + goto err_del_clk_provider; + + phy_provider =3D devm_of_phy_provider_register(inno->dev, + of_phy_simple_xlate); + ret =3D PTR_ERR_OR_ZERO(phy_provider); + if (ret) + goto err_del_clk_provider; + + return 0; + +err_del_clk_provider: + of_clk_del_provider(dev->of_node); +err_disable_refoclk: + clk_disable_unprepare(inno->refoclk); + return ret; +} + +static void starfive_hdmi_phy_remove(struct platform_device *pdev) +{ + struct starfive_hdmi_phy *inno =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + clk_disable_unprepare(inno->refoclk); +} + +static const struct of_device_id starfive_hdmi_phy_of_match[] =3D { + { .compatible =3D "starfive,jh7110-inno-hdmi-phy", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_hdmi_phy_of_match); + +static struct platform_driver starfive_hdmi_phy_driver =3D { + .probe =3D starfive_hdmi_phy_probe, + .remove =3D starfive_hdmi_phy_remove, + .driver =3D { + .name =3D "starfive-inno-hdmi-phy", + .of_match_table =3D starfive_hdmi_phy_of_match, + }, +}; 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Sat, 8 Nov 2025 01:05:11 +0000 (GMT) From: Michal Wilczynski Date: Sat, 08 Nov 2025 02:04:47 +0100 Subject: [PATCH RFC 13/13] riscv: dts: starfive: jh7110: Update DT for display subsystem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20251108-jh7110-clean-send-v1-13-06bf43bb76b1@samsung.com> In-Reply-To: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> To: Michal Wilczynski , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Icenowy Zheng , Maud Spierings , Andy Yan , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20251108010512eucas1p11f3e192a7b174f8585c98cb2efe68689 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20251108010512eucas1p11f3e192a7b174f8585c98cb2efe68689 X-EPHeader: CA X-CMS-RootMailID: 20251108010512eucas1p11f3e192a7b174f8585c98cb2efe68689 References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> Activate the display subsystem drivers by refactoring the device tree. This change wraps the dc8200, hdmi, and voutcrg nodes within the new vout_subsystem node. This ensures the PD_VOUT power domain is enabled before the child drivers are probed. The monolithic hdmi node is replaced with the hdmi_mfd (MFD parent) node, containing the hdmi_phy and hdmi_controller children. The voutcrg node is updated to consume the pixel clock from the &hdmi_phy node instead of the old fixed-clock. The dc8200 node is also updated to get its pixel clocks from voutcrg's MUXes. Finally, the old, incorrect hdmitx0-pixel-clock fixed-clock node is removed. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 119 ++++++++++++++++++++= +++- arch/riscv/boot/dts/starfive/jh7110.dtsi | 111 +++++++++++++++++---= -- 2 files changed, 207 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7110-common.dtsi index 2eaf01775ef57d884b4d662af3caa83da2d2ad48..ce459e297261393a35206170704= 1db453819885c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -33,6 +33,25 @@ memory@40000000 { bootph-pre-ram; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* vout applies for space from this CMA + * Without this CMA reservation, + * vout may not work properly. + */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x0 0x20000000>; + alignment =3D <0x0 0x1000>; + alloc-ranges =3D <0x0 0x70000000 0x0 0x20000000>; + linux,cma-default; + }; + }; + gpio-restart { compatible =3D "gpio-restart"; gpios =3D <&sysgpio 35 GPIO_ACTIVE_HIGH>; @@ -73,12 +92,47 @@ codec { }; }; }; + + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; }; =20 &cpus { timebase-frequency =3D <4000000>; }; =20 +&dc8200 { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_port0: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_out_dpi0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_in>; + }; + }; + + dpu_port1: port@1 { + reg =3D <1>; + }; + }; +}; + &dvp_clk { clock-frequency =3D <74250000>; }; @@ -99,8 +153,31 @@ &gmac1_rmii_refin { clock-frequency =3D <50000000>; }; =20 -&hdmitx0_pixelclk { - clock-frequency =3D <297000000>; +&hdmi_controller { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_pins>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dpi0>; + }; + }; + + hdmi_out_port: port@1 { + reg =3D <1>; + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + + }; + }; }; =20 &i2srx_bclk_ext { @@ -388,6 +465,40 @@ &syscrg { }; =20 &sysgpio { + hdmi_pins: hdmi-0 { + hdmi-cec-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + hdmi-hpd-pins { + pinmux =3D ; + input-enable; + bias-disable; /* external pull-up */ + }; + + hdmi-scl-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + hdmi-sda-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux =3D ; }; + +&voutcrg { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 0ba74ef046792fd63ed6cf971fa1438609b06fb1..da670a44dcec0f3dae65a2612c2= 4b79f3cdd7d6c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -283,12 +283,6 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock { #clock-cells =3D <0>; }; =20 - hdmitx0_pixelclk: hdmitx0-pixel-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "hdmitx0_pixelclk"; - #clock-cells =3D <0>; - }; - i2srx_bclk_ext: i2srx-bclk-ext-clock { compatible =3D "fixed-clock"; clock-output-names =3D "i2srx_bclk_ext"; @@ -344,6 +338,14 @@ tdm_ext: tdm-ext-clock { #clock-cells =3D <0>; }; =20 + xin24m: xin24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "xin24m"; + }; + + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -1203,22 +1205,89 @@ camss: isp@19840000 { status =3D "disabled"; }; =20 - voutcrg: clock-controller@295c0000 { - compatible =3D "starfive,jh7110-voutcrg"; - reg =3D <0x0 0x295c0000 0x0 0x10000>; - clocks =3D <&syscrg JH7110_SYSCLK_VOUT_SRC>, - <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, - <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, - <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, - <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, - <&hdmitx0_pixelclk>; - clock-names =3D "vout_src", "vout_top_ahb", - "vout_top_axi", "vout_top_hdmitx0_mclk", - "i2stx0_bclk", "hdmitx0_pixelclk"; - resets =3D <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; + vout_subsystem: display-subsystem@29400000 { + compatible =3D "starfive,jh7110-vout-subsystem"; + reg =3D <0x0 0x29400000 0x0 0x200000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + power-domains =3D <&pwrc JH7110_PD_VOUT>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>; + resets =3D <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>; + + dc8200: display@29400000 { + compatible =3D "verisilicon,dc"; + reg =3D <0x0 0x29400000 0x0 0x2800>; + interrupts =3D <95>; + + clocks =3D <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>; + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; + + resets =3D <&voutcrg JH7110_VOUTRST_DC8200_CORE>, + <&voutcrg JH7110_VOUTRST_DC8200_AXI>, + <&voutcrg JH7110_VOUTRST_DC8200_AHB>; + reset-names =3D "core", "axi", "ahb"; + }; + + hdmi_mfd: hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi-mfd"; + reg =3D <0x0 0x29590000 0x0 0x4000>; + + hdmi_phy: phy { + compatible =3D "starfive,jh7110-inno-hdmi-phy"; + + clocks =3D <&xin24m>; + clock-names =3D "refoclk"; + + /* Output clock: The variable pixel clock */ + #clock-cells =3D <0>; + clock-output-names =3D "hdmi_pclk"; + + /* PHY provider for the controller */ + #phy-cells =3D <0>; + }; + + hdmi_controller: controller { + compatible =3D "starfive,jh7110-inno-hdmi-controller"; + interrupts =3D <99>; + + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, + <&hdmi_phy>; + clock-names =3D "sys", "mclk", "bclk", "pclk"; + + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + reset-names =3D "hdmi_tx"; + + phys =3D <&hdmi_phy>; + phy-names =3D "hdmi-phy"; + }; + }; + + voutcrg: clock-controller@295c0000 { + compatible =3D "starfive,jh7110-voutcrg"; + reg =3D <0x0 0x295c0000 0x0 0x10000>; + + clocks =3D <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmi_phy>; + clock-names =3D "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + + resets =3D <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; }; =20 pcie0: pcie@940000000 { --=20 2.34.1