From nobody Mon Feb 9 00:03:46 2026 Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46E6D302747 for ; Fri, 7 Nov 2025 19:16:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.66 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762542975; cv=none; b=hVWVr8Z8ESdwQ6MFB71Rkx2gu1uCrsGnvCct2ozNsyfeE9v2tqE2WhErhNQLjz7Fy2A4Q5/uwfRuj54/GbgxB0wY0Pa3sKXXnpBKLRft6nNT41zwsB+WkJ1oTV+YX6irUDEMXbXyR2iLqCF9yiliZvoSMUrtBl6krItcOCgdHzg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762542975; c=relaxed/simple; bh=2ocZfsYLEyORGY2RIkS0+WK85kj+3iZiP/pJ0G668Pg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oz6wPya6HI6PpXeh6VD92EhPdzG3ghi94DoOcJylCs7LTKZ+jiFFd1wfHlwtKL2VBVPy77C4qfMOz9U36M7SjuPT0Azlg0fg+pYo7fzfwJDyOCpwZBUaNWJ3Yr53rd2mOC42dzGnkXfwuKPXS8lcMoBnxfDuLoC8lSpDVsph8Q0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com; spf=pass smtp.mailfrom=riscstar.com; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b=bzPXZYR0; arc=none smtp.client-ip=209.85.166.66 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riscstar.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b="bzPXZYR0" Received: by mail-io1-f66.google.com with SMTP id ca18e2360f4ac-94880628ffaso29233339f.0 for ; Fri, 07 Nov 2025 11:16:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1762542971; x=1763147771; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iPun3L1XgCMTeQ3bynZtUISWafgn6K8Gc9jGJeXkooo=; b=bzPXZYR0ZtBcwNYInFHHDpNJJ5XVYLxo6kQWch+RrnvRQepL0xQTn2Z/2DgPgl/qDG 0qPQ61KJ5HcaXwtGZkrmNOnDitSgOnWL0YQBVSeMfR+86rZ2Rxstd3OPVRKzSPjJUxit Gc03I8fNIr09mf6bXAasaALvPwm/qy3/bvDBV2li1PPQ7ezqKojp9wU1/SB74+dqYy8/ J1NPy8grMp/TAeHmUAfMSOoCMxhQ75Wu/wag4f3K2JKUzKldy7LBwhglJyeliI2HAHpP fL2OiznQRJNgE/+3k6Ybx3TdhCkYvSMLdHrUc3Kuh5eopnbUPwscDPoA+1jy6VhtOHmK 40Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762542971; x=1763147771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=iPun3L1XgCMTeQ3bynZtUISWafgn6K8Gc9jGJeXkooo=; b=pnE/OEcw62WG7n7JTTYp7SG0I8/q6gU+pi6ej7ppMo4gZms193/HF4FLw4eykbEQVF BmcslU2er6W7J8K7j0oKvJvds/pct8GuzSHvjCTWrPHPYiZf2gFi5UqgOukOo5J3m1t7 SOVErdGhII2Glm99UFfOKfAA8XlKqGWGLPWys9Z3PIM9iBAA0IJ2+RZ0nxUf8G1F2Vrb 6kU3qNgnTxWRLAeZQaf3Mt8uY2GbeAxmRk2c5Y0zCapRbkcfgS2x0BKsOEl28ZH6i8va uF+NwzoMrl4b4HKc28vVl7r0VmZyzZJcu5Xq1qTKXKgpsGDHtLSN7M9Qz2dxqN0fz2Pt tvRg== X-Forwarded-Encrypted: i=1; AJvYcCUPYgKSqmVWQWAXtJx4GUD1h+lY1zZQqzUYH+cUn+PWSdMcNbVCiDQpfTp1VaOZmGt4jjXZxK6I7aOSUEw=@vger.kernel.org X-Gm-Message-State: AOJu0Yx5kdQW5CP0fSQD8Lgtuy6yzuQajbysSCcVPxyF3fFOTF/Bo5T9 Cis5lEG0Gzpd/uyrhALGfsSFhFE80E2425HhZC0ro2BcNFUFhevAbZsmCjtAOxxAGB0= X-Gm-Gg: ASbGncvv2T2brYo7Wiz3niNbvYhOjs1w4VYQWV7hhvVtDWdZqkQZgtK7RDBX4Ryu1mV O1eRC++mZcSZOO6iMp0YSfhIYel5wtlqJrAQSMTWa39sqAHxU0VWglGqbkJlpA2LErdzATazJnp K7HAnBmK3H5rq1Ncd2B2EcO2TgeJojDd2WXDNlQ5NynYnOOb1qKIgqPujYh6mfZ8+UunsUcEv5i MaP4ZuGl+x8ykWW/DBfjYh3H8eGJ24/GxBzbRL+CZzhJabGtDhQYFhh32DovlHQaLVk/ch5S1oi HY+uI1hs+8UQH8SmdHfxvug76XakKQlbZ0JMd9KEgQukcgYAfRc1DDADVie/2oMFP98iddj/R0X +JI6frsTOPNnbinXnfwHTEhtvisXKGSajRELlTWEDS3g1uZ2w2+aRJPX7r4Zh6oQdCAqo2gJfyn VwKCRI1dPCeVvyiYS1pZmC7tjDU22Ml5voWJG1Lp5/82O4FvwveqhIjg== X-Google-Smtp-Source: AGHT+IGMngpNxasxOy5qpZHmxuLQ2gLe+aaxDuhNRzXMHr19MIE/5vhXEQ0iOJURKXuoVE6ifTCzwg== X-Received: by 2002:a92:d806:0:b0:433:382a:b39 with SMTP id e9e14a558f8ab-43362990414mr28103945ab.4.1762542971194; Fri, 07 Nov 2025 11:16:11 -0800 (PST) Received: from zippy.localdomain (c-75-72-117-212.hsd1.mn.comcast.net. [75.72.117.212]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-94888c34c6asm118772939f.10.2025.11.07.11.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 11:16:10 -0800 (PST) From: Alex Elder To: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com Cc: dlan@gentoo.org, aurelien@aurel32.net, johannes@erdfelt.com, p.zabel@pengutronix.de, christian.bruel@foss.st.com, thippeswamy.havalige@amd.com, krishna.chundru@oss.qualcomm.com, mayank.rana@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, shradha.t@samsung.com, inochiama@gmail.com, guodong@riscstar.com, linux-pci@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/7] PCI: spacemit: Add SpacemiT PCIe host driver Date: Fri, 7 Nov 2025 13:15:54 -0600 Message-ID: <20251107191557.1827677-6-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251107191557.1827677-1-elder@riscstar.com> References: <20251107191557.1827677-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a driver for the PCIe host controller found in the SpacemiT K1 SoC. The hardware is derived from the Synopsys DesignWare PCIe IP. The driver supports three PCIe ports that operate at PCIe gen2 transfer rates (5 GT/sec). The first port uses a combo PHY, which may be configured for use for USB 3 instead. Signed-off-by: Alex Elder --- v5: - Kconfig option now positioned based on vendor name sort - Kconfig option description has been expanded a bit - Kconfig option does not depend on PCI or OF=20 - dw_pcie_readl_dbi() and dw_pcie_writel_dbi() are now used when turning off ASPM L1 - In k1_pcie_phy_init(): - Vendor and device IDs are set earlier - PERST# is now asserted separately - phy_init() is now called later - Getting and enabling the regulator is done in the controller probe function, rather than relying on the root port driver doing that drivers/pci/controller/dwc/Kconfig | 13 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 353 ++++++++++++++++++ 3 files changed, 367 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-spacemit-k1.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index 349d4657393c9..718bb54e943f6 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -416,6 +416,19 @@ config PCIE_SOPHGO_DW Say Y here if you want PCIe host controller support on Sophgo SoCs. =20 +config PCIE_SPACEMIT_K1 + tristate "SpacemiT K1 PCIe controller (host mode)" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on HAS_IOMEM + select PCIE_DW_HOST + select PCI_PWRCTRL_SLOT + default ARCH_SPACEMIT + help + Enables support for the DesignWare based PCIe controller in + the SpacemiT K1 SoC operating in host mode. Three controllers + are available on the K1 SoC; the first of these shares a PHY + with a USB 3.0 host controller (one or the other can be used). + config PCIE_SPEAR13XX bool "STMicroelectronics SPEAr PCIe controller" depends on ARCH_SPEAR13XX || COMPILE_TEST diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 7ae28f3b0fb39..662b0a219ddc4 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_PCIE_UNIPHIER) +=3D pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) +=3D pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) +=3D pcie-visconti.o obj-$(CONFIG_PCIE_RCAR_GEN4) +=3D pcie-rcar-gen4.o +obj-$(CONFIG_PCIE_SPACEMIT_K1) +=3D pcie-spacemit-k1.o obj-$(CONFIG_PCIE_STM32_HOST) +=3D pcie-stm32.o obj-$(CONFIG_PCIE_STM32_EP) +=3D pcie-stm32-ep.o =20 diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/co= ntroller/dwc/pcie-spacemit-k1.c new file mode 100644 index 0000000000000..fd428a39b83cd --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SpacemiT K1 PCIe host driver + * + * Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reser= ved. + * Copyright (c) 2023, spacemit Corporation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define PCI_VENDOR_ID_SPACEMIT 0x201f +#define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 + +/* Offsets and field definitions for link management registers */ +#define K1_PHY_AHB_IRQ_EN 0x0000 +#define PCIE_INTERRUPT_EN BIT(0) + +#define K1_PHY_AHB_LINK_STS 0x0004 +#define SMLH_LINK_UP BIT(1) +#define RDLH_LINK_UP BIT(12) + +#define INTR_ENABLE 0x0014 +#define MSI_CTRL_INT BIT(11) + +/* Some controls require APMU regmap access */ +#define SYSCON_APMU "spacemit,apmu" + +/* Offsets and field definitions for APMU registers */ +#define PCIE_CLK_RESET_CONTROL 0x0000 +#define LTSSM_EN BIT(6) +#define PCIE_AUX_PWR_DET BIT(9) +#define PCIE_RC_PERST BIT(12) /* 1: assert PERST# */ +#define APP_HOLD_PHY_RST BIT(30) +#define DEVICE_TYPE_RC BIT(31) /* 0: endpoint; 1: RC */ + +#define PCIE_CONTROL_LOGIC 0x0004 +#define PCIE_SOFT_RESET BIT(0) + +struct k1_pcie { + struct dw_pcie pci; + struct phy *phy; + void __iomem *link; + struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ + u32 pmu_off; +}; + +#define to_k1_pcie(dw_pcie) \ + platform_get_drvdata(to_platform_device((dw_pcie)->dev)) + +static void k1_pcie_toggle_soft_reset(struct k1_pcie *k1) +{ + u32 offset; + u32 val; + + /* + * Write, then read back to guarantee it has reached the device + * before we start the delay. + */ + offset =3D k1->pmu_off + PCIE_CONTROL_LOGIC; + regmap_set_bits(k1->pmu, offset, PCIE_SOFT_RESET); + regmap_read(k1->pmu, offset, &val); + + mdelay(2); + + regmap_clear_bits(k1->pmu, offset, PCIE_SOFT_RESET); +} + +/* Enable app clocks, deassert resets */ +static int k1_pcie_enable_resources(struct k1_pcie *k1) +{ + struct dw_pcie *pci =3D &k1->pci; + int ret; + + ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(pci->app_clks), pci->app_clks); + if (ret) + return ret; + + ret =3D reset_control_bulk_deassert(ARRAY_SIZE(pci->app_rsts), + pci->app_rsts); + if (ret) + goto err_disable_clks; + + return 0; + +err_disable_clks: + clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks); + + return ret; +} + +/* Assert resets, disable app clocks */ +static void k1_pcie_disable_resources(struct k1_pcie *k1) +{ + struct dw_pcie *pci =3D &k1->pci; + + reset_control_bulk_assert(ARRAY_SIZE(pci->app_rsts), pci->app_rsts); + clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks); +} + +static int k1_pcie_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct k1_pcie *k1 =3D to_k1_pcie(pci); + u32 reset_ctrl; + u32 val; + int ret; + + k1_pcie_toggle_soft_reset(k1); + + ret =3D k1_pcie_enable_resources(k1); + if (ret) + return ret; + + /* Set the PCI vendor and device ID */ + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K1); + dw_pcie_dbi_ro_wr_dis(pci); + + /* + * Start by asserting fundamental reset (drive PERST# low). The + * PCI CEM spec says that PERST# should be deasserted at least + * 100ms after the power becomes stable, so we'll insert that + * delay first. Write, then read it back to guarantee the write + * reaches the device before we start the delay. + */ + reset_ctrl =3D k1->pmu_off + PCIE_CLK_RESET_CONTROL; + regmap_set_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST); + regmap_read(k1->pmu, reset_ctrl, &val); + mdelay(PCIE_T_PVPERL_MS); + + /* + * Put the controller in root complex mode, and indicate that + * Vaux (3.3v) is present. + */ + regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); + + ret =3D phy_init(k1->phy); + if (ret) { + k1_pcie_disable_resources(k1); + + return ret; + } + + /* Finally deassert fundamental reset (drive PERST# high) */ + regmap_clear_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST); + + return 0; +} + +/* Disable ASPM L1 for now, until reported errors can be reproduced */ +static void k1_pcie_post_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + u8 offset; + u32 val; + + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset +=3D PCI_EXP_LNKCAP; + + /* Turn off ASPM L1 for the link */ + dw_pcie_dbi_ro_wr_en(pci); + val =3D dw_pcie_readl_dbi(pci, offset); + val &=3D ~PCI_EXP_LNKCAP_ASPM_L1; + dw_pcie_writel_dbi(pci, offset, val); + dw_pcie_dbi_ro_wr_dis(pci); +} + +static void k1_pcie_deinit(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct k1_pcie *k1 =3D to_k1_pcie(pci); + + /* Assert fundamental reset (drive PERST# low) */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, + PCIE_RC_PERST); + + phy_exit(k1->phy); + + k1_pcie_disable_resources(k1); +} + +static const struct dw_pcie_host_ops k1_pcie_host_ops =3D { + .init =3D k1_pcie_init, + .post_init =3D k1_pcie_post_init, + .deinit =3D k1_pcie_deinit, +}; + +static bool k1_pcie_link_up(struct dw_pcie *pci) +{ + struct k1_pcie *k1 =3D to_k1_pcie(pci); + u32 val; + + val =3D readl_relaxed(k1->link + K1_PHY_AHB_LINK_STS); + + return (val & RDLH_LINK_UP) && (val & SMLH_LINK_UP); +} + +static int k1_pcie_start_link(struct dw_pcie *pci) +{ + struct k1_pcie *k1 =3D to_k1_pcie(pci); + u32 val; + + /* Stop holding the PHY in reset, and enable link training */ + regmap_update_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, + APP_HOLD_PHY_RST | LTSSM_EN, LTSSM_EN); + + /* Enable the MSI interrupt */ + writel_relaxed(MSI_CTRL_INT, k1->link + INTR_ENABLE); + + /* Top-level interrupt enable */ + val =3D readl_relaxed(k1->link + K1_PHY_AHB_IRQ_EN); + val |=3D PCIE_INTERRUPT_EN; + writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN); + + return 0; +} + +static void k1_pcie_stop_link(struct dw_pcie *pci) +{ + struct k1_pcie *k1 =3D to_k1_pcie(pci); + u32 val; + + /* Disable interrupts */ + val =3D readl_relaxed(k1->link + K1_PHY_AHB_IRQ_EN); + val &=3D ~PCIE_INTERRUPT_EN; + writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN); + + writel_relaxed(0, k1->link + INTR_ENABLE); + + /* Disable the link and hold the PHY in reset */ + regmap_update_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, + APP_HOLD_PHY_RST | LTSSM_EN, APP_HOLD_PHY_RST); +} + +static const struct dw_pcie_ops k1_pcie_ops =3D { + .link_up =3D k1_pcie_link_up, + .start_link =3D k1_pcie_start_link, + .stop_link =3D k1_pcie_stop_link, +}; + +static int k1_pcie_parse_port(struct k1_pcie *k1) +{ + struct device *dev =3D k1->pci.dev; + struct device_node *root_port; + struct phy *phy; + + /* We assume only one root port */ + root_port =3D of_get_next_available_child(dev_of_node(dev), NULL); + if (!root_port) + return -EINVAL; + + phy =3D devm_of_phy_get(dev, root_port, NULL); + + of_node_put(root_port); + + if (IS_ERR(phy)) + return PTR_ERR(phy); + + k1->phy =3D phy; + + return 0; +} + +static int k1_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct k1_pcie *k1; + int ret; + + k1 =3D devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); + if (!k1) + return -ENOMEM; + + k1->pmu =3D syscon_regmap_lookup_by_phandle_args(dev_of_node(dev), + SYSCON_APMU, 1, + &k1->pmu_off); + if (IS_ERR(k1->pmu)) + return dev_err_probe(dev, PTR_ERR(k1->pmu), + "failed to lookup PMU registers\n"); + + k1->link =3D devm_platform_ioremap_resource_byname(pdev, "link"); + if (!k1->link) + return dev_err_probe(dev, -ENOMEM, + "failed to map \"link\" registers\n"); + + k1->pci.dev =3D dev; + k1->pci.ops =3D &k1_pcie_ops; + dw_pcie_cap_set(&k1->pci, REQ_RES); + + k1->pci.pp.ops =3D &k1_pcie_host_ops; + + /* Hold the PHY in reset until we start the link */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, + APP_HOLD_PHY_RST); + + ret =3D devm_regulator_get_enable(dev, "vpcie3v3"); + if (ret) + return dev_err_probe(dev, ret, + "failed to get \"vpcie3v3\" supply\n"); + + pm_runtime_set_active(dev); + pm_runtime_no_callbacks(dev); + devm_pm_runtime_enable(dev); + + platform_set_drvdata(pdev, k1); + + ret =3D k1_pcie_parse_port(k1); + if (ret) + return dev_err_probe(dev, ret, "failed to parse root port\n"); + + ret =3D dw_pcie_host_init(&k1->pci.pp); + if (ret) + return dev_err_probe(dev, ret, "failed to initialize host\n"); + + return 0; +} + +static void k1_pcie_remove(struct platform_device *pdev) +{ + struct k1_pcie *k1 =3D platform_get_drvdata(pdev); + + dw_pcie_host_deinit(&k1->pci.pp); +} + +static const struct of_device_id k1_pcie_of_match_table[] =3D { + { .compatible =3D "spacemit,k1-pcie", }, + { }, +}; + +static struct platform_driver k1_pcie_driver =3D { + .probe =3D k1_pcie_probe, + .remove =3D k1_pcie_remove, + .driver =3D { + .name =3D "spacemit-k1-pcie", + .of_match_table =3D k1_pcie_of_match_table, + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + }, +}; +module_platform_driver(k1_pcie_driver); --=20 2.48.1