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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-94888c34c6asm118772939f.10.2025.11.07.11.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 11:16:07 -0800 (PST) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org Cc: dlan@gentoo.org, guodong@riscstar.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/7] dt-bindings: pci: spacemit: Introduce PCIe host controller Date: Fri, 7 Nov 2025 13:15:52 -0600 Message-ID: <20251107191557.1827677-4-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251107191557.1827677-1-elder@riscstar.com> References: <20251107191557.1827677-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the Device Tree binding for the PCIe root complex found on the SpacemiT K1 SoC. This device is derived from the Synopsys Designware PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2 link speeds (5 GT/sec). One of the ports uses a combo PHY, which is typically used to support a USB 3 port. Reviewed-by: Rob Herring (Arm) Signed-off-by: Alex Elder --- v5: - Add Rob Herring's Reviewed-by tag - Wrap lines at 80 columns - Root port nodes will begin with pcie ('e' is not optional) .../bindings/pci/spacemit,k1-pcie-host.yaml | 157 ++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-= host.yaml diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.ya= ml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml new file mode 100644 index 0000000000000..c4c00b5fcdc0c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PCI Express Host Controller + +maintainers: + - Alex Elder + +description: > + The SpacemiT K1 SoC PCIe host controller is based on the Synopsys Design= Ware + PCIe IP. The controller uses the DesignWare built-in MSI interrupt + controller, and supports 256 MSIs. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: spacemit,k1-pcie + + reg: + items: + - description: DesignWare PCIe registers + - description: ATU address space + - description: PCIe configuration space + - description: Link control registers + + reg-names: + items: + - const: dbi + - const: atu + - const: config + - const: link + + clocks: + items: + - description: DWC PCIe Data Bus Interface (DBI) clock + - description: DWC PCIe application AXI-bus master interface clock + - description: DWC PCIe application AXI-bus slave interface clock + + clock-names: + items: + - const: dbi + - const: mstr + - const: slv + + resets: + items: + - description: DWC PCIe Data Bus Interface (DBI) reset + - description: DWC PCIe application AXI-bus master interface reset + - description: DWC PCIe application AXI-bus slave interface reset + + reset-names: + items: + - const: dbi + - const: mstr + - const: slv + + interrupts: + items: + - description: Interrupt used for MSIs + + interrupt-names: + const: msi + + spacemit,apmu: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle that refers to the APMU system controller, whose regmap is + used in managing resets and link state, along with and offset of its + reset control register. + items: + - items: + - description: phandle to APMU system controller + - description: register offset + +patternProperties: + '^pcie@': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + phys: + maxItems: 1 + + vpcie3v3-supply: + description: + A phandle for 3.3v regulator to use for PCIe + + required: + - phys + - vpcie3v3-supply + + unevaluatedProperties: false + +required: + - clocks + - clock-names + - resets + - reset-names + - interrupts + - interrupt-names + - spacemit,apmu + +unevaluatedProperties: false + +examples: + - | + #include + pcie@ca400000 { + device_type =3D "pci"; + compatible =3D "spacemit,k1-pcie"; + reg =3D <0xca400000 0x00001000>, + <0xca700000 0x0001ff24>, + <0x9f000000 0x00002000>, + <0xc0c20000 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x9f002000 0x0 0x00100000>, + <0x02000000 0x0 0x90000000 0x90000000 0x0 0x0f000000>; + interrupts =3D <142>; + interrupt-names =3D "msi"; + clocks =3D <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>; + reset-names =3D "dbi", + "mstr", + "slv"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_3_cfg>; + spacemit,apmu =3D <&syscon_apmu 0x3d4>; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie1_phy>; + vpcie3v3-supply =3D <&pcie_vcc_3v3>; + }; + }; --=20 2.48.1