From nobody Fri Dec 19 20:17:07 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8802C2BD5B9; Fri, 7 Nov 2025 16:25:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762532759; cv=none; b=X7F01TkJutZ/nRpPEqeAHErqrdMaatQ3YRGA6aAXnbj4iPbC6MLLN/8pYm5dwomNthwL75ModCpXDrgIVBACPQaWt9rdVO2DhQVBMAx59WMCzL0YewBvPj8mKu6zWcI/Mo5D3lmlWTQg5iTw+Z+QaIX6pmB7MvYkCjgMAmAYF5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762532759; c=relaxed/simple; bh=7CwFn3glPOx+LEuwLyVNBz8w4VFBGU+ikxsXH3OvEZM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JoCJArT6o3ueY8SENqqbPKZTWWSGaz3syeT1NgV68MFF5sc64jfb2u7ppFcRvtJLWF87C0Ym8N1Q6Xhe01b+k4EKGGwGQN5gT2wrNJ3DzY6XqphKla9tJDVFmRM+pbUjQePh5vbq2EDh6xHh8s9zIAIN20Z6xchCM6zGxUhnc+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aVryJvXp; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aVryJvXp" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5A7D0ooh2282023; Fri, 7 Nov 2025 16:25:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wejWMBrYU48tLmTyosI5XfDNT011hcTBGXvSUb8Cw9s=; b=aVryJvXpOJJa/lhM FLZyG7K9pYzPNeoSnIYGKJAxPPNi5d4pLmQPAHODPsPcvgY7OxFRHrYM4wlukTGu PvvC3o6SCrRahEdHo98ntbfCrQyiMkjf9N0fXlxAyTUEY4Sdb5ANASlGyQrhWyMr Zq97E1Krv8s6oxauUCXHyEY06fIn0RuNWffJP7WEkxWQruoSdAh438tETKj8zNZe Kt51GkBYnofaMcjLHmoMeaaZApyARyEJOJB+JOFaO6aBUG6HyCPz+1DL5sQs+MQo CnRAh6m8t7FADWghEbGcKBfea/dyrvqu/uvf6M77lPvBXc7vS9XJV3sojtFMiYvr M2Z90A== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4a9a9shv6g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Nov 2025 16:25:47 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5A7GPkQV024442 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Nov 2025 16:25:46 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Fri, 7 Nov 2025 08:25:40 -0800 From: Vikram Sharma To: , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v6 1/2] dt-bindings: media: qcom,qcs8300-camss: Add missing power supplies Date: Fri, 7 Nov 2025 21:55:20 +0530 Message-ID: <20251107162521.511536-2-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251107162521.511536-1-quic_vikramsa@quicinc.com> References: <20251107162521.511536-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=CdgFJbrl c=1 sm=1 tr=0 ts=690e1d8b cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=Cg3GaYijB682ADaUwpUA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA3MDEzNSBTYWx0ZWRfX7KWhvaCkoG4G pBJLSRAY7dkbwytqYYt3GE8mwh+t8BGoUk94SOc+mkVH+XpWIyYK/S5ekiYLtdEYIo+gGCOpbNS WSO4xY8ZsnIwDGWzrU2dk35iI+H5Cd4kkVGYmBrN1A7HY9lPne24T7YLzBQodrIfxBWHGmrS/Vj CmBK8PAyLfTJhc9DefE0/KZCdUWqlCe0KkhPE+aZQKchbmWJ1aQV2UZUFHrEbV3505OB03SDt7L n3TvSWzvPf4GagS6ZW2xEBupWCSfBMcPDOsqmn7iHZfs7eaDcnSTurCH0w06r06rC2RELgFdiw+ XXkp16fjL9K2oM0qdyJ4oPDGOR8XCvPwbIoiIxT3Y1e31MDv5PfheiZ7sHI2EkRvPARKpf9w58o 8M51hnpG3WtGRcVRCofqieLyjFSz+Q== X-Proofpoint-ORIG-GUID: 6tor7pudIUAbELG53kSioz-X6DKPGxdE X-Proofpoint-GUID: 6tor7pudIUAbELG53kSioz-X6DKPGxdE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-07_04,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511070135 Content-Type: text/plain; charset="utf-8" Add missing vdda-phy-supply and vdda-pll-supply in the (monaco)qcs8300 camss binding. While enabling imx412 sensor for qcs8300 we see a need to add these supplies which were missing in initial submission. Fixes: 634a2958fae30 ("media: dt-bindings: Add qcom,qcs8300-camss compatibl= e") Cc: Co-developed-by: Nihal Kumar Gupta Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/qcom,qcs8300-camss.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yam= l b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml index 80a4540a22dc..e5f170aa4d9e 100644 --- a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml @@ -120,6 +120,14 @@ properties: items: - const: top =20 + vdda-phy-supply: + description: + Phandle to a 0.88V regulator supply to CSI PHYs. + + vdda-pll-supply: + description: + Phandle to 1.2V regulator supply to CSI PHYs pll block. + ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -160,6 +168,8 @@ required: - power-domains - power-domain-names - ports + - vdda-phy-supply + - vdda-pll-supply =20 additionalProperties: false =20 @@ -328,6 +338,9 @@ examples: power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; power-domain-names =3D "top"; =20 + vdda-phy-supply =3D <&vreg_l4a_0p88>; + vdda-pll-supply =3D <&vreg_l1c_1p2>; + ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1 From nobody Fri Dec 19 20:17:07 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D96128003A; Fri, 7 Nov 2025 16:26:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762532766; cv=none; b=E+MJfG9yeAnqd+KnOc4rid1Db1DWZvkYZ4TxAm0/0HsVHJpl29nAcGAsNvvrOJ/9h9luuS+uOceWAn8FAYghzffZDyI8rGt+PEh9T6wwc6QSIdIPhepEn4yzkKz44d6e1Ggx6w55EMD0A4s7fBuiVGftz2apwBSQQJkEsOgRYZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762532766; c=relaxed/simple; bh=PHPATmNt8kaxQF+BqKnO/NhP4pQunc7NGKgbOLo/wkY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SabdYR+2uppQ0uh4389ciAN8TuzDhcq9vd6uU03TwakmszxD14OyEarKzpjSAwQmdJC9C21MwAzUv518u9+73XIGK6Ha+K6MGxyGx5NU8pfuscUPgiC/E/XFwK3uZHzR1OirfsAmBNiPx8Q/fYbi4HT5w1QpARnTrxV5ov2hnR8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=PzawPGQT; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PzawPGQT" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5A7FkLLF630889; Fri, 7 Nov 2025 16:25:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= DB/UCOqHnpALAfKhtycs9LeBvRVIeZ8ZLA5pJK7PKaU=; b=PzawPGQT/C9LdZDC 400LrcMCSNX0kVC3b7+IpPDBLOg/WjaKG/VRAgBKutFdWGt8pn/0T1fv8NFq5qOU jhMbVAthnUU7jFzWhPwVUlx/+cQXSrzRYmzxKmoZuDlWBfma1kHf01Px7xq3NIW0 3TnJB76sdhtOjV2Sca3eji+eurBxNyX8hQP6N8eNdSY846Qq4hBnE4ep/GXhaecw 2QKvhNVGRMS1lDuDU9nS7jVLXb4kfLxycjsd85OFScVegOtWija3mQdZD2nBf7cN nqGSatbS94iWibDzuwTRYQfHnWDyo3v8gwAvcTULOX/liRl9L/BBfRXq5pIZBVaB gpI2XA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4a922337s0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Nov 2025 16:25:52 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5A7GPp5t028644 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Nov 2025 16:25:51 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Fri, 7 Nov 2025 08:25:46 -0800 From: Vikram Sharma To: , , , , , , , , , , CC: , , , , , , , , Konrad Dybcio Subject: [PATCH v6 2/2] arm64: dts: qcom: qcs8300: Add support for camss Date: Fri, 7 Nov 2025 21:55:21 +0530 Message-ID: <20251107162521.511536-3-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251107162521.511536-1-quic_vikramsa@quicinc.com> References: <20251107162521.511536-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA3MDEzNSBTYWx0ZWRfX8eCnqWIAgY4D yn7ZOfJHWj9Gghvuqr3JPyABTfPdGG6xb+1NefCrQkiYPc0qstbIYH27433FNJCJTGnEEItTCcZ Lzr4t7G8vP9FUCyo2R/8uHdvHwo6EAbXh73BN0zzVWy0R53ns63ek/PN+Jazpbpki9GQ78/CMHv jV8yQD4htjW54FbIuNv1n8+Ht1gAWPkPbj1mYUNS/zT4doN9NVrGw3BObM1UeWke/VNrZ8wBY4f B4ayAbcbbtsLSXLD237BmH7GejVuto5S8qFhREFsW1JjRkuswDy3Nxuo/uPV1vLX1Xt0oOYbkdw dAEZaX6vFxHGJSY/nKYzrc358sbfATsqgsebCw8dkP8kwnxYSdMBE87Ht8CretsK40RCsyV4Cq8 /HSIJofph4/qzxz9lXCmvKtLo1prxQ== X-Authority-Analysis: v=2.4 cv=Csmys34D c=1 sm=1 tr=0 ts=690e1d90 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=49fK2wAub7YDTLIv2YQA:9 a=FOEl7-wtY1rPn7cj:21 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-GUID: IyYdVxUOFdEnPNvedShlfPek0n2dVHgo X-Proofpoint-ORIG-GUID: IyYdVxUOFdEnPNvedShlfPek0n2dVHgo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-07_04,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511070135 Content-Type: text/plain; charset="utf-8" Add changes to support the camera subsystem on the QCS8300. Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Signed-off-by: Vikram Sharma Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/monaco.dtsi | 172 +++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 816fa2af8a9a..774255c3f6fc 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4776,6 +4776,178 @@ videocc: clock-controller@abf0000 { #power-domain-cells =3D <1>; }; =20 + camss: isp@ac78000 { + compatible =3D "qcom,qcs8300-camss"; + + reg =3D <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0xf00>, + <0x0 0xac7c000 0x0 0xf00>, + <0x0 0xac84000 0x0 0xf00>, + <0x0 0xac88000 0x0 0xf00>, + <0x0 0xac8c000 0x0 0xf00>, + <0x0 0xac90000 0x0 0xf00>, + <0x0 0xac94000 0x0 0xf00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x400>, + <0x0 0xacad000 0x0 0x400>, + <0x0 0xacae000 0x0 0x400>, + <0x0 0xac4d000 0x0 0xf000>, + <0x0 0xac60000 0x0 0xf000>, + <0x0 0xac85000 0x0 0xd00>, + <0x0 0xac89000 0x0 0xd00>, + <0x0 0xac8d000 0x0 0xd00>, + <0x0 0xac91000 0x0 0xd00>, + <0x0 0xac95000 0x0 0xd00>; + reg-names =3D "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names =3D "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_0"; + + iommus =3D <&apps_smmu 0x2400 0x20>; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names =3D "top"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible =3D "qcom,qcs8300-camcc"; reg =3D <0x0 0x0ade0000 0x0 0x20000>; --=20 2.34.1