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[93.34.90.37]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4776bd087b1sm66665955e9.16.2025.11.07.08.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 08:13:35 -0800 (PST) From: Christian Marangi To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: nvmem: airoha: add SMC eFuses schema Date: Fri, 7 Nov 2025 17:13:21 +0100 Message-ID: <20251107161325.2309275-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251107161325.2309275-1-ansuelsmth@gmail.com> References: <20251107161325.2309275-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Airoha SMC eFuses schema to document new Airoha SoC AN7581/AN7583 way of accessing the 2 eFuse bank via the SMC command. Each eFuse bank expose 64 eFuse cells of 32 bit used to give information on HW Revision, PHY Calibration, Device Model, Private Key and all kind of other info specific to the SoC or the running system. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/nvmem/airoha,smc-efuses.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/airoha,smc-efus= es.yaml diff --git a/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml= b/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml new file mode 100644 index 000000000000..e21ce07c4f41 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/airoha,smc-efuses.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha SMC eFuses + +description: | + Airoha new SoC (AN7581/AN7583) expose banks of eFuse accessible + via specific SMC commands. + + 2 different bank of eFuse or 64 cells of 32 bit are exposed + read-only used to give information on HW Revision, PHY Calibration, + Device Model, Private Key... + +maintainers: + - Christian Marangi + +properties: + compatible: + enum: + - airoha,an7581-efuses + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + '^efuse-bank@[0-1]$': + type: object + + allOf: + - $ref: nvmem.yaml# + + properties: + reg: + description: Identify the eFuse bank. + enum: [0, 1] + + required: + - reg + + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + efuse { + compatible =3D "airoha,an7581-efuses"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + efuse-bank@0 { + reg =3D <0>; + }; + }; + +... --=20 2.51.0 From nobody Fri Dec 19 20:15:28 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCD5332F745 for ; Fri, 7 Nov 2025 16:13:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762532020; cv=none; b=vGkR8pVA4BjArNhI5pBRmJYv/d0xccoXvSTI08PSw190cUUawflUhdtq6ryf7c4IzqRai8fgmE1r2XHegYUfPgP+3nqbB7/nqi1rxdcJQsrax6DramB4NmCBC5YQzReMmAeauKb9loyoxQ4PxSLcEbsEdxvdJU1xH2Cc7mCpsIQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762532020; c=relaxed/simple; bh=hrrLzMnZuUkom8I9qzvbne/uAV8TzA4LfzM4RMkjwr0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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[93.34.90.37]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4776bd087b1sm66665955e9.16.2025.11.07.08.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 08:13:36 -0800 (PST) From: Christian Marangi To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] nvmem: airoha: Add support for SMC eFUSE Date: Fri, 7 Nov 2025 17:13:22 +0100 Message-ID: <20251107161325.2309275-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251107161325.2309275-1-ansuelsmth@gmail.com> References: <20251107161325.2309275-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for SMC eFUSE on AN7581 SoC. The SoC have 2 set of 2048 bits of eFUSE that are used to read calibration value for PCIe, Thermal, USB and other specific info of the SoC like revision and HW device present. eFuse value are taken by sending SMC command. ATF is responsible of validaing the data and rejecting reading protected data (like Private Key). In such case the SMC command will return non-zero value on a0 register. Signed-off-by: Christian Marangi --- drivers/nvmem/Kconfig | 13 ++++ drivers/nvmem/Makefile | 2 + drivers/nvmem/airoha-smc-efuses.c | 118 ++++++++++++++++++++++++++++++ 3 files changed, 133 insertions(+) create mode 100644 drivers/nvmem/airoha-smc-efuses.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index bf47a982cf62..c2de26977c95 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -28,6 +28,19 @@ source "drivers/nvmem/layouts/Kconfig" =20 # Devices =20 +config NVMEM_AIROHA_SMC_EFUSES + tristate "Airoha SMC eFuse support" + depends on ARCH_AIROHA || COMPILE_TEST + depends on HAVE_ARM_SMCCC + default ARCH_AIROHA + help + Say y here to enable support for reading eFuses on Airoha AN7581 + SoCs. These are e.g. used to store factory programmed + calibration data required for the PCIe or the USB-C PHY or Thermal. + + This driver can also be built as a module. If so, the module will + be called nvmem-airoha-smc-efuses. + config NVMEM_AN8855_EFUSE tristate "Airoha AN8855 eFuse support" depends on MFD_AIROHA_AN8855 || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 7252b8ec88d4..f6f2bc51dee1 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -10,6 +10,8 @@ nvmem_layouts-y :=3D layouts.o obj-y +=3D layouts/ =20 # Devices +obj-$(CONFIG_NVMEM_AIROHA_SMC_EFUSES) +=3D nvmem-airoha-smc-efuses.o +nvmem-airoha-smc-efuses-y :=3D airoha-smc-efuses.o obj-$(CONFIG_NVMEM_AN8855_EFUSE) +=3D nvmem-an8855-efuse.o nvmem-an8855-efuse-y :=3D an8855-efuse.o obj-$(CONFIG_NVMEM_APPLE_EFUSES) +=3D nvmem-apple-efuses.o diff --git a/drivers/nvmem/airoha-smc-efuses.c b/drivers/nvmem/airoha-smc-e= fuses.c new file mode 100644 index 000000000000..bb279d149519 --- /dev/null +++ b/drivers/nvmem/airoha-smc-efuses.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include + +#define AIROHA_SMC_EFUSE_FID 0x82000001 +#define AIROHA_SMC_EFUSE_SUB_ID_READ 0x44414552 + +#define AIROHA_EFUSE_CELLS 64 + +struct airoha_efuse_bank_priv { + u8 bank_index; +}; + +static int airoha_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct regmap *regmap =3D context; + + return regmap_bulk_read(regmap, offset, + val, bytes / sizeof(u32)); +} + +static int airoha_efuse_reg_read(void *context, unsigned int offset, + unsigned int *val) +{ + struct airoha_efuse_bank_priv *priv =3D context; + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(AIROHA_SMC_EFUSE_FID, + AIROHA_SMC_EFUSE_SUB_ID_READ, + priv->bank_index, offset, 0, 0, 0, 0, &res); + + /* check if SMC reported an error */ + if (res.a0) + return -EIO; + + *val =3D res.a1; + return 0; +} + +static const struct regmap_config airoha_efuse_regmap_config =3D { + .reg_read =3D airoha_efuse_reg_read, + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int airoha_efuse_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + for_each_child_of_node_scoped(dev->of_node, child) { + struct nvmem_config airoha_nvmem_config =3D { + .name =3D "airoha-efuse", + .size =3D AIROHA_EFUSE_CELLS * sizeof(u32), + .stride =3D sizeof(u32), + .word_size =3D sizeof(u32), + .reg_read =3D airoha_efuse_read, + }; + struct airoha_efuse_bank_priv *priv; + struct nvmem_device *nvmem; + struct regmap *regmap; + u32 bank; + + ret =3D of_property_read_u32(child, "reg", &bank); + if (ret) + return ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->bank_index =3D bank; + + regmap =3D devm_regmap_init(dev, NULL, priv, + &airoha_efuse_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + airoha_nvmem_config.priv =3D regmap; + airoha_nvmem_config.dev =3D dev; + airoha_nvmem_config.id =3D bank; + nvmem =3D devm_nvmem_register(dev, &airoha_nvmem_config); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + } + + return 0; +} + +static const struct of_device_id airoha_efuse_of_match[] =3D { + { .compatible =3D "airoha,an7581-efuses", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_efuse_of_match); + +static struct platform_driver airoha_efuse_driver =3D { + .probe =3D airoha_efuse_probe, + .driver =3D { + .name =3D "airoha-efuse", + .of_match_table =3D airoha_efuse_of_match, + }, +}; +module_platform_driver(airoha_efuse_driver); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for Airoha SMC eFUSEs"); +MODULE_LICENSE("GPL"); --=20 2.51.0