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[2.205.18.238]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bf312240sm179779666b.18.2025.11.07.00.08.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 00:08:08 -0800 (PST) From: Jonas Gorski To: Florian Fainelli , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 8/8] net: dsa: b53: add support for bcm63xx ARL entry format Date: Fri, 7 Nov 2025 09:07:49 +0100 Message-ID: <20251107080749.26936-9-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251107080749.26936-1-jonas.gorski@gmail.com> References: <20251107080749.26936-1-jonas.gorski@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ARL registers of BCM63XX embedded switches are somewhat unique. The normal ARL table access registers have the same format as BCM5389, but the ARL search registers differ: * SRCH_CTL is at the same offset of BCM5389, but 16 bits wide. It does not have more fields, just needs to be accessed by a 16 bit read. * SRCH_RSLT_MACVID and SRCH_RSLT are aligned to 32 bit, and have shifted offsets. * SRCH_RSLT has a different format than the normal ARL data entry register. * There is only one set of ENTRY_N registers, implying a 1 bin layout. So add appropriate ops for bcm63xx and let it use it. Signed-off-by: Jonas Gorski Reviewed-by: Florian Fainelli --- drivers/net/dsa/b53/b53_common.c | 44 +++++++++++++++++++++++++++----- drivers/net/dsa/b53/b53_priv.h | 15 +++++++++++ drivers/net/dsa/b53/b53_regs.h | 9 +++++++ 3 files changed, 61 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_com= mon.c index 73ea9adb95b7..72c85cd34a4e 100644 --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c @@ -2058,12 +2058,20 @@ static void b53_read_arl_srch_ctl(struct b53_device= *dev, u8 *val) =20 if (is5325(dev) || is5365(dev)) offset =3D B53_ARL_SRCH_CTL_25; - else if (dev->chip_id =3D=3D BCM5389_DEVICE_ID || is5397_98(dev)) + else if (dev->chip_id =3D=3D BCM5389_DEVICE_ID || is5397_98(dev) || + is63xx(dev)) offset =3D B53_ARL_SRCH_CTL_89; else offset =3D B53_ARL_SRCH_CTL; =20 - b53_read8(dev, B53_ARLIO_PAGE, offset, val); + if (is63xx(dev)) { + u16 val16; + + b53_read16(dev, B53_ARLIO_PAGE, offset, &val16); + *val =3D val16 & 0xff; + } else { + b53_read8(dev, B53_ARLIO_PAGE, offset, val); + } } =20 static void b53_write_arl_srch_ctl(struct b53_device *dev, u8 val) @@ -2072,12 +2080,16 @@ static void b53_write_arl_srch_ctl(struct b53_devic= e *dev, u8 val) =20 if (is5325(dev) || is5365(dev)) offset =3D B53_ARL_SRCH_CTL_25; - else if (dev->chip_id =3D=3D BCM5389_DEVICE_ID || is5397_98(dev)) + else if (dev->chip_id =3D=3D BCM5389_DEVICE_ID || is5397_98(dev) || + is63xx(dev)) offset =3D B53_ARL_SRCH_CTL_89; else offset =3D B53_ARL_SRCH_CTL; =20 - b53_write8(dev, B53_ARLIO_PAGE, offset, val); + if (is63xx(dev)) + b53_write16(dev, B53_ARLIO_PAGE, offset, val); + else + b53_write8(dev, B53_ARLIO_PAGE, offset, val); } =20 static int b53_arl_search_wait(struct b53_device *dev) @@ -2131,6 +2143,18 @@ static void b53_arl_search_read_89(struct b53_device= *dev, u8 idx, b53_arl_to_entry_89(ent, mac_vid, fwd_entry); } =20 +static void b53_arl_search_read_63xx(struct b53_device *dev, u8 idx, + struct b53_arl_entry *ent) +{ + u16 fwd_entry; + u64 mac_vid; + + b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_63XX, + &mac_vid); + b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_63XX, &fwd_entry); + b53_arl_search_to_entry_63xx(ent, mac_vid, fwd_entry); +} + static void b53_arl_search_read_95(struct b53_device *dev, u8 idx, struct b53_arl_entry *ent) { @@ -2730,6 +2754,12 @@ static const struct b53_arl_ops b53_arl_ops_89 =3D { .arl_search_read =3D b53_arl_search_read_89, }; =20 +static const struct b53_arl_ops b53_arl_ops_63xx =3D { + .arl_read_entry =3D b53_arl_read_entry_89, + .arl_write_entry =3D b53_arl_write_entry_89, + .arl_search_read =3D b53_arl_search_read_63xx, +}; + static const struct b53_arl_ops b53_arl_ops_95 =3D { .arl_read_entry =3D b53_arl_read_entry_95, .arl_write_entry =3D b53_arl_write_entry_95, @@ -2899,14 +2929,14 @@ static const struct b53_chip_data b53_switch_chips[= ] =3D { .dev_name =3D "BCM63xx", .vlans =3D 4096, .enabled_ports =3D 0, /* pdata must provide them */ - .arl_bins =3D 4, - .arl_buckets =3D 1024, + .arl_bins =3D 1, + .arl_buckets =3D 4096, .imp_port =3D 8, .vta_regs =3D B53_VTA_REGS_63XX, .duplex_reg =3D B53_DUPLEX_STAT_63XX, .jumbo_pm_reg =3D B53_JUMBO_PORT_MASK_63XX, .jumbo_size_reg =3D B53_JUMBO_MAX_SIZE_63XX, - .arl_ops =3D &b53_arl_ops_95, + .arl_ops =3D &b53_arl_ops_63xx, }, { .chip_id =3D BCM53010_DEVICE_ID, diff --git a/drivers/net/dsa/b53/b53_priv.h b/drivers/net/dsa/b53/b53_priv.h index d6d25bb3945b..2bfd0e7c95c9 100644 --- a/drivers/net/dsa/b53/b53_priv.h +++ b/drivers/net/dsa/b53/b53_priv.h @@ -409,6 +409,21 @@ static inline void b53_arl_from_entry_89(u64 *mac_vid,= u32 *fwd_entry, *fwd_entry |=3D ARLTBL_AGE_89; } =20 +static inline void b53_arl_search_to_entry_63xx(struct b53_arl_entry *ent, + u64 mac_vid, u16 fwd_entry) +{ + memset(ent, 0, sizeof(*ent)); + u64_to_ether_addr(mac_vid, ent->mac); + ent->vid =3D mac_vid >> ARLTBL_VID_S; + + ent->port =3D fwd_entry & ARL_SRST_PORT_ID_MASK_63XX; + ent->port >>=3D 1; + + ent->is_age =3D !!(fwd_entry & ARL_SRST_AGE_63XX); + ent->is_static =3D !!(fwd_entry & ARL_SRST_STATIC_63XX); + ent->is_valid =3D 1; +} + static inline void b53_arl_read_entry(struct b53_device *dev, struct b53_arl_entry *ent, u8 idx) { diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h index c303507d3034..69ebbec932f6 100644 --- a/drivers/net/dsa/b53/b53_regs.h +++ b/drivers/net/dsa/b53/b53_regs.h @@ -368,11 +368,13 @@ #define B53_ARL_SRCH_ADDR_25 0x22 #define B53_ARL_SRCH_ADDR_65 0x24 #define B53_ARL_SRCH_ADDR_89 0x31 +#define B53_ARL_SRCH_ADDR_63XX 0x32 #define ARL_ADDR_MASK GENMASK(14, 0) =20 /* ARL Search MAC/VID Result (64 bit) */ #define B53_ARL_SRCH_RSTL_0_MACVID 0x60 #define B53_ARL_SRCH_RSLT_MACVID_89 0x33 +#define B53_ARL_SRCH_RSLT_MACVID_63XX 0x34 =20 /* Single register search result on 5325 */ #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 @@ -388,6 +390,13 @@ #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0= x10)) #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) =20 +/* 63XX ARL Search Data Result (16 bit) */ +#define B53_ARL_SRCH_RSLT_63XX 0x3c +#define ARL_SRST_PORT_ID_MASK_63XX GENMASK(9, 1) +#define ARL_SRST_TC_MASK_63XX GENMASK(13, 11) +#define ARL_SRST_AGE_63XX BIT(14) +#define ARL_SRST_STATIC_63XX BIT(15) + /************************************************************************* * IEEE 802.1X Registers *************************************************************************/ --=20 2.43.0