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Fri, 07 Nov 2025 12:53:43 -0800 (PST) From: David Lechner Date: Fri, 07 Nov 2025 14:52:47 -0600 Subject: [PATCH v2 1/6] spi: dt-bindings: Add spi-data-buses property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251107-spi-add-multi-bus-support-v2-1-8a92693314d9@baylibre.com> References: <20251107-spi-add-multi-bus-support-v2-0-8a92693314d9@baylibre.com> In-Reply-To: <20251107-spi-add-multi-bus-support-v2-0-8a92693314d9@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2076; 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Signed-off-by: David Lechner --- v2 changes: * Renamed property from spi-buses to spi-data-buses to make it clear that we are only talking about the SDI/SDO lines and not the entire SPI bus (SCK, CS, etc). * Fixed prefix order in subject. This patch has been seen before in a different series from Sean [1]. [1]: https://lore.kernel.org/linux-spi/20250616220054.3968946-2-sean.anders= on@linux.dev/ Changes: * Added maxItems. (8 is the most I've seen so far on an ADC) * Tweaked the description a bit. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 12 ++++++++= ++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 8b6e8fc009dbdc80978f3afef84ddc688ade4348..6fe739eaf09876b9c5d8902f792= ca02181d7266f 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -89,6 +89,18 @@ properties: description: Delay, in microseconds, after a write transfer. =20 + spi-data-buses: + description: + Array of data bus numbers that describes which SPI data buses of the + controller are connected to the peripheral. This only applies to + peripherals connected to specialized SPI controllers that have multi= ple + SPI data buses (a set of independent SDI/SDO lines each with its own + serializer) on a single controller. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + default: [0] + stacked-memories: description: Several SPI memories can be wired in stacked mode. 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Fri, 07 Nov 2025 12:53:44 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:7bb8:950b:327d:4ba4]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-656c57eae5esm2915601eaf.16.2025.11.07.12.53.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 12:53:44 -0800 (PST) From: David Lechner Date: Fri, 07 Nov 2025 14:52:48 -0600 Subject: [PATCH v2 2/6] spi: Support multi-bus controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251107-spi-add-multi-bus-support-v2-2-8a92693314d9@baylibre.com> References: <20251107-spi-add-multi-bus-support-v2-0-8a92693314d9@baylibre.com> In-Reply-To: <20251107-spi-add-multi-bus-support-v2-0-8a92693314d9@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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(A data bus in this context means lines connected to a serializer, so a controller with two data buses would have two serializers in a single controller). This is common in the type of controller that can be used with parallel flash memories, but can be used for general purpose SPI as well. To indicate support, a controller just needs to set ctlr->num_data_bus to something greater than 1. Peripherals indicate which bus they are connected to via device tree (ACPI support can be added if needed). Acked-by: Nuno S=C3=A1 Acked-by: Marcelo Schmitt Signed-off-by: David Lechner --- This patch has been seen in a different series [1] by Sean before: [1]: https://lore.kernel.org/linux-spi/20250616220054.3968946-4-sean.anders= on@linux.dev/ Changes: * Use u8 array instead of bitfield so that the order of the mapping is preserved. (Now looks very much like chip select mapping.) * Added doc strings for added fields. * Tweaked the comments. --- drivers/spi/spi.c | 28 +++++++++++++++++++++++++++- include/linux/spi/spi.h | 17 +++++++++++++++++ 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 8588e8562220ff5f77977a91b869e220b400c0b2..1cc193ee81120180264047039ef= 035a958481ede 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2354,7 +2354,7 @@ static void of_spi_parse_dt_cs_delay(struct device_no= de *nc, static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device = *spi, struct device_node *nc) { - u32 value, cs[SPI_DEVICE_CS_CNT_MAX]; + u32 value, buses[SPI_DEVICE_DATA_BUS_CNT_MAX], cs[SPI_DEVICE_CS_CNT_MAX]; int rc, idx; =20 /* Mode (clock phase/polarity/etc.) */ @@ -2446,6 +2446,31 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, for (idx =3D 0; idx < rc; idx++) spi_set_chipselect(spi, idx, cs[idx]); =20 + rc =3D of_property_read_variable_u32_array(nc, "spi-data-buses", buses, 1, + ARRAY_SIZE(buses)); + if (rc < 0 && rc !=3D -EINVAL) { + dev_err(&ctlr->dev, "%pOF has invalid 'spi-data-buses' property (%d)\n", + nc, rc); + return rc; + } + + if (rc =3D=3D -EINVAL) { + /* Default when property is omitted. */ + spi->num_data_bus =3D 1; + } else { + for (idx =3D 0; idx < rc; idx++) { + if (buses[idx] >=3D ctlr->num_data_bus) { + dev_err(&ctlr->dev, + "%pOF has out of range 'spi-data-buses' property (%d/%d)\n", + nc, buses[idx], ctlr->num_data_bus); + return -EINVAL; + } + spi->data_bus[idx] =3D buses[idx]; + } + + spi->num_data_bus =3D rc; + } + /* * By default spi->chip_select[0] will hold the physical CS number, * so set bit 0 in spi->cs_index_mask. @@ -3064,6 +3089,7 @@ struct spi_controller *__spi_alloc_controller(struct = device *dev, mutex_init(&ctlr->add_lock); ctlr->bus_num =3D -1; ctlr->num_chipselect =3D 1; + ctlr->num_data_bus =3D 1; ctlr->target =3D target; if (IS_ENABLED(CONFIG_SPI_SLAVE) && target) ctlr->dev.class =3D &spi_target_class; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index cb2c2df3108999a73b67ef4a7b0d2cb07adfc669..c314194d4e7e2b396795ece10e1= 42118ca05f4eb 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -23,6 +23,9 @@ /* Max no. of CS supported per spi device */ #define SPI_DEVICE_CS_CNT_MAX 4 =20 +/* Max no. of data buses supported per spi device */ +#define SPI_DEVICE_DATA_BUS_CNT_MAX 8 + struct dma_chan; struct software_node; struct ptp_system_timestamp; @@ -171,6 +174,9 @@ extern void spi_transfer_cs_change_delay_exec(struct sp= i_message *msg, * @chip_select: Array of physical chipselect, spi->chipselect[i] gives * the corresponding physical CS for logical CS i. * @num_chipselect: Number of physical chipselects used. + * @data_bus: Array of physical data buses. This is only used with special= ized + * controllers that support multiple data buses. + * @num_data_bus: Number of physical data buses used. * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect = array * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect li= nes * (optional, NULL when not using a GPIO line) @@ -231,6 +237,8 @@ struct spi_device { =20 u8 chip_select[SPI_DEVICE_CS_CNT_MAX]; u8 num_chipselect; + u8 data_bus[SPI_DEVICE_DATA_BUS_CNT_MAX]; + u8 num_data_bus; =20 /* * Bit mask of the chipselect(s) that the driver need to use from @@ -401,6 +409,7 @@ extern struct spi_device *spi_new_ancillary_device(stru= ct spi_device *spi, u8 ch * SPI targets, and are numbered from zero to num_chipselects. * each target has a chipselect signal, but it's common that not * every chipselect is connected to a target. + * @num_data_bus: Number of data buses supported by this controller. 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This requires both the peripheral and the controller to have multiple serializers connected to separate data buses. It could also be used with a single controller and multiple peripherals that are functioning as a single logical device (similar to parallel memories). The possible values for this field have the following semantics: - SPI_MULTI_BUS_MODE_SINGLE: Only use the first bus. This means that it it is operating just like a conventional SPI bus. It is the default value so that existing drivers do not need to be modified. Example: tx_buf[0] =3D 0x88; struct spi_transfer xfer =3D { .tx_buf =3D tx_buf, .len =3D 1, }; spi_sync_transfer(spi, &xfer, 1); controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0 - SPI_MULTI_BUS_MODE_MIRROR: Send a single data word over all of the buses at the same time. This only makes sense for writes and not for reads. Example: tx_buf[0] =3D 0x88; struct spi_transfer xfer =3D { .tx_buf =3D tx_buf, .len =3D 1, .multi_bus_mode =3D SPI_MULTI_BUS_MODE_MIRROR, }; spi_sync_transfer(spi, &xfer, 1); controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0 SDO 1 0-0-0-1-0-0-0-1 SDI 1 - SPI_MULTI_BUS_MODE_STRIPE: Send or receive two different data words at the same time, one on each bus. Example: struct spi_transfer xfer =3D { .rx_buf =3D rx_buf, .len =3D 2, /* must be multiple of number of buses */ .multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE, }; spi_sync_transfer(spi, &xfer, 1); controller < data bits < peripheral ---------- ---------------- ---------- SDI 0 0-0-0-1-0-0-0-1 SDO 0 SDI 1 1-0-0-0-1-0-0-0 SDO 1 After the transfer, rx_buf[0] =3D=3D 0x11 (word from SDO 0) and rx_buf[1] =3D=3D 0x88 (word from SDO 1). If the transfer was longer, the data would continue in an alternating fashion. Acked-by: Nuno S=C3=A1 Acked-by: Marcelo Schmitt Signed-off-by: David Lechner --- include/linux/spi/spi.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index c314194d4e7e2b396795ece10e142118ca05f4eb..7d22ef5077d1229cac2574831f8= 0092c591b972f 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -976,6 +976,8 @@ struct spi_res { * (SPI_NBITS_SINGLE) is used. * @rx_nbits: number of bits used for reading. If 0 the default * (SPI_NBITS_SINGLE) is used. + * @multi_bus_mode: How to serialize data on multiple buses. One of the + * SPI_MULTI_BUS_MODE_* values. * @len: size of rx and tx buffers (in bytes) * @speed_hz: Select a speed other than the device default for this * transfer. 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a=openpgp-sha256; l=11262; i=dlechner@baylibre.com; h=from:subject:message-id; bh=tDgY9PgjE3rE33iaQr1P6OAzhqfnlIin3aQjjP7cTsw=; b=owEBbAGT/pANAwAKAcLMIAH/AY/AAcsmYgBpDlxAFRFTT9BeZuPCT/R7t64DTDDepkVGvPhGA ownsyE6vfWJATIEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaQ5cQAAKCRDCzCAB/wGP wDWHB/QJbbjOIG/SDsXPlJGmah/kDYwKw8YWdx9ahTjab4U87wdF1ymGKiEBWyO3pzAl4HpVelT pXilGpHmXTH17QuhcaoN3chgMDltrI3ZE3qTO2RMUM5INRLGVo7PkSn0vYofyaiWDcN0nXIWxZ3 r3NNH+B5Tj7rbpAZAYnNR5Ku2tnNghXS7N9HRCnnkNq6gTFY8lYy6xMQjV0cNkrB+jShE0jgqlZ zf7NI1Aj8fEhZVY7iNxRAw1mowSyfb+k8D0N6P2pv+7t0S2Cqr+Hps5QnSxK5AJU5LZKOITGFHy w3bAmhKjtmnnhKKDVxHSmAedPpvvvTCVOE8TBEGNCYrOv1Y= X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add support for SPI_MULTI_BUS_MODE_STRIPE to the AXI SPI engine driver. The v2.0.0 version of the AXI SPI Engine IP core supports multiple buses. This can be used with SPI_MULTI_BUS_MODE_STRIPE to support reading from simultaneous sampling ADCs that have a separate SDO line for each analog channel. This allows reading all channels at the same time to increase throughput. Signed-off-by: David Lechner Reviewed-by: Marcelo Schmitt --- v2 changes: * Fixed off-by-one in SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK --- drivers/spi/spi-axi-spi-engine.c | 128 +++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 124 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-eng= ine.c index e06f412190fd243161a0b3df992f26157531f6a1..c9d146e978b89abb8273900722a= e2cfafdd6325f 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -23,6 +23,9 @@ #include #include =20 +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C +#define SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK(23, 16) +#define SPI_ENGINE_REG_DATA_WIDTH_MASK GENMASK(15, 0) #define SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH 0x10 #define SPI_ENGINE_REG_RESET 0x40 =20 @@ -75,6 +78,8 @@ #define SPI_ENGINE_CMD_REG_CLK_DIV 0x0 #define SPI_ENGINE_CMD_REG_CONFIG 0x1 #define SPI_ENGINE_CMD_REG_XFER_BITS 0x2 +#define SPI_ENGINE_CMD_REG_SDI_MASK 0x3 +#define SPI_ENGINE_CMD_REG_SDO_MASK 0x4 =20 #define SPI_ENGINE_MISC_SYNC 0x0 #define SPI_ENGINE_MISC_SLEEP 0x1 @@ -105,6 +110,10 @@ #define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16 #define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16 =20 +/* Extending SPI_MULTI_BUS_MODE values for optimizing messages. */ +#define SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN -1 +#define SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING -2 + struct spi_engine_program { unsigned int length; uint16_t instructions[] __counted_by(length); @@ -142,6 +151,9 @@ struct spi_engine_offload { unsigned long flags; unsigned int offload_num; unsigned int spi_mode_config; + unsigned int multi_bus_mode; + u8 primary_bus_mask; + u8 all_bus_mask; u8 bits_per_word; }; =20 @@ -165,6 +177,22 @@ struct spi_engine { bool offload_requires_sync; }; =20 +static u8 spi_engine_primary_bus_flag(struct spi_device *spi) +{ + return BIT(spi->data_bus[0]); +} + +static u8 spi_engine_all_bus_flags(struct spi_device *spi) +{ + u8 flags =3D 0; + int i; + + for (i =3D 0; i < spi->num_data_bus; i++) + flags |=3D BIT(spi->data_bus[i]); + + return flags; +} + static void spi_engine_program_add_cmd(struct spi_engine_program *p, bool dry, uint16_t cmd) { @@ -193,7 +221,7 @@ static unsigned int spi_engine_get_config(struct spi_de= vice *spi) } =20 static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry, - struct spi_transfer *xfer) + struct spi_transfer *xfer, u32 num_lanes) { unsigned int len; =20 @@ -204,6 +232,9 @@ static void spi_engine_gen_xfer(struct spi_engine_progr= am *p, bool dry, else len =3D xfer->len / 4; =20 + if (xfer->multi_bus_mode =3D=3D SPI_MULTI_BUS_MODE_STRIPE) + len /=3D num_lanes; + while (len) { unsigned int n =3D min(len, 256U); unsigned int flags =3D 0; @@ -269,6 +300,7 @@ static int spi_engine_precompile_message(struct spi_mes= sage *msg) { unsigned int clk_div, max_hz =3D msg->spi->controller->max_speed_hz; struct spi_transfer *xfer; + int multi_bus_mode =3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN; u8 min_bits_per_word =3D U8_MAX; u8 max_bits_per_word =3D 0; =20 @@ -284,6 +316,24 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) min_bits_per_word =3D min(min_bits_per_word, xfer->bits_per_word); max_bits_per_word =3D max(max_bits_per_word, xfer->bits_per_word); } + + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + switch (xfer->multi_bus_mode) { + case SPI_MULTI_BUS_MODE_SINGLE: + case SPI_MULTI_BUS_MODE_STRIPE: + break; + default: + /* Other modes, like mirror not supported */ + return -EINVAL; + } + + /* If all xfers have the same multi-bus mode, we can optimize. */ + if (multi_bus_mode =3D=3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN) + multi_bus_mode =3D xfer->multi_bus_mode; + else if (multi_bus_mode !=3D xfer->multi_bus_mode) + multi_bus_mode =3D SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING; + } } =20 /* @@ -297,6 +347,10 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) priv->bits_per_word =3D min_bits_per_word; else priv->bits_per_word =3D 0; + + priv->multi_bus_mode =3D multi_bus_mode; + priv->primary_bus_mask =3D spi_engine_primary_bus_flag(msg->spi); + priv->all_bus_mask =3D spi_engine_all_bus_flags(msg->spi); } =20 return 0; @@ -310,6 +364,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, struct spi_engine_offload *priv; struct spi_transfer *xfer; int clk_div, new_clk_div, inst_ns; + int prev_multi_bus_mode =3D SPI_MULTI_BUS_MODE_SINGLE; bool keep_cs =3D false; u8 bits_per_word =3D 0; =20 @@ -334,6 +389,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, * in the same way. */ bits_per_word =3D priv->bits_per_word; + prev_multi_bus_mode =3D priv->multi_bus_mode; } else { spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG, @@ -344,6 +400,24 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, spi_engine_gen_cs(p, dry, spi, !xfer->cs_off); =20 list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + if (xfer->multi_bus_mode !=3D prev_multi_bus_mode) { + u8 bus_flags =3D spi_engine_primary_bus_flag(spi); + + if (xfer->multi_bus_mode =3D=3D SPI_MULTI_BUS_MODE_STRIPE) + bus_flags =3D spi_engine_all_bus_flags(spi); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + bus_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + bus_flags)); + } + prev_multi_bus_mode =3D xfer->multi_bus_mode; + } + new_clk_div =3D host->max_speed_hz / xfer->effective_speed_hz; if (new_clk_div !=3D clk_div) { clk_div =3D new_clk_div; @@ -360,7 +434,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, bits_per_word)); } =20 - spi_engine_gen_xfer(p, dry, xfer); + spi_engine_gen_xfer(p, dry, xfer, spi->num_data_bus); spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer), inst_ns, xfer->effective_speed_hz); =20 @@ -394,6 +468,17 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, if (clk_div !=3D 1) spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, 0)); + + /* Restore single bus mode unless offload disable will restore it later. = */ + if (prev_multi_bus_mode =3D=3D SPI_MULTI_BUS_MODE_STRIPE && + (!msg->offload || priv->multi_bus_mode !=3D SPI_MULTI_BUS_MODE_STRIPE= )) { + u8 bus_flags =3D spi_engine_primary_bus_flag(spi); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, bus_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, bus_flags)); + } } =20 static void spi_engine_xfer_next(struct spi_message *msg, @@ -799,6 +884,17 @@ static int spi_engine_setup(struct spi_device *device) writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (host->num_data_bus > 1) { + u8 bus_flags =3D spi_engine_primary_bus_flag(device); + + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + bus_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + bus_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + /* * In addition to setting the flags, we have to do a CS assert command * to make the new setting actually take effect. @@ -902,6 +998,15 @@ static int spi_engine_trigger_enable(struct spi_offloa= d *offload) priv->bits_per_word), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (priv->multi_bus_mode =3D=3D SPI_MULTI_BUS_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->all_bus_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->all_bus_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + writel_relaxed(SPI_ENGINE_CMD_SYNC(1), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 @@ -929,6 +1034,16 @@ static void spi_engine_trigger_disable(struct spi_off= load *offload) reg &=3D ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE; writel_relaxed(reg, spi_engine->base + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num)); + + /* Restore single-bus mode. */ + if (priv->multi_bus_mode =3D=3D SPI_MULTI_BUS_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->primary_bus_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->primary_bus_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } } =20 static struct dma_chan @@ -973,7 +1088,7 @@ static int spi_engine_probe(struct platform_device *pd= ev) { struct spi_engine *spi_engine; struct spi_controller *host; - unsigned int version; + unsigned int version, data_width_reg_val; int irq, ret; =20 irq =3D platform_get_irq(pdev, 0); @@ -1042,7 +1157,7 @@ static int spi_engine_probe(struct platform_device *p= dev) return PTR_ERR(spi_engine->base); =20 version =3D readl(spi_engine->base + ADI_AXI_REG_VERSION); - if (ADI_AXI_PCORE_VER_MAJOR(version) !=3D 1) { + if (ADI_AXI_PCORE_VER_MAJOR(version) > 2) { dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%u\n", ADI_AXI_PCORE_VER_MAJOR(version), ADI_AXI_PCORE_VER_MINOR(version), @@ -1050,6 +1165,8 @@ static int spi_engine_probe(struct platform_device *p= dev) return -ENODEV; } =20 + data_width_reg_val =3D readl(spi_engine->base + SPI_ENGINE_REG_DATA_WIDTH= ); + if (adi_axi_pcore_ver_gteq(version, 1, 1)) { unsigned int sizes =3D readl(spi_engine->base + SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH); @@ -1097,6 +1214,9 @@ static int spi_engine_probe(struct platform_device *p= dev) } if (adi_axi_pcore_ver_gteq(version, 1, 3)) host->mode_bits |=3D SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; 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These chips are simultaneous sampling ADCs and have one SDO line per channel, either 2 or 4 total depending on the part number. Signed-off-by: David Lechner --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 22 ++++++++++++++++++= ++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index b91bfb16ed6bc6c605880f81050250d1ed9c307a..9ef46cdb047d45d088e0fbc345f= 58c5b09083385 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -62,6 +62,10 @@ properties: spi-cpol: true spi-cpha: true =20 + spi-data-buses: + minItems: 1 + maxItems: 4 + vcc-supply: description: A 3V to 3.6V supply that powers the chip. =20 @@ -245,6 +249,22 @@ allOf: patternProperties: "^channel@[0-3]$": false =20 + # 2-channel chip can only have up to 2 buses + - if: + properties: + compatible: + enum: + - adi,ad7380 + - adi,ad7381 + - adi,ad7386 + - adi,ad7387 + - adi,ad7388 + - adi,ad7389 + then: + properties: + spi-data-buses: + maxItems: 2 + examples: - | #include @@ -260,6 +280,7 @@ examples: spi-cpol; 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The AD7380 family of ADCs have multiple SDO lines on the chip that can be used to read each channel on a separate SPI bus. If wired up to a SPI controller that supports it, the driver will now take advantage of this feature. This allows reaching the maximum sample rate advertised in the datasheet when combined with SPI offloading. Reviewed-by: Nuno S=C3=A1 Signed-off-by: David Lechner --- v2 changes: * Move st->seq_xfer[3].multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE; to probe(). --- drivers/iio/adc/ad7380.c | 42 +++++++++++++++++++++++++++++------------- 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index bfd908deefc0f40b42bd8a44bfce7a2510b2fdf1..8891c31e61714b00fb01571f7dd= d163cc948a8fb 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -77,8 +77,7 @@ #define AD7380_CONFIG1_REFSEL BIT(1) #define AD7380_CONFIG1_PMODE BIT(0) =20 -#define AD7380_CONFIG2_SDO2 GENMASK(9, 8) -#define AD7380_CONFIG2_SDO BIT(8) +#define AD7380_CONFIG2_SDO GENMASK(9, 8) #define AD7380_CONFIG2_RESET GENMASK(7, 0) =20 #define AD7380_CONFIG2_RESET_SOFT 0x3C @@ -92,11 +91,6 @@ #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ #define T_POWERUP_US 5000 /* Power up */ =20 -/* - * AD738x support several SDO lines to increase throughput, but driver cur= rently - * supports only 1 SDO line (standard SPI transaction) - */ -#define AD7380_NUM_SDO_LINES 1 #define AD7380_DEFAULT_GAIN_MILLI 1000 =20 /* @@ -1084,7 +1078,7 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) if (oversampling_ratio > 1) xfer.delay.value =3D T_CONVERT_0_NS + T_CONVERT_X_NS * (oversampling_ratio - 1) * - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; + st->chip_info->num_simult_channels / st->spi->num_data_bus; =20 return spi_sync_transfer(st->spi, &xfer, 1); } @@ -1113,7 +1107,7 @@ static int ad7380_update_xfers(struct ad7380_state *s= t, if (oversampling_ratio > 1) t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * (oversampling_ratio - 1) * - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; + st->chip_info->num_simult_channels / st->spi->num_data_bus; =20 if (st->seq) { xfer[0].delay.value =3D xfer[1].delay.value =3D t_convert; @@ -1198,6 +1192,8 @@ static int ad7380_init_offload_msg(struct ad7380_stat= e *st, xfer->bits_per_word =3D scan_type->realbits; xfer->offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; xfer->len =3D AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_cha= nnels; + if (st->spi->num_data_bus > 1) + xfer->multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); st->offload_msg.offload =3D st->offload; @@ -1793,6 +1789,7 @@ static const struct iio_info ad7380_info =3D { =20 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) { + u32 sdo; int ret; =20 /* perform hard reset */ @@ -1815,11 +1812,24 @@ static int ad7380_init(struct ad7380_state *st, boo= l external_ref_en) st->ch =3D 0; st->seq =3D false; =20 - /* SPI 1-wire mode */ + /* SDO field has an irregular mapping. */ + switch (st->spi->num_data_bus) { + case 1: + sdo =3D 1; + break; + case 2: + sdo =3D 0; + break; + case 4: + sdo =3D 2; + break; + default: + return -EINVAL; + } + return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, AD7380_CONFIG2_SDO, - FIELD_PREP(AD7380_CONFIG2_SDO, - AD7380_NUM_SDO_LINES)); + FIELD_PREP(AD7380_CONFIG2_SDO, sdo)); } =20 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev, @@ -1842,7 +1852,7 @@ static int ad7380_probe_spi_offload(struct iio_dev *i= ndio_dev, "failed to get offload trigger\n"); =20 sample_rate =3D st->chip_info->max_conversion_rate_hz * - AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels; + spi->num_data_bus / st->chip_info->num_simult_channels; =20 st->sample_freq_range[0] =3D 1; /* min */ st->sample_freq_range[1] =3D 1; /* step */ @@ -2010,6 +2020,8 @@ static int ad7380_probe(struct spi_device *spi) st->normal_xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs-= >t_csh_ns; st->normal_xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; st->normal_xfer[1].rx_buf =3D st->scan_data; + if (spi->num_data_bus > 1) + st->normal_xfer[1].multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, ARRAY_SIZE(st->normal_xfer)); @@ -2031,6 +2043,10 @@ static int ad7380_probe(struct spi_device *spi) st->seq_xfer[2].cs_change =3D 1; st->seq_xfer[2].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; st->seq_xfer[2].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + if (spi->num_data_bus > 1) { + st->seq_xfer[2].multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE; + st->seq_xfer[3].multi_bus_mode =3D SPI_MULTI_BUS_MODE_STRIPE; + } =20 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, ARRAY_SIZE(st->seq_xfer)); --=20 2.43.0