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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6411f713959sm4444376a12.5.2025.11.07.08.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 08:08:50 -0800 (PST) From: Luca Weiss Date: Fri, 07 Nov 2025 17:08:47 +0100 Subject: [PATCH 1/5] dt-bindings: interconnect: qcom,sm6350-rpmh: Add clocks for QoS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251107-sm6350-icc-qos-v1-1-8275e5fc3f61@fairphone.com> References: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> In-Reply-To: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762531729; l=3518; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=wCfL/0TbR2D1La8wfkO0vzsLgEQ1Zd5Y2m8FV9wi1Gg=; b=XFhe9WKdgQrhgwCeP/Zu9aHiY8hnx5TxEMqejAH60sY7NNNSJ7zYWpPjHr9tJL6L5Vxd/IUll 0+5xg/BwfpFCCSx7nx2Yh4b+QYUkjuUBCgHp1iuRuFkX3leuHhJRZFG X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the clocks for some interconnects to the bindings that are required to set up the QoS correctly. Update one of the examples to aggre2_noc to have an example with clocks. Also while we're at it, remove #interconnect-cells: true as that's already provided from qcom,rpmh-common.yaml. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski --- .../bindings/interconnect/qcom,sm6350-rpmh.yaml | 65 ++++++++++++++++++= ---- 1 file changed, 54 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpm= h.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.ya= ml index 49eb156b08e0..2dc16e4293a9 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml @@ -12,9 +12,6 @@ maintainers: description: Qualcomm RPMh-based interconnect provider on SM6350. =20 -allOf: - - $ref: qcom,rpmh-common.yaml# - properties: compatible: enum: @@ -30,7 +27,9 @@ properties: reg: maxItems: 1 =20 - '#interconnect-cells': true + clocks: + minItems: 1 + maxItems: 2 =20 patternProperties: '^interconnect-[a-z0-9\-]+$': @@ -46,8 +45,6 @@ patternProperties: - qcom,sm6350-clk-virt - qcom,sm6350-compute-noc =20 - '#interconnect-cells': true - required: - compatible =20 @@ -57,10 +54,54 @@ required: - compatible - reg =20 +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre1-noc + - qcom,sm6350-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false =20 examples: - | + #include + #include + config_noc: interconnect@1500000 { compatible =3D "qcom,sm6350-config-noc"; reg =3D <0x01500000 0x28000>; @@ -68,14 +109,16 @@ examples: qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 - system_noc: interconnect@1620000 { - compatible =3D "qcom,sm6350-system-noc"; - reg =3D <0x01620000 0x17080>; + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sm6350-aggre2-noc"; + reg =3D <0x01700000 0x1f880>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; =20 - clk_virt: interconnect-clk-virt { - compatible =3D "qcom,sm6350-clk-virt"; + compute_noc: interconnect-compute-noc { + compatible =3D "qcom,sm6350-compute-noc"; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; --=20 2.51.2 From nobody Fri Dec 19 21:53:41 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 452032F549F for ; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6411f713959sm4444376a12.5.2025.11.07.08.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 08:08:51 -0800 (PST) From: Luca Weiss Date: Fri, 07 Nov 2025 17:08:48 +0100 Subject: [PATCH 2/5] interconnect: qcom: icc-rpmh: Get parent's regmap for nested NoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251107-sm6350-icc-qos-v1-2-8275e5fc3f61@fairphone.com> References: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> In-Reply-To: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762531729; l=1554; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=FrKylvjtIbykfg6BNRKjScYknFwVxGFQEfuD+JLYCCg=; b=nTRGQyYmySEkpmasdBUmEaPB51ISRGLTYkLSIUcHDR8tbweZYP3kljRlJhHKqSeem9gQeqLRC DHVQ5/NTu3BDPGZMEfeU2PpcIDxP74CA8UJEXfBUhruv7IqiClWTtIv X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Since commit 57eb14779dfd ("interconnect: qcom: icc-rpmh: Support child NoC device probe") the icc-rpmh driver supports initializing child NoCs, but those child NoCs also need to be able to get the parent's regmap in order to enable QoS. Change the driver to support that and support programming QoS register. Signed-off-by: Luca Weiss --- drivers/interconnect/qcom/icc-rpmh.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qc= om/icc-rpmh.c index f90c29111f48..2103185a44a5 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -308,7 +308,16 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; =20 - base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + /* Try parent's regmap */ + qp->regmap =3D dev_get_regmap(dev->parent, NULL); + if (qp->regmap) + goto regmap_done; + goto skip_qos_config; + } + + base =3D devm_ioremap_resource(dev, res); if (IS_ERR(base)) goto skip_qos_config; =20 @@ -318,6 +327,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) goto skip_qos_config; } =20 +regmap_done: qp->num_clks =3D devm_clk_bulk_get_all(qp->dev, &qp->clks); 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6411f713959sm4444376a12.5.2025.11.07.08.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 08:08:51 -0800 (PST) From: Luca Weiss Date: Fri, 07 Nov 2025 17:08:49 +0100 Subject: [PATCH 3/5] interconnect: qcom: sm6350: Remove empty BCM arrays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251107-sm6350-icc-qos-v1-3-8275e5fc3f61@fairphone.com> References: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> In-Reply-To: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762531729; l=1767; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=yWJZX5pTtTBbyY/nQH9wW9jtpKcujH2KDm9MV6WcgRE=; b=4zcbiYwJD4C2WWOQVJKpY7aqjPmWPTB217iJUU4vwEVsg9ocL9+9WFfA/TmTJ8b8SF0q7EKHn 2vYniMUYxWGCIsvid0N4wRR0KUrob3/8yWJHfXYAAoNxwUcqme5i21c X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Clean up the code by removing empty BCM arrays to save some lines. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm6350.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom= /sm6350.c index 99c435a5968f..246549cb761e 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1526,9 +1526,6 @@ static const struct qcom_icc_desc sm6350_config_noc = =3D { .num_bcms =3D ARRAY_SIZE(config_noc_bcms), }; =20 -static struct qcom_icc_bcm * const dc_noc_bcms[] =3D { -}; - static struct qcom_icc_node * const dc_noc_nodes[] =3D { [MASTER_CNOC_DC_NOC] =3D &qhm_cnoc_dc_noc, [SLAVE_GEM_NOC_CFG] =3D &qhs_gemnoc, @@ -1538,8 +1535,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { static const struct qcom_icc_desc sm6350_dc_noc =3D { .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), - .bcms =3D dc_noc_bcms, - .num_bcms =3D ARRAY_SIZE(dc_noc_bcms), }; =20 static struct qcom_icc_bcm * const gem_noc_bcms[] =3D { @@ -1600,9 +1595,6 @@ static const struct qcom_icc_desc sm6350_mmss_noc =3D= { .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), }; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6411f713959sm4444376a12.5.2025.11.07.08.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 08:08:52 -0800 (PST) From: Luca Weiss Date: Fri, 07 Nov 2025 17:08:50 +0100 Subject: [PATCH 4/5] interconnect: qcom: sm6350: enable QoS configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251107-sm6350-icc-qos-v1-4-8275e5fc3f61@fairphone.com> References: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> In-Reply-To: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762531729; l=15099; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=PpqpMgS1hpomQ6JwbVbN+tPs9Mxa/GpmHN/usrG63lM=; b=PUTrVMKteKXqivWAazJTOUHP/hxxIYZVjk8dt+qH7Y1W2PXkDO1b5Yc/HmN3pGA3Jnw7SuTP7 Qx2gW13BpvJDZ3kw0jQD8BOWLf0M5kRstaa7X2RyTWtyEMaKdvaZAl0 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Enable QoS configuration for master ports with predefined values for priority and urgency forwarding. While this does require some "clocks" to be specified in devicetree to work correctly, thanks to ".qos_requires_clocks =3D true," this is backwards compatible with old DT as QoS programming will be skipped for aggre1_noc and aggre2_noc when clocks are not provided. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm6350.c | 288 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 288 insertions(+) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom= /sm6350.c index 246549cb761e..d96bec1cbb26 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -150,26 +150,50 @@ static struct qcom_icc_node qhm_a1noc_cfg =3D { .link_nodes =3D { &srvc_aggre1_noc }, }; =20 +static struct qcom_icc_qosbox qhm_qup_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qhm_qup_0 =3D { .name =3D "qhm_qup_0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qup_0_qos, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_emmc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x7000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_emmc =3D { .name =3D "xm_emmc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_emmc_qos, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_ufs_mem_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x8000 }, + .prio =3D 4, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_ufs_mem_qos, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -182,58 +206,113 @@ static struct qcom_icc_node qhm_a2noc_cfg =3D { .link_nodes =3D { &srvc_aggre2_noc }, }; =20 +static struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qdss_bam_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox qhm_qup_1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; static struct qcom_icc_node qhm_qup_1 =3D { .name =3D "qhm_qup_1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qup_1_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox qxm_crypto_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x6000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_crypto_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox qxm_ipa_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x7000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_ipa_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_qdss_etr_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_qdss_etr_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_sdc2_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_sdc2_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; =20 +static struct qcom_icc_qosbox xm_usb3_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_usb3_0_qos, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -278,18 +357,34 @@ static struct qcom_icc_node qup1_core_master =3D { .link_nodes =3D { &qup1_core_slave }, }; =20 +static struct qcom_icc_qosbox qnm_npu_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0xf000, 0x11000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_npu_qos, .num_links =3D 1, .link_nodes =3D { &qns_cdsp_gemnoc }, }; =20 +static struct qcom_icc_qosbox qxm_npu_dsp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qxm_npu_dsp =3D { .name =3D "qxm_npu_dsp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_npu_dsp_qos, .num_links =3D 1, .link_nodes =3D { &qns_cdsp_gemnoc }, }; @@ -401,19 +496,35 @@ static struct qcom_icc_node qhm_cnoc_dc_noc =3D { &qhs_gemnoc }, }; =20 +static struct qcom_icc_qosbox acm_apps_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x2f100, 0x2f000 }, + .prio =3D 0, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &acm_apps_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, }; =20 +static struct qcom_icc_qosbox acm_sys_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x35000 }, + .prio =3D 6, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &acm_sys_tcu_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, @@ -429,53 +540,101 @@ static struct qcom_icc_node qhm_gemnoc_cfg =3D { &qhs_mdsp_ms_mpu_cfg }, }; =20 +static struct qcom_icc_qosbox qnm_cmpnoc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x2e000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_cmpnoc_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, }; =20 +static struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x30000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_hf_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, }; =20 +static struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x34000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_sf_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, }; =20 +static struct qcom_icc_qosbox qnm_snoc_gc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x32000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qnm_snoc_gc_qos, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; =20 +static struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x31000 }, + .prio =3D 0, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &qnm_snoc_sf_qos, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; =20 +static struct qcom_icc_qosbox qxm_gpu_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x33000, 0x33080 }, + .prio =3D 0, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qxm_gpu_qos, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_gem_noc_snoc }, @@ -497,50 +656,98 @@ static struct qcom_icc_node qhm_mnoc_cfg =3D { .link_nodes =3D { &srvc_mnoc }, }; =20 +static struct qcom_icc_qosbox qnm_video0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .prio =3D 2, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_video0_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; =20 +static struct qcom_icc_qosbox qnm_video_cvp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 5, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qnm_video_cvp_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; =20 +static struct qcom_icc_qosbox qxm_camnoc_hf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0xa000, 0xb000 }, + .prio =3D 3, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qxm_camnoc_hf =3D { .name =3D "qxm_camnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qxm_camnoc_hf_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; =20 +static struct qcom_icc_qosbox qxm_camnoc_icp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 5, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_camnoc_icp =3D { .name =3D "qxm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_camnoc_icp_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; =20 +static struct qcom_icc_qosbox qxm_camnoc_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 3, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qxm_camnoc_sf_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; =20 +static struct qcom_icc_qosbox qxm_mdp0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 3, + .urg_fwd =3D 1, +}; + static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qxm_mdp0_qos, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -616,19 +823,35 @@ static struct qcom_icc_node qnm_gemnoc =3D { &xs_qdss_stm }, }; =20 +static struct qcom_icc_qosbox qxm_pimem_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_pimem_qos, .num_links =3D 2, .link_nodes =3D { &qns_gemnoc_gc, &qxs_imem }, }; =20 +static struct qcom_icc_qosbox xm_gic_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 3, + .urg_fwd =3D 0, +}; + static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_gic_qos, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_gc }, }; @@ -1388,11 +1611,21 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_SERVICE_A1NOC] =3D &srvc_aggre1_noc, }; =20 +static const struct regmap_config sm6350_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x15080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_aggre1_noc =3D { + .config =3D &sm6350_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1413,11 +1646,21 @@ static struct qcom_icc_node * const aggre2_noc_node= s[] =3D { [SLAVE_SERVICE_A2NOC] =3D &srvc_aggre2_noc, }; =20 +static const struct regmap_config sm6350_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f880, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_aggre2_noc =3D { + .config =3D &sm6350_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -1459,7 +1702,16 @@ static struct qcom_icc_node * const compute_noc_node= s[] =3D { [SLAVE_CDSP_GEM_NOC] =3D &qns_cdsp_gemnoc, }; =20 +static const struct regmap_config sm6350_compute_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f880, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_compute_noc =3D { + .config =3D &sm6350_compute_noc_regmap_config, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1532,7 +1784,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { [SLAVE_LLCC_CFG] =3D &qhs_llcc, }; =20 +static const struct regmap_config sm6350_dc_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_dc_noc =3D { + .config =3D &sm6350_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1561,7 +1822,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { [SLAVE_SERVICE_GEM_NOC] =3D &srvc_gemnoc, }; =20 +static const struct regmap_config sm6350_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3e200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_gem_noc =3D { + .config =3D &sm6350_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1588,7 +1858,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC] =3D &srvc_mnoc, }; =20 +static const struct regmap_config sm6350_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c100, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sm6350_mmss_noc =3D { + .config =3D &sm6350_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1643,7 +1922,16 @@ static struct qcom_icc_node * const system_noc_nodes= [] =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6411f713959sm4444376a12.5.2025.11.07.08.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 08:08:53 -0800 (PST) From: Luca Weiss Date: Fri, 07 Nov 2025 17:08:51 +0100 Subject: [PATCH 5/5] arm64: dts: qcom: sm6350: Add clocks for aggre1 & aggre2 NoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251107-sm6350-icc-qos-v1-5-8275e5fc3f61@fairphone.com> References: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> In-Reply-To: <20251107-sm6350-icc-qos-v1-0-8275e5fc3f61@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762531729; l=1111; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=i/zVTdeMZ54Xl+f6Uuj7idYd+OZeYrqPQPp6jVP3UlU=; b=PiC3z4QTLZs98rmiEeLKQeKe7Tx7B7T3YjwsMCoa58NO85pAHVrafZ7ofCkKZne2/b+dgR8Da 6rRb2VnmUQmA7T9eGbSGozCVKcu3EOy/cmKQgdC5w3MldBXuk2dh1z8 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= As per updated bindings, add the clocks for those two interconnects, which are required to set up QoS correctly. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 0c9dc596aa2b..c9a812bc256b 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1117,6 +1117,7 @@ aggre1_noc: interconnect@16e0000 { reg =3D <0x0 0x016e0000 0x0 0x15080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; }; =20 aggre2_noc: interconnect@1700000 { @@ -1124,6 +1125,8 @@ aggre2_noc: interconnect@1700000 { reg =3D <0x0 0x01700000 0x0 0x1f880>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; =20 compute_noc: interconnect-compute-noc { compatible =3D "qcom,sm6350-compute-noc"; --=20 2.51.2