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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477622661c4sm50001595e9.0.2025.11.06.06.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Nov 2025 06:33:40 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 1/2] reset: rzg2l-usbphy-ctrl: Propagate the return value of regmap_field_update_bits() Date: Thu, 6 Nov 2025 16:33:26 +0200 Message-ID: <20251106143327.3049052-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106143327.3049052-1-claudiu.beznea.uj@bp.renesas.com> References: <20251106143327.3049052-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Propagate the return value of regmap_field_update_bits() to avoid losing any possible error. With this, the return type of rzg2l_usbphy_ctrl_set_pwrrdy() was updated accordingly. Signed-off-by: Claudiu Beznea Reviewed-by: Philipp Zabel --- drivers/reset/reset-rzg2l-usbphy-ctrl.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-= rzg2l-usbphy-ctrl.c index 4ecb9acb2641..9ce0c1f5d465 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -117,13 +117,13 @@ static const struct regmap_config rzg2l_usb_regconf = =3D { .max_register =3D 1, }; =20 -static void rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy, - bool power_on) +static int rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy, + bool power_on) { u32 val =3D power_on ? 0 : 1; =20 /* The initialization path guarantees that the mask is 1 bit long. */ - regmap_field_update_bits(pwrrdy, 1, val); + return regmap_field_update_bits(pwrrdy, 1, val); } =20 static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) @@ -138,6 +138,7 @@ static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device = *dev) struct regmap *regmap; const int *data; u32 args[2]; + int ret; =20 data =3D device_get_match_data(dev); if ((uintptr_t)data !=3D RZG2L_USBPHY_CTRL_PWRRDY) @@ -161,7 +162,9 @@ static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device = *dev) if (IS_ERR(pwrrdy)) return PTR_ERR(pwrrdy); =20 - rzg2l_usbphy_ctrl_set_pwrrdy(pwrrdy, true); + ret =3D rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); + if (ret) + return ret; =20 return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, pwrrdy= ); } --=20 2.43.0 From nobody Mon Feb 9 11:36:21 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB88C345CB7 for ; Thu, 6 Nov 2025 14:33:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762439628; cv=none; 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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477622661c4sm50001595e9.0.2025.11.06.06.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Nov 2025 06:33:43 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 2/2] reset: rzg2l-usbphy-ctrl: Add suspend/resume support Date: Thu, 6 Nov 2025 16:33:27 +0200 Message-ID: <20251106143327.3049052-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106143327.3049052-1-claudiu.beznea.uj@bp.renesas.com> References: <20251106143327.3049052-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RZ/G2L USBPHY control driver is also used on the RZ/G3S SoC. The RZ/G3S SoC supports a power-saving mode in which power to most USB components (including the USBPHY control block) is turned off. Because of this, the USBPHY control block needs to be reconfigured when returning from power-saving mode. Add suspend/resume support to handle runtime suspend/resume of the device, assert/deassert the reset signal, and reinitialize the USBPHY control block. Signed-off-by: Claudiu Beznea --- drivers/reset/reset-rzg2l-usbphy-ctrl.c | 94 +++++++++++++++++++++---- 1 file changed, 79 insertions(+), 15 deletions(-) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-= rzg2l-usbphy-ctrl.c index 9ce0c1f5d465..8ba65839f6e4 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -36,6 +36,7 @@ struct rzg2l_usbphy_ctrl_priv { struct reset_control *rstc; void __iomem *base; struct platform_device *vdev; + struct regmap_field *pwrrdy; =20 spinlock_t lock; }; @@ -92,6 +93,19 @@ static int rzg2l_usbphy_ctrl_status(struct reset_control= ler_dev *rcdev, return !!(readl(priv->base + RESET) & port_mask); } =20 +/* put pll and phy into reset state */ +static void rzg2l_usbphy_ctrl_init(struct rzg2l_usbphy_ctrl_priv *priv) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&priv->lock, flags); + val =3D readl(priv->base + RESET); + val |=3D RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESE= T_PORT1; + writel(val, priv->base + RESET); + spin_unlock_irqrestore(&priv->lock, flags); +} + #define RZG2L_USBPHY_CTRL_PWRRDY 1 =20 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] =3D { @@ -131,9 +145,9 @@ static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) rzg2l_usbphy_ctrl_set_pwrrdy(data, false); } =20 -static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev) +static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev, + struct rzg2l_usbphy_ctrl_priv *priv) { - struct regmap_field *pwrrdy; struct reg_field field; struct regmap *regmap; const int *data; @@ -158,15 +172,15 @@ static int rzg2l_usbphy_ctrl_pwrrdy_init(struct devic= e *dev) field.lsb =3D __ffs(args[1]); field.msb =3D __fls(args[1]); =20 - pwrrdy =3D devm_regmap_field_alloc(dev, regmap, field); - if (IS_ERR(pwrrdy)) - return PTR_ERR(pwrrdy); + priv->pwrrdy =3D devm_regmap_field_alloc(dev, regmap, field); + if (IS_ERR(priv->pwrrdy)) + return PTR_ERR(priv->pwrrdy); =20 ret =3D rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); if (ret) return ret; =20 - return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, pwrrdy= ); + return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, priv->= pwrrdy); } =20 static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) @@ -175,9 +189,7 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_devi= ce *pdev) struct rzg2l_usbphy_ctrl_priv *priv; struct platform_device *vdev; struct regmap *regmap; - unsigned long flags; int error; - u32 val; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -191,7 +203,7 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_devi= ce *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 - error =3D rzg2l_usbphy_ctrl_pwrrdy_init(dev); + error =3D rzg2l_usbphy_ctrl_pwrrdy_init(dev, priv); if (error) return error; =20 @@ -214,12 +226,7 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_dev= ice *pdev) goto err_pm_disable_reset_deassert; } =20 - /* put pll and phy into reset state */ - spin_lock_irqsave(&priv->lock, flags); - val =3D readl(priv->base + RESET); - val |=3D RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESE= T_PORT1; - writel(val, priv->base + RESET); - spin_unlock_irqrestore(&priv->lock, flags); + rzg2l_usbphy_ctrl_init(priv); =20 priv->rcdev.ops =3D &rzg2l_usbphy_ctrl_reset_ops; priv->rcdev.of_reset_n_cells =3D 1; @@ -266,10 +273,67 @@ static void rzg2l_usbphy_ctrl_remove(struct platform_= device *pdev) reset_control_assert(priv->rstc); } =20 +static int rzg2l_usbphy_ctrl_suspend(struct device *dev) +{ + struct rzg2l_usbphy_ctrl_priv *priv =3D dev_get_drvdata(dev); + int ret; + + pm_runtime_put(dev); + + ret =3D reset_control_assert(priv->rstc); + if (ret) + goto rpm_resume; + + ret =3D rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false); + if (ret) + goto reset_deassert; + + return 0; + +reset_deassert: + reset_control_deassert(priv->rstc); +rpm_resume: + pm_runtime_resume_and_get(dev); + return ret; +} + +static int rzg2l_usbphy_ctrl_resume(struct device *dev) +{ + struct rzg2l_usbphy_ctrl_priv *priv =3D dev_get_drvdata(dev); + int ret; + + ret =3D rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); + if (ret) + return ret; + + ret =3D reset_control_deassert(priv->rstc); + if (ret) + goto pwrrdy_off; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + goto reset_assert; + + rzg2l_usbphy_ctrl_init(priv); + + return 0; + +reset_assert: + reset_control_assert(priv->rstc); +pwrrdy_off: + rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false); + return ret; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(rzg2l_usbphy_ctrl_pm_ops, + rzg2l_usbphy_ctrl_suspend, + rzg2l_usbphy_ctrl_resume); + static struct platform_driver rzg2l_usbphy_ctrl_driver =3D { .driver =3D { .name =3D "rzg2l_usbphy_ctrl", .of_match_table =3D rzg2l_usbphy_ctrl_match_table, + .pm =3D pm_ptr(&rzg2l_usbphy_ctrl_pm_ops), }, .probe =3D rzg2l_usbphy_ctrl_probe, .remove =3D rzg2l_usbphy_ctrl_remove, --=20 2.43.0