From nobody Fri Dec 19 17:19:46 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3213E32BF41; Thu, 6 Nov 2025 12:43:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433027; cv=none; b=hHHdUFoCrc+eyYyBgF/1O1ZMpsXxGhfr8u3utR9nxmabtw3b74HwOl59/zH86si27zOC0/10DeCJC7Z3w7boJqiebGW9SeaV+q0o5njaMctCTcY6qbKohKe1WJYsjoA8+4VES7sgQwNkAUQAmO6M6LmQ+nNasHmr+ncTgKKKNwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433027; c=relaxed/simple; bh=/wBqBfs+IKzqRQIiNiOLmnGtDE5uFseQ1e9LDu/sGrQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ox8tnqWAPMHmg8/IWOzT5QJYNpS45XJA/BkdGxPZ4eIYMmaI51/4nN634QEoIscTB0a6kQkPuu/dUO66aas98DK4qOfdXJVcm9j0tROgZToAA4vDd02iFRX9VZnELZuEqgxVQ+vSK1Qk7LwQ7NxC6en1Ym+go2OyU4pv2mtmWEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=RV3e0e0t; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="RV3e0e0t" X-UUID: 37a3b748bb0e11f0b33aeb1e7f16c2b6-20251106 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5bjf1Grep5o57O7yDujdNivtzNopvWOK2E/ugqJt1CY=; b=RV3e0e0tkl/aBZ/V0nxa+AewgRZfHI6EVcnP1359DWFB2nRQ3lzdg/v1FApZSh5xxH+jZLiP6YgWIpoV+5uHx0nT+hiD1gA7Om35/C7TXI8eDBtRaeX8mntMqbjd6ijY95YeNE9m3P2M56ROoZNyB3OgzLFPT7uGHBraEe5x2pM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:df9c0f79-515a-42f6-a4c9-a59ade91814d,IP:0,UR L:0,TC:0,Content:0,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:a9d874c,CLOUDID:d113fc7c-f9d7-466d-a1f7-15b5fcad2ce6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:2,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 37a3b748bb0e11f0b33aeb1e7f16c2b6-20251106 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1203535066; Thu, 06 Nov 2025 20:43:38 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Thu, 6 Nov 2025 20:43:37 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Thu, 6 Nov 2025 20:43:37 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v3 03/21] clk: mediatek: fix mfg mux issue Date: Thu, 6 Nov 2025 20:41:48 +0800 Message-ID: <20251106124330.1145600-4-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> References: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin MFG mux design is different for MTK SoCs, For MT8189, we need to enable parent first to garentee parent clock stable. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/clk-mux.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index c5af6dc078a3..15309c7dbbfb 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -414,16 +414,20 @@ static int mtk_clk_mux_notifier_cb(struct notifier_bl= ock *nb, struct clk_notifier_data *data =3D _data; struct clk_hw *hw =3D __clk_get_hw(data->clk); struct mtk_mux_nb *mux_nb =3D to_mtk_mux_nb(nb); + struct clk_hw *p_hw =3D clk_hw_get_parent_by_index(hw, + mux_nb->bypass_index); int ret =3D 0; =20 switch (event) { case PRE_RATE_CHANGE: + clk_prepare_enable(p_hw->clk); mux_nb->original_index =3D mux_nb->ops->get_parent(hw); ret =3D mux_nb->ops->set_parent(hw, mux_nb->bypass_index); break; case POST_RATE_CHANGE: case ABORT_RATE_CHANGE: ret =3D mux_nb->ops->set_parent(hw, mux_nb->original_index); + clk_disable_unprepare(p_hw->clk); break; } =20 --=20 2.45.2