From nobody Fri Dec 19 17:20:10 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B349732ED39; Thu, 6 Nov 2025 12:43:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433035; cv=none; b=Xi0AMvwG9p+kcvSgYKGeMlJW5cVzATq4YIB0GOTu3XmgfPi6GDlLEeTAfdz1zzWzJVfsssO6n7KUliosIkf0tsig1MtZHwxTGrBjR8m3dHAExF28oltK6XvjXBjSZs3+jB7bXoJ4QsJv5aeA2apVwCKBqABWXL4HL1DdzbKcncc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433035; c=relaxed/simple; bh=gTWASIGMERDpQKrjtw3e1m5YRN1rR8e0l5PtfgoDyhg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DJjLSM1Pra6An9WswQNLlCkposuPywkVBuucoxg/IKC5/3ZKB1+ID/rJTfSJY9OHi5Mt59gKj49tR5Sd0HqJkmpthhUrggnagkU27KYRpPivzp00cPz07Q6vs1spNe8RN/4UTC9GeURXW5RbSsh61xgqPlYpLBFOoNwOZYT3hv8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=nXplDTMi; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="nXplDTMi" X-UUID: 38f0ad90bb0e11f08ac0a938fc7cd336-20251106 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LIHVBXnQN2Ijgw2G3KADn1qkSYIz3/eKbrMMUyWzLLo=; b=nXplDTMiEJp9fsPl5R9K7QtJaaIxEywE3FKrZdozqvqVg9Yjp2VrZf/5PAcmo5UDRH0O7nT5nv6YiDMlNFJyEDmbRQoC6O2y55r5aKJmYiuZESDgS68Rs7s0BDf8N7p4eHjdPZrgPR1p4uHqFjLPjkYvcIKUUOxnyRZtQNCH4eU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:f34f4304-5e67-485f-927f-57c692fc42a3,IP:0,UR L:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-50 X-CID-META: VersionHash:a9d874c,CLOUDID:b369fe18-3399-4579-97ab-008f994989ea,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:2,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 38f0ad90bb0e11f08ac0a938fc7cd336-20251106 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1695248759; Thu, 06 Nov 2025 20:43:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Thu, 6 Nov 2025 20:43:39 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Thu, 6 Nov 2025 20:43:39 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v3 18/21] clk: mediatek: Add MT8189 ufs clock support Date: Thu, 6 Nov 2025 20:42:03 +0800 Message-ID: <20251106124330.1145600-19-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> References: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 ufs clock controller, which provides clock gate control for Universal Flash Storage. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 12 ++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-ufs.c | 100 ++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-ufs.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 2cc1a28436f1..3ef964b19d97 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -939,6 +939,18 @@ config COMMON_CLK_MT8189_SCP management for SCP-related features, ensuring proper clock distribution and gating for power efficiency and functionality. =20 +config COMMON_CLK_MT8189_UFS + tristate "Clock driver for MediaTek MT8189 ufs" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the Universal Flash + Storage (UFS) interface on MediaTek MT8189 SoCs. This includes + clock sources, dividers, and gates that are specific to the UFS + feature of the MT8189 platform. It is recommended to enable this + option if the system includes a UFS device that relies on the MT8189 + SoC for clock management. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 819c67395e1b..4179808dba7b 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -135,6 +135,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) +=3D clk-mt8189-= mdpsys.o obj-$(CONFIG_COMMON_CLK_MT8189_MFG) +=3D clk-mt8189-mfg.o obj-$(CONFIG_COMMON_CLK_MT8189_MMSYS) +=3D clk-mt8189-dispsys.o obj-$(CONFIG_COMMON_CLK_MT8189_SCP) +=3D clk-mt8189-scp.o +obj-$(CONFIG_COMMON_CLK_MT8189_UFS) +=3D clk-mt8189-ufs.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-ufs.c b/drivers/clk/mediatek/c= lk-mt8189-ufs.c new file mode 100644 index 000000000000..9272e4efea2b --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-ufs.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs ufscfg_ao_reg_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0xc, + .sta_ofs =3D 0x4, +}; + +#define GATE_UFSCFG_AO_REG(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &ufscfg_ao_reg_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + .flags =3D CLK_OPS_PARENT_ENABLE | CLK_IGNORE_UNUSED, \ + } + +static const struct mtk_gate ufscfg_ao_reg_clks[] =3D { + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM, + "ufscfg_ao_unipro_tx_sym", "clk26m", 1), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0, + "ufscfg_ao_unipro_rx_sym0", "clk26m", 2), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1, + "ufscfg_ao_unipro_rx_sym1", "clk26m", 3), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_SYS, + "ufscfg_ao_unipro_sys", "ufs_sel", 4), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_U_SAP_CFG, + "ufscfg_ao_u_sap_cfg", "clk26m", 5), + GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS, + "ufscfg_ao_u_phy_ahb_s_bus", "axi_u_sel", 6), +}; + +static const struct mtk_clk_desc ufscfg_ao_reg_mcd =3D { + .clks =3D ufscfg_ao_reg_clks, + .num_clks =3D ARRAY_SIZE(ufscfg_ao_reg_clks), +}; + +static const struct mtk_gate_regs ufscfg_pdn_reg_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0xc, + .sta_ofs =3D 0x4, +}; + +#define GATE_UFSCFG_PDN_REG(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &ufscfg_pdn_reg_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + .flags =3D CLK_OPS_PARENT_ENABLE | CLK_IGNORE_UNUSED, \ + } + +static const struct mtk_gate ufscfg_pdn_reg_clks[] =3D { + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_UFS, + "ufscfg_ufshci_ufs", "ufs_sel", 0), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_AES, + "ufscfg_ufshci_aes", "aes_ufsfde_sel", 1), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AHB, + "ufscfg_ufshci_u_ahb", "axi_u_sel", 3), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AXI, + "ufscfg_ufshci_u_axi", "mem_sub_u_sel", 5), +}; + +static const struct mtk_clk_desc ufscfg_pdn_reg_mcd =3D { + .clks =3D ufscfg_pdn_reg_clks, + .num_clks =3D ARRAY_SIZE(ufscfg_pdn_reg_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_ufs[] =3D { + { .compatible =3D "mediatek,mt8189-ufscfg-ao", .data =3D &ufscfg_ao_reg_m= cd }, + { .compatible =3D "mediatek,mt8189-ufscfg-pdn", .data =3D &ufscfg_pdn_reg= _mcd }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8189_ufs_drv =3D { + .probe =3D mtk_clk_simple_probe, + .driver =3D { + .name =3D "clk-mt8189-ufs", + .of_match_table =3D of_match_clk_mt8189_ufs, + }, +}; + +module_platform_driver(clk_mt8189_ufs_drv); +MODULE_LICENSE("GPL"); --=20 2.45.2