From nobody Fri Dec 19 17:20:11 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F260532C936; Thu, 6 Nov 2025 12:43:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433034; cv=none; b=fnkCAlEQG5mOg70X1qOFMA70ATsGmitw1rmPSoS1nSu1nTmdC+2UNt331KvLiymZXsJcMiOD3m44nspScR0xcofb43X4tiUgN0fdZCH3HuRElGybJaNfT8WcZqGlBAnxbmghioWqSYZdHPYC9n9OHkFNex/v9AQpS1mW0t74GB0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433034; c=relaxed/simple; bh=vYc2MJQCRuvHsoPko9rZ5yRlmrI4s6nuS0Udj7sf2lo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XYlFPWqcJWM3oa/XVeTpm0dQ8Ms0A1aFpBao1f1dFL2je4TNWIibhW6d3Ip/aYnhEMcnEozNW+sVzVuf3C9mTsZOOhNijI8/mwTDxlK4dlNSpbSog8ToFa3I/TWtmAKjVuWKVyjO8MVNaeOtxWT1hLlWo1+EgqxSIdlWKimG0u4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=BCs2Mle2; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="BCs2Mle2" X-UUID: 38dbed74bb0e11f08ac0a938fc7cd336-20251106 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LER1Qf7D5I6J9w8xgObEuO2R/RxpPzNqWvzDcUL9RhE=; b=BCs2Mle2efGhlbeXfvxiLfJYTCYzPPCc3Vl9UoYSrfl1He/6DsicJKybeCsz+oSRzdMV1oqMbvDITcYTThE24Od8Xhnna8gQZDMqwQtfgxa14kWy9742zaQMrmXbDCfXshbvsP3JBMgIT20y6mVt4NMu4Gr2vRfvmT21+cpYfqI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:ad4570e6-d61e-4e1f-bec6-e39de7c2fb91,IP:0,UR L:0,TC:0,Content:0,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:a9d874c,CLOUDID:dd13fc7c-f9d7-466d-a1f7-15b5fcad2ce6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:2,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 38dbed74bb0e11f08ac0a938fc7cd336-20251106 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1687308242; Thu, 06 Nov 2025 20:43:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Thu, 6 Nov 2025 20:43:39 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Thu, 6 Nov 2025 20:43:39 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v3 14/21] clk: mediatek: Add MT8189 mdp clock support Date: Thu, 6 Nov 2025 20:41:59 +0800 Message-ID: <20251106124330.1145600-15-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> References: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 mdp clock controller, which provides clock gate control for display system. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 12 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-mdpsys.c | 100 +++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-mdpsys.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index c0fe1aa49993..ef962f5816a8 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -894,6 +894,18 @@ config COMMON_CLK_MT8189_IMG are building a kernel for a device that uses the MT8189 SoC and requires image processing capabilities, say Y or M to include this driver. =20 +config COMMON_CLK_MT8189_MDPSYS + tristate "Clock driver for MediaTek MT8189 mdpsys" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + This driver supports the display system clocks on the MediaTek MT8189 + SoC. By enabling this option, it allows for the control of the clocks + related to the display subsystem. This is crucial for the proper + functionality of the display features on devices powered by the MT8189 + chipset, ensuring that the display system operates efficiently and + effectively. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index a1eaf123f2f0..9b23e4c5e019 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -131,6 +131,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-d= bgao.o obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8189_IMG) +=3D clk-mt8189-img.o +obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) +=3D clk-mt8189-mdpsys.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-mdpsys.c b/drivers/clk/mediate= k/clk-mt8189-mdpsys.c new file mode 100644 index 000000000000..eac966ebac36 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-mdpsys.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mdp0_cg_regs =3D { + .set_ofs =3D 0x04, + .clr_ofs =3D 0x08, + .sta_ofs =3D 0x00, +}; + +static const struct mtk_gate_regs mdp1_cg_regs =3D { + .set_ofs =3D 0x14, + .clr_ofs =3D 0x18, + .sta_ofs =3D 0x10, +}; + +#define GATE_MDP0(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &mdp0_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + .flags =3D CLK_OPS_PARENT_ENABLE | CLK_IGNORE_UNUSED, \ + } + +#define GATE_MDP1(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &mdp1_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + .flags =3D CLK_OPS_PARENT_ENABLE | CLK_IGNORE_UNUSED, \ + } + +static const struct mtk_gate mdp_clks[] =3D { + /* MDP0 */ + GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0", "mdp0_sel", 0), + GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp0_sel", 1), + GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp0_sel", 2), + GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0", "mdp0_sel", 3), + GATE_MDP0(CLK_MDP_RDMA2, "mdp_rdma2", "mdp0_sel", 4), + GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0", "mdp0_sel", 5), + GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0", "mdp0_sel", 6), + GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0", "mdp0_sel", 7), + GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0", "mdp0_sel", 8), + GATE_MDP0(CLK_MDP_COLOR0, "mdp_color0", "mdp0_sel", 9), + GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0", "mdp0_sel", 10), + GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_fake_eng0", "mdp0_sel", 11), + GATE_MDP0(CLK_MDPSYS_CONFIG, "mdpsys_config", "mdp0_sel", 14), + GATE_MDP0(CLK_MDP_RDMA1, "mdp_rdma1", "mdp0_sel", 15), + GATE_MDP0(CLK_MDP_RDMA3, "mdp_rdma3", "mdp0_sel", 16), + GATE_MDP0(CLK_MDP_HDR1, "mdp_hdr1", "mdp0_sel", 17), + GATE_MDP0(CLK_MDP_AAL1, "mdp_aal1", "mdp0_sel", 18), + GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1", "mdp0_sel", 19), + GATE_MDP0(CLK_MDP_TDSHP1, "mdp_tdshp1", "mdp0_sel", 20), + GATE_MDP0(CLK_MDP_COLOR1, "mdp_color1", "mdp0_sel", 21), + GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1", "mdp0_sel", 22), + GATE_MDP0(CLK_MDP_RSZ2, "mdp_rsz2", "mdp0_sel", 24), + GATE_MDP0(CLK_MDP_WROT2, "mdp_wrot2", "mdp0_sel", 25), + GATE_MDP0(CLK_MDP_RSZ3, "mdp_rsz3", "mdp0_sel", 28), + GATE_MDP0(CLK_MDP_WROT3, "mdp_wrot3", "mdp0_sel", 29), + /* MDP1 */ + GATE_MDP1(CLK_MDP_BIRSZ0, "mdp_birsz0", "mdp0_sel", 3), + GATE_MDP1(CLK_MDP_BIRSZ1, "mdp_birsz1", "mdp0_sel", 4), +}; + +static const struct mtk_clk_desc mdp_mcd =3D { + .clks =3D mdp_clks, + .num_clks =3D ARRAY_SIZE(mdp_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_mdpsys[] =3D { + { .compatible =3D "mediatek,mt8189-mdpsys", .data =3D &mdp_mcd }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8189_mdpsys_drv =3D { + .probe =3D mtk_clk_simple_probe, + .driver =3D { + .name =3D "clk-mt8189-mdpsys", + .of_match_table =3D of_match_clk_mt8189_mdpsys, + }, +}; + +module_platform_driver(clk_mt8189_mdpsys_drv); +MODULE_LICENSE("GPL"); --=20 2.45.2