From nobody Fri Dec 19 17:19:40 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE1D13328F6; Thu, 6 Nov 2025 12:43:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433035; cv=none; b=CNjZ233Q5T7d+t0EA4Wk7EtN1QxzzF/tsx8Iq7ox65HNrIYR51UMk4PPhpmgvkfGvDXKKIeVGIDi827R3MUI3FKuwyBBr2HrsQRTSSKAact0Qkavhu092iKfSY9vEQ7JPcv99oqcvru6SSNhZ8oNHL9Fe6p5xXsJTDsMEjODMkE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433035; c=relaxed/simple; bh=0V2qMHuOwOJAQEBi96zBjnY7CLeP+D4HTsxJ7XTfbYc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YKoJ0VzP2vBBwl8DLe7hA6X8qFHN7xbAnrj8yoxX6FAxD7k8XE12Z1HGMpYEKgc3WSk8USbwFlK60G33Ue/RxKWwctlHOwN3h2944/XJGUKzl8JEuy2Bqg3hm0BFK9oWh2OuYxUrEgdmeYK8Eb9TowkJfQI3GKoAvGwYfd1ZS+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=BGhlyJPi; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="BGhlyJPi" X-UUID: 38933642bb0e11f08ac0a938fc7cd336-20251106 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=c/SsWent1RCQNaV5BwuVJPJWEh3ggHtRBjZU7QMaCp4=; b=BGhlyJPiMnyV1QZxa66P3HrT2QB1SBnVsLEO1IOtgmEbt+Z15NboywFEjMUlGbtZTLkNcWjIPsDqrzfn+cTdxO7fVuH67de+WYSAXmYgBGuiiJtY60FJqp2xB9An/e9A8OTGJbfFH1B17rhSILFgubqzUFzELs7CegJH5+dF9tw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:71efb79e-30f3-4560-9155-1d9a4c67847d,IP:0,UR L:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-50 X-CID-META: VersionHash:a9d874c,CLOUDID:cbd934e0-3890-4bb9-a90e-2a6a4ecf6c66,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:2,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 38933642bb0e11f08ac0a938fc7cd336-20251106 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2117734709; Thu, 06 Nov 2025 20:43:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Thu, 6 Nov 2025 20:43:38 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Thu, 6 Nov 2025 20:43:38 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v3 12/21] clk: mediatek: Add MT8189 i2c clock support Date: Thu, 6 Nov 2025 20:41:57 +0800 Message-ID: <20251106124330.1145600-13-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> References: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 i2c clock controller, which provides clock gate control for i2c. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 13 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-iic.c | 139 ++++++++++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-iic.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 76c9391bee69..71603fba2ea8 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -870,6 +870,19 @@ config COMMON_CLK_MT8189_DVFSRC vcore dvfs clocks. If you want to control its clocks, say Y or M to include this driver in your kernel build. =20 +config COMMON_CLK_MT8189_IIC + tristate "Clock driver for MediaTek MT8189 iic" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this option to support the clock framework for MediaTek MT8189 + integrated circuits (iic). This driver is responsible for managing + clock sources, dividers, and gates specifically designed for MT8189 + SoCs. Enabling this driver ensures that the system can correctly + manage clock frequencies and power for various components within + the MT8189 chipset, improving the overall performance and power + efficiency of the device. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 3a8dad865c97..0eed1edf7c63 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -129,6 +129,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus= .o obj-$(CONFIG_COMMON_CLK_MT8189_CAM) +=3D clk-mt8189-cam.o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-dvfsrc.o +obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-iic.c b/drivers/clk/mediatek/c= lk-mt8189-iic.c new file mode 100644 index 000000000000..1a2a74b822a5 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-iic.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs impe_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPE(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &impe_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + .flags =3D CLK_OPS_PARENT_ENABLE, \ + } + +static const struct mtk_gate impe_clks[] =3D { + GATE_IMPE(CLK_IMPE_I2C0, "impe_i2c0", "i2c_sel", 0), + GATE_IMPE(CLK_IMPE_I2C1, "impe_i2c1", "i2c_sel", 1), +}; + +static const struct mtk_clk_desc impe_mcd =3D { + .clks =3D impe_clks, + .num_clks =3D ARRAY_SIZE(impe_clks), +}; + +static const struct mtk_gate_regs impen_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPEN(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &impen_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + .flags =3D CLK_OPS_PARENT_ENABLE, \ + } + +static const struct mtk_gate impen_clks[] =3D { + GATE_IMPEN(CLK_IMPEN_I2C7, "impen_i2c7", "i2c_sel", 0), + GATE_IMPEN(CLK_IMPEN_I2C8, "impen_i2c8", "i2c_sel", 1), +}; + +static const struct mtk_clk_desc impen_mcd =3D { + .clks =3D impen_clks, + .num_clks =3D ARRAY_SIZE(impen_clks), +}; + +static const struct mtk_gate_regs imps_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPS(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &imps_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + .flags =3D CLK_OPS_PARENT_ENABLE, \ + } + +static const struct mtk_gate imps_clks[] =3D { + GATE_IMPS(CLK_IMPS_I2C3, "imps_i2c3", "i2c_sel", 0), + GATE_IMPS(CLK_IMPS_I2C4, "imps_i2c4", "i2c_sel", 1), + GATE_IMPS(CLK_IMPS_I2C5, "imps_i2c5", "i2c_sel", 2), + GATE_IMPS(CLK_IMPS_I2C6, "imps_i2c6", "i2c_sel", 3), +}; + +static const struct mtk_clk_desc imps_mcd =3D { + .clks =3D imps_clks, + .num_clks =3D ARRAY_SIZE(imps_clks), +}; + +static const struct mtk_gate_regs impws_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPWS(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &impws_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + .flags =3D CLK_OPS_PARENT_ENABLE, \ + } + +static const struct mtk_gate impws_clks[] =3D { + GATE_IMPWS(CLK_IMPWS_I2C2, "impws_i2c2", "i2c_sel", 0), +}; + +static const struct mtk_clk_desc impws_mcd =3D { + .clks =3D impws_clks, + .num_clks =3D ARRAY_SIZE(impws_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_iic[] =3D { + { .compatible =3D "mediatek,mt8189-iic-wrap-e", .data =3D &impe_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-en", .data =3D &impen_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-s", .data =3D &imps_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-ws", .data =3D &impws_mcd }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8189_iic_drv =3D { + .probe =3D mtk_clk_simple_probe, + .driver =3D { + .name =3D "clk-mt8189-iic", + .of_match_table =3D of_match_clk_mt8189_iic, + }, +}; + +module_platform_driver(clk_mt8189_iic_drv); +MODULE_LICENSE("GPL"); --=20 2.45.2