From nobody Fri Dec 19 17:19:39 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D311332E6B5; Thu, 6 Nov 2025 12:43:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433032; cv=none; b=cwPKOMURR9xvf6f82N/FVvgIgqv0hs4/ujMaCdXNj5nt0wFWf+GYHS4npEm6kdhSr56XBqWPG7R37yh2gRVyt4j6AZZZ6Hfiy5Tq2DEcRZJA23KN1OuTuHeHydM1mco35bcF0OoUmtQr9SctAqySSxVlIhZwbWGrZG603MJRoY0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762433032; c=relaxed/simple; bh=HL8IWf5DaElpplMxp+5nRPd3rOn2WhabfaC/xnjdzP0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=u2ckCDF8vdZIM0ACfhNNoViGIxJoDrSh90zvMUe4ouxDLTzZ8P6YG01MR1Av1n+wqrVGcfvCyOhKXNQZqqBHVyE/BrNOTpNyoCaxme5y8mNgdotf+90TSf1Rq/r06ki3IzgXj5dHvaoCsMoy+z0GeqaixCLQNN/uZvpfWMtMEws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=OH1qyoRk; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="OH1qyoRk" X-UUID: 3863b4d0bb0e11f08ac0a938fc7cd336-20251106 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mLiD0RUH8avhai/+nOpfX3FHj+VIOyhNPMQSFNVdBCg=; b=OH1qyoRkQLtDh3JEe+QcHOK9Tg+W+X4cVsbWmdLHAT3V9osDtNygjYtj8hQl1hk80MPr6SYT9Scym6RIQsE09mxNmiEFp89D/OIu+o4ZJuuWKMjnxi/AF3vxQt3nrAofyORkwXsUMAwGl/Fah6udbHdJiaX2k8DmLKrMF9UsuA0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:10a73ea0-c2d5-4ba6-8fca-754d3c53bcb5,IP:0,UR L:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-50 X-CID-META: VersionHash:a9d874c,CLOUDID:cad934e0-3890-4bb9-a90e-2a6a4ecf6c66,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:2,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 3863b4d0bb0e11f08ac0a938fc7cd336-20251106 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1518347632; Thu, 06 Nov 2025 20:43:39 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Thu, 6 Nov 2025 20:43:38 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Thu, 6 Nov 2025 20:43:38 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v3 10/21] clk: mediatek: Add MT8189 dbgao clock support Date: Thu, 6 Nov 2025 20:41:55 +0800 Message-ID: <20251106124330.1145600-11-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> References: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 dbgao clock controller, which provides clock gate control for debug-system. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 10 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dbgao.c | 115 ++++++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-dbgao.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 82a26d952bff..c707b224dccd 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -850,6 +850,16 @@ config COMMON_CLK_MT8189_CAM that relies on this SoC and you want to control its clocks, say Y or M to include this driver in your kernel build. =20 +config COMMON_CLK_MT8189_DBGAO + tristate "Clock driver for MediaTek MT8189 debug ao" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the debug function + on MediaTek MT8189 SoCs. This includes enabling and disabling + vcore debug system clocks. If you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 95a8f4ae05ee..eabe2cab4b8d 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -127,6 +127,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixed= sys.o clk-mt8189-topckgen.o clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus.o obj-$(CONFIG_COMMON_CLK_MT8189_CAM) +=3D clk-mt8189-cam.o +obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dbgao.c b/drivers/clk/mediatek= /clk-mt8189-dbgao.c new file mode 100644 index 000000000000..d760e2ea801a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dbgao.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs dbgao_cg_regs =3D { + .set_ofs =3D 0x70, + .clr_ofs =3D 0x70, + .sta_ofs =3D 0x70, +}; + +#define GATE_DBGAO(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &dbgao_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate dbgao_clks[] =3D { + GATE_DBGAO(CLK_DBGAO_ATB_EN, "dbgao_atb_en", "atb_sel", 0), +}; + +static const struct mtk_clk_desc dbgao_mcd =3D { + .clks =3D dbgao_clks, + .num_clks =3D ARRAY_SIZE(dbgao_clks), +}; + +static const struct mtk_gate_regs dem0_cg_regs =3D { + .set_ofs =3D 0x2c, + .clr_ofs =3D 0x2c, + .sta_ofs =3D 0x2c, +}; + +static const struct mtk_gate_regs dem1_cg_regs =3D { + .set_ofs =3D 0x30, + .clr_ofs =3D 0x30, + .sta_ofs =3D 0x30, +}; + +static const struct mtk_gate_regs dem2_cg_regs =3D { + .set_ofs =3D 0x70, + .clr_ofs =3D 0x70, + .sta_ofs =3D 0x70, +}; + +#define GATE_DEM0(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &dem0_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ + } + +#define GATE_DEM1(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &dem1_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ + } + +#define GATE_DEM2(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &dem2_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate dem_clks[] =3D { + /* DEM0 */ + GATE_DEM0(CLK_DEM_BUSCLK_EN, "dem_busclk_en", "axi_sel", 0), + /* DEM1 */ + GATE_DEM1(CLK_DEM_SYSCLK_EN, "dem_sysclk_en", "axi_sel", 0), + /* DEM2 */ + GATE_DEM2(CLK_DEM_ATB_EN, "dem_atb_en", "atb_sel", 0), +}; + +static const struct mtk_clk_desc dem_mcd =3D { + .clks =3D dem_clks, + .num_clks =3D ARRAY_SIZE(dem_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dbgao[] =3D { + { .compatible =3D "mediatek,mt8189-dbg-ao", .data =3D &dbgao_mcd }, + { .compatible =3D "mediatek,mt8189-dem", .data =3D &dem_mcd }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8189_dbgao_drv =3D { + .probe =3D mtk_clk_simple_probe, + .driver =3D { + .name =3D "clk-mt8189-dbgao", + .of_match_table =3D of_match_clk_mt8189_dbgao, + }, +}; + +module_platform_driver(clk_mt8189_dbgao_drv); +MODULE_LICENSE("GPL"); --=20 2.45.2