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Thu, 6 Nov 2025 02:29:08 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 6/7] rust: pci: add config space read/write support Date: Thu, 6 Nov 2025 12:27:52 +0200 Message-ID: <20251106102753.2976-7-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106102753.2976-1-zhiw@nvidia.com> References: <20251106102753.2976-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|CH0PR12MB8461:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e3ab7ef-7e10-4f20-c4ef-08de1d1f5f5f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QONL+4d+op2oqinNNc0XKYASABocY/PVmyu8STBHWQqNxKG3MA2c572kpnUf?= =?us-ascii?Q?lBypVNIhVqWKrzp8eEF6hzLU5DcM1akFKFhnlcSPQ5OpgZBecYP+QraqHzPZ?= =?us-ascii?Q?XNhfmQa9K43RBicvQfy/v7BzciBzXEyDrTvV+07UOB5CwxtiG0FT0STe2EzQ?= =?us-ascii?Q?l6p7hDS2tU/exdagfdQzNuXpaK+EbOBeX9ubXmTdMgduKIOf76iEHp+Hki1t?= =?us-ascii?Q?yhulDsdxo6mYUbTpl7bmT6csJnVS+TstL9iRtgCJSiPUqjqL7ivuVhEPrBzc?= =?us-ascii?Q?K7wF87LjH2/d3b1kx/7ClUXeEs5pbgoXUdqrykDkYSYpVlZUidaXs/5toQrC?= =?us-ascii?Q?hQTJvmeNr3oXawGASKE1eR/u6RqrpIV/Ko1AsI+mIpRHxNliCRofd81UPTTe?= =?us-ascii?Q?BHuhlTlOomvHxmjBNmTjn0M1z4VsmrKCTvh0xYMkVTkY6brrNdjLKKJZ2tXy?= =?us-ascii?Q?WGZDN4i+Wfw19E/e9V3lM585KNw8KZrRUjIE+ng/6NzTGwhhVdZVEP942Ohp?= =?us-ascii?Q?HEgrb7eg/kYLC4iVmApi0xl/yzwJWAXUaMcexBGIm1vW0ldYWBdUzEPJAhjh?= =?us-ascii?Q?SzUZWL5ZTvS9eMLAZcLUP2S6I3UrJN5E7n8wNP2MLXCuvafOY41KWUgWtE/6?= =?us-ascii?Q?oht6FGP3C8kFZzP7RtDOK09aGlYgU/Wm0P7EYxD5msFuqgnE/Il4X7goGF99?= =?us-ascii?Q?RWTMhUzpD+O9Eh/Cod9T9FYJR3sj3908jGZBinmerkflxJDXgLyoUoGJyIuQ?= =?us-ascii?Q?cXaSXmz8mQoNV71FtDHHzQoWtg7m9KPVkN170//+2FrYZHJhmrMt81v5BNHS?= =?us-ascii?Q?wWRmoUgJLaYf7drqFt6+AA+jr1AHvj+D1/BlW4Mar58wwgaF2B/D526U9AkR?= =?us-ascii?Q?A6TYQqzMnBJA4Wy3iKoCm2rz0MgVuJRkT+4OpYYi2RtbGVl+I33b7/IurhqX?= =?us-ascii?Q?VJ28XkAq8jpqYyiLcCDURvRhyb1wKu1kQM6AliZs0XTDAPBm1skPGkKKhDpy?= =?us-ascii?Q?NX5pA1I01uWb5Ch1c7njkpMRvdzQFqD99VLqlayjPMJIj8sG3cFy9K9Tb8kg?= =?us-ascii?Q?Ek+bMEL3htCng5RU7EDh2eZfEl7uk2XC6aimk40Vhh5BTo6luLV+0QdeEOBN?= =?us-ascii?Q?FMxNQlZ0RIwhM/jC5+6Diaojv6ZgDaX5vYFm4FSaJynS0cYueLHwB+e9ucVi?= =?us-ascii?Q?1rP7wJE1X2iry3OSFrYwUp6ZkgV0ZRXgObyYKlEeQleqGd5/jsivErvI0Dwb?= =?us-ascii?Q?taasPsfVsuGxhi7Memm3aBRJk/oMTnfHrRcWRhV8PEAZxlL4cqbq6JeC2x/d?= =?us-ascii?Q?1BrZfRQhCwPCSTO3Z0XUlJZUcXKu8ORI2r1EG+CPSp1cHuE8ldeuG1RS99FQ?= =?us-ascii?Q?XPKzZPCm+OQZKM8+KtRAoxo4D7HdowzsON2TjP1BUQ/VtMXQntrc9TzL2o1N?= =?us-ascii?Q?f8w3eAM+hGZCYE3abDjYhBn5EyS0ufeKnUsnwY6vTsDcb0ogy2gfWu7Kqa7e?= =?us-ascii?Q?x7/7VwbMhw30X0h7zhKk1Gy/pZoOGe4sOdRhHFDZrZRQEpdi5ZYkYw1Dkw0q?= =?us-ascii?Q?0A809adlBXKxd/nCWYg=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:29:31.4060 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e3ab7ef-7e10-4f20-c4ef-08de1d1f5f5f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002322.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8461 Content-Type: text/plain; charset="utf-8" Drivers might need to access PCI config space for querying capability structures and access the registers inside the structures. For Rust drivers need to access PCI config space, the Rust PCI abstraction needs to support it in a way that upholds Rust's safety principles. Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe accessors for PCI config space. The new type implements the `Io` trait to share offset validation and bound-checking logic with others. Cc: Danilo Krummrich Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 55 +++++++++++++++++++++++++++++++++++++- rust/kernel/pci/io.rs | 62 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 115 insertions(+), 2 deletions(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 410b79d46632..0b8064d6c0d1 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -39,7 +39,10 @@ ClassMask, Vendor, // }; -pub use self::io::Bar; +pub use self::io::{ + Bar, + ConfigSpace, // +}; pub use self::irq::{ IrqType, IrqTypes, @@ -330,6 +333,28 @@ fn as_raw(&self) -> *mut bindings::pci_dev { } } =20 +/// Represents the size of a PCI configuration space. +/// +/// PCI devices can have either a *normal* (legacy) configuration space of= 256 bytes, +/// or an *extended* configuration space of 4096 bytes as defined in the P= CI Express +/// specification. +#[repr(usize)] +pub enum ConfigSpaceSize { + /// 256-byte legacy PCI configuration space. + Normal =3D 256, + + /// 4096-byte PCIe extended configuration space. + Extended =3D 4096, +} + +impl ConfigSpaceSize { + /// Get the raw value of this enum. + #[inline(always)] + pub const fn as_raw(self) -> usize { + self as usize + } +} + impl Device { /// Returns the PCI vendor ID as [`Vendor`]. /// @@ -426,6 +451,20 @@ pub fn pci_class(&self) -> Class { // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. Class::from_raw(unsafe { (*self.as_raw()).class }) } + + /// Returns the size of configuration space. + fn cfg_size(&self) -> Result { + // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. + let size =3D unsafe { (*self.as_raw()).cfg_size }; + match size { + 256 =3D> Ok(ConfigSpaceSize::Normal), + 4096 =3D> Ok(ConfigSpaceSize::Extended), + _ =3D> { + debug_assert!(false); + Err(EINVAL) + } + } + } } =20 impl Device { @@ -441,6 +480,20 @@ pub fn set_master(&self) { // SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid = `struct pci_dev`. unsafe { bindings::pci_set_master(self.as_raw()) }; } + + /// Return an initialized config space object. + pub fn config_space<'a>( + &'a self, + ) -> Result> { + Ok(ConfigSpace { pdev: self }) + } + + /// Return an initialized config space object. + pub fn config_space_exteneded<'a>( + &'a self, + ) -> Result> { + Ok(ConfigSpace { pdev: self }) + } } =20 // SAFETY: `Device` is a transparent wrapper of a type that doesn't depend= on `Device`'s generic diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index 2bbb3261198d..a9895ee2c5c8 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -2,12 +2,19 @@ =20 //! PCI memory-mapped I/O infrastructure. =20 -use super::Device; +use super::{ + Device, + ConfigSpaceSize, // +}; use crate::{ bindings, device, devres::Devres, io::{ + define_read, + define_write, + Io, + IoInfallible, Mmio, MmioRaw, // }, @@ -16,6 +23,59 @@ }; use core::ops::Deref; =20 +/// Represents the PCI configuration space of a device. +/// +/// Provides typed read and write accessors for configuration registers +/// using the standard `pci_read_config_*` and `pci_write_config_*` helper= s. +/// +/// The generic const parameter `SIZE` can be used to indicate the +/// maximum size of the configuration space (e.g. 256 bytes for legacy, +/// 4096 bytes for extended config space). The actual size is obtained +/// from the underlying `struct pci_dev` via [`Device::cfg_size`]. +pub struct ConfigSpace<'a, const SIZE: usize =3D { ConfigSpaceSize::Extend= ed as usize }> { + pub(crate) pdev: &'a Device, +} + +macro_rules! call_config_read { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =3D> {{ + let mut val: $ty =3D 0; + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, &mut val) }; + val + }}; +} + +macro_rules! call_config_write { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr= ) =3D> { + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, $value) }; + }; +} + +impl<'a, const SIZE: usize> Io for ConfigSpace<'a, SIZE> { + const MIN_SIZE: usize =3D SIZE; + + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + 0 + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.pdev.cfg_size().map_or(0, |v| v as usize) + } +} + +impl<'a, const SIZE: usize> IoInfallible for ConfigSpace<'a, SIZE> { + define_read!(infallible, read8, call_config_read, pci_read_config_byte= -> u8); + define_read!(infallible, read16, call_config_read, pci_read_config_wor= d -> u16); + define_read!(infallible, read32, call_config_read, pci_read_config_dwo= rd -> u32); + + define_write!(infallible, write8, call_config_write, pci_write_config_= byte <- u8); + define_write!(infallible, write16, call_config_write, pci_write_config= _word <- u16); + define_write!(infallible, write32, call_config_write, pci_write_config= _dword <- u32); +} + /// A PCI BAR to perform I/O-Operations on. /// /// # Invariants --=20 2.51.0