From nobody Fri Dec 19 15:48:09 2025 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011056.outbound.protection.outlook.com [40.107.208.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD8932248B4; Thu, 6 Nov 2025 10:28:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.56 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424925; cv=fail; b=FzgX2cJeaTsjXq3tpnxPcHiMvum0FRiiozXVIKGagzCeKIxzlmbB+uQB0N51McpGbA9lza9E18D4We9A5l+afPheT4YnetsKtK5fiWDLfX8LCs3BOmwpG4/EnBiaYn52OqsMvg9IucALxgbNRt5vMq4SdscUYm5PUbtfIQVQjc4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424925; c=relaxed/simple; bh=pmufUxO4slioaJ2XtjP+dPrsPcRDjxS4Yfvv2hMe+R8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QGsqRRpSMMNRa9SXx5EKzvNUXDGhApjuL/eEnrfEqu5L3JbrKspTMatWCcHtU69k9SUeYjEL5/22/KUSuzOCQrYKm5sYDfysQd1ocC3yhJnEEQGR6JR445PjsqK3dRGBUxptyz7RMjQCwTg1viGagaq9cpMunTa3ZHwYWewj5sA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=bIBjd9iJ; arc=fail smtp.client-ip=40.107.208.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bIBjd9iJ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rVKzNyo97xAw6ZXHNx8idMqRVB9qBe0dmnhgrzAxIy3UQSCCORTdnkQdgmd2EKrAgejswt+G+m7jzngjZejjass+YhqkvSepeXTd0xrNBOKscSVCPcWHHSx4GbB4GqN+0oWkPECvnKa2tZM0Z4+g7Eg055yxGMxodSnyQrRheq/0tDT2VDlriUi2ph87Pku5yIJptG+k0lfrhUmkV8e69iCXItwWI4WutvIZx0a2qw24Mk+8chBR64KTC+yKiGSCq/aSTOBZq6TDs6KAgPbA9EGNOsHrLy0HZke22XPyQsFGjCmuHpgr5x5dsqPKFQWJuLssVhGKdAhrbThC0+xLUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uHnxk5gTlMEwwObcrUO522PaSj/dgW0lDqaTDSNRIx8=; b=gJwSkjA9HTSYEJQ5jQXr0kqFvXRV0Ta/V5cFjTYgEh3OMxK97E8C9XT8rTmU7V2OfcgptHYGx8TEPWf2Y+7rbLFacBuKucIfCxU9YD2n/puq6NO1LxUYV0Uiu7A3vZjiIzgcH45SlYoi4ELZD8EFXrYCnhgCJJP6brgVrt2PzrxFHwdG8pnM7dzXT//IGBX+3dJIq2wvDKxmKpthqDdpBfNmK5/DOlGMo8krt4/puYVfQkcKvT+TKxlbzRB/DDiJuT3mikjn1JsVrfk3AjPvI/GsvGirBB0fb5KJ0G9MpSdCzmHLwmDFFzU7I217VPCk9NuRqIvUYbrl6Rk4RF7jnA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uHnxk5gTlMEwwObcrUO522PaSj/dgW0lDqaTDSNRIx8=; b=bIBjd9iJ8vQjBHtgGuJn8m7VQMg6iOhDW/faZYqPGPII2zV78OCwW+bhre9JnPXfLs6hsodJjEAxc7RTE7O3IEYr53nxqJFm3NVX+hRIZGUWVm0DX7zqi5HXUvIN1qy0KPqMDEdnvMujIQVZ+v1ZHQ9ogw7M/SwTsjeajuQWvlnFB7terbLEKDSSeiOc4g3vVtUXGYX6IxF5/34dGSPbUc9UPMoySJ99I5/LMyd9aYEz/tqjUTHkmzuCeKx0djzRBxZA/G7RChWFEEMRpCc3fTIISj8RzIVTnFQKTd/WTxFHg/Mfpxijq5F/GKj0s5ezxyECAe7TykBKWgZSl7HL1g== Received: from SJ0PR05CA0181.namprd05.prod.outlook.com (2603:10b6:a03:330::6) by BL1PR12MB5852.namprd12.prod.outlook.com (2603:10b6:208:397::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9275.16; Thu, 6 Nov 2025 10:28:39 +0000 Received: from SJ1PEPF00002321.namprd03.prod.outlook.com (2603:10b6:a03:330:cafe::7b) by SJ0PR05CA0181.outlook.office365.com (2603:10b6:a03:330::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.7 via Frontend Transport; Thu, 6 Nov 2025 10:28:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF00002321.mail.protection.outlook.com (10.167.242.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Thu, 6 Nov 2025 10:28:38 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:28:25 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:28:24 -0800 Received: from inno-vm-xubuntu (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 6 Nov 2025 02:28:14 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 1/7] samples: rust: rust_driver_pci: use "kernel vertical" style for imports Date: Thu, 6 Nov 2025 12:27:47 +0200 Message-ID: <20251106102753.2976-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106102753.2976-1-zhiw@nvidia.com> References: <20251106102753.2976-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002321:EE_|BL1PR12MB5852:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d7bc97d-d5b0-42a6-991a-08de1d1f4017 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2PGp0tRnT7z3V/w7QKS/3yormuFfc6JHpAbKVS+sIo379g1SW+kq4EWmDuXh?= =?us-ascii?Q?LobWKqKLNPrG8GW9wHbdd887fxNIXd+K2HvpzN5YCB2+yNDptaaHXraZFWGv?= =?us-ascii?Q?lKZz+C7WeZbLWcOoHu4JiMjJOT3NHXN3DwTIoyNHQptOmwistkjLwnaHvPYl?= =?us-ascii?Q?QX154KtJKo5kdUnhOo0CnJga/1N0Bul0ZMfov2qgfXZJ+CYDybeL//7R0jJ3?= =?us-ascii?Q?8JMCp/b9pTsSGky824l29mdI0iLEh9MynJSj7oLuOCCiBtEqb7RZw7mf6wyN?= =?us-ascii?Q?3ME37+bV8j3pqdJPuWQ/owOneNHqmpKEcTz2tjHETrBV6KGgujx/0fKkjqVy?= =?us-ascii?Q?Ko/JAhpXD3fUfVdiOQYslcE84vZusErchL2IWmz+fWFnD1LqCqoYbb+yNMDt?= =?us-ascii?Q?ZOu7r/XyCbMyPKifsG4GmuMZTsBSKz5/VpEZp22hy+Clx/xHYxXcq0B58f4y?= =?us-ascii?Q?4xOTFySVp8uGq1BlXacSDZfT1Ah7YcRHVZclOtvvNdLEftZdHwMu2KqkJr91?= =?us-ascii?Q?vGx1uZWcwjLH+GISlQ9PZGcdXC/sq4nDwbM014Nxd/jNwgZCrMVbBa7rBFTv?= =?us-ascii?Q?CbcmTIe+4Io3Dh3jaICaQHkdvTUUP3jR24xZry1QQwXnke5mjgsPxkgAm59t?= =?us-ascii?Q?Fhu9WWtgMXScDCO6s1OSRI+8gL1XPUIWpuKDM/2YkgZYKi2aSZbKMSPdYynR?= =?us-ascii?Q?ByXe0gsVFo/0qwLRG+PZ2nE+bZAxvR0CwI0YYAqLqdTdWpKMIXmETaduc1zU?= =?us-ascii?Q?VzH25PC8fAyIvvbEE7wAmiEwHu+w2tFRZh5/VMhCBz1NG39kbpNfdnoZbNkJ?= =?us-ascii?Q?QYW228QHNn0RzGe36hptAIh5RQ7GtZGTyDlExymD60n42EFj/P1jSAumVCqg?= =?us-ascii?Q?4OWyyfI9I0dpvLAClgeC1O7XmS7s4dkhFclWlG8bid6kcw+zpDOCLQwrbWQL?= =?us-ascii?Q?HVzTetqVZSALKTLe20oI47fBLMOT1u1zcQUBncOOnCirPp64ZFGaTr0RIMi/?= =?us-ascii?Q?d/gynyWewUQgFsQblXYh0RWKGxSplZfJFr/jftYH1bg3EIyaQNcPt+1SExFv?= =?us-ascii?Q?FCPUuHpBPrUY5DHTvESDOtNoxnCkxLsGMvYOD0CdusowLNxlAf10PPbYXdeX?= =?us-ascii?Q?u/88YMljhnmX2z/fEcJzyqa7jXp6ZIy0YVVAtLSsPs2al2azgm6fb9dn4jtu?= =?us-ascii?Q?z/4j8AMSdCnBcqSEUZpT/J/1eXBzC2r0IBTRWQVCXPNnRGI1lNZkznbNi0G2?= =?us-ascii?Q?Gu6cLug5hpt0/2OCyupX06eDsmNGiccrgOQphX8dLirWp6O6Y8ERp49tLhq9?= =?us-ascii?Q?irJVA+5DwWZbkcykUS0rmgmtmGr577rwyI1urSFJskbO2cf5zoMWZyOodAUX?= =?us-ascii?Q?4SFymPWkj7xF+RkyRLc4qVxXRmxvBa4dcnb+noN/AjALrclPSRDretua0azH?= =?us-ascii?Q?riNqCE1AdpixlUDM/F5je9T4t6YN34z1GrZ0oZ9SANIqE601s2fTCC8nUqZz?= =?us-ascii?Q?eP8HxtrBV6pnMPG5sqKXkXAJ/3EezX+Br9MCtnJrpPST9QwmTfX8upQujgT9?= =?us-ascii?Q?2IpWWx4kehCvgtqLRno=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:28:38.9093 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d7bc97d-d5b0-42a6-991a-08de1d1f4017 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002321.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5852 Content-Type: text/plain; charset="utf-8" Convert all imports in the rust_driver_pci to use "kernel vertical" style. Signed-off-by: Zhi Wang --- samples/rust/rust_driver_pci.rs | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci= .rs index 5823787bea8e..ee6248b8cda5 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -4,7 +4,14 @@ //! //! To make this driver probe, QEMU must be run with `-device pci-testdev`. =20 -use kernel::{c_str, device::Core, devres::Devres, pci, prelude::*, sync::a= ref::ARef}; +use kernel::{ + c_str, + device::Core, + devres::Devres, + pci, + prelude::*, + sync::aref::ARef, // +}; =20 struct Regs; =20 --=20 2.51.0 From nobody Fri Dec 19 15:48:09 2025 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012040.outbound.protection.outlook.com [40.107.200.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E42362DE711; Thu, 6 Nov 2025 10:28:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.40 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424935; cv=fail; b=UWsiu5uz6ndj20wDDBuo2lc1oyYYm554bRNEtRB6nVfXrRMpzHBZlQZO29Nxk3bDAzJZIwG/IiKhE4YQN7WttHrl3qcqi9r0JyCWxaT/EfuHVtizafeUhYVexz5V4PRIBBE+xEJYEQW6z2Xtn6yI1FU+AlrgdYeApFQnQCzKpv8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424935; c=relaxed/simple; bh=tKDBxG3e6MoAesYciefNra/nh4DPjrp8k4A2slrdbrI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JpASr6C+3xXIaaeRSUZBGgSo6NAgZQ4ouNySHUD40Y9HqQNaEiLnsgEG5b7tEQ4VxXqnhdnoZrc0KPD18BS/oqyKmFMGdqscTp6Tv66JOlhKKCaYAj3iHtPJiQ0nK0kXVXAKVfSdp8UsHbSeiMSPWJ+8stw4Q4/JvKmcaCklGLo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=cW+sLbxJ; arc=fail smtp.client-ip=40.107.200.40 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="cW+sLbxJ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=t7x7KPBnkMa8XcLBn3Yqr213Jj92OegIGsLWfV6bhJXFjA1KuF679bQQrJi2J1o6VD78pIwSKNzGFhHCrBlT+x959TFn1YB/WSqwp7kAlMjPcS0IfU4xwNc9qIYVToCPeNCllnp51LrbOQo86ODD/BrZDcA63882FgmiQ0XS1+ZMOWDDDk0M4gMfb9KcZW9fAA4M4+qaOZw793Zm9p2HKyQbBGZpnZZYQuzEoq91iHbQo1IWweoVOiNSye3g+x64kI8Oflp6UaFMKxI3HR52ZqNp8ZlMff4Rs90N4tpPstjUdsbm6g1p5CQCyBVSL6V91isEtS7lF6bkkSa4W3fmDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=g8r/7njniFBJ58aIWqD031fcvnWshNpwknOtcJZEWxs=; b=J3xy2toWyBjkdq3pG3FU5VrdEjo2pg86NCds3++iFHAk/WKrmszhnA+tXCwKrd4O/BPgy/fm24ZYml8SFDPanz+ivbUisIDz9Z3/mPiwZIYcM/mJxKtCAB6cL6TBxQnFy+GJDuy7NguJ7QVHARUd1IUseRYPQOFBq+U59dF4/z6OAP1LkzGweZhrhLMGxiaLtfEfAhYJqnOdlYIl+E5xKQDXGEGctjm+vQb6H9JRoKr3j7rY3kGULbNBPNQcnpCf2cXGoUIRQnmFpH43Q53JZuA3BzbiJzxeTN8isC35pmHCp8iSMgQQXNvKtJsRUhGcGibiE+S3/oKvkbDB8F2teQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=g8r/7njniFBJ58aIWqD031fcvnWshNpwknOtcJZEWxs=; b=cW+sLbxJ016rtwiD0cP2KnBjz9wmcCH5q4oPCdB5abza2sh62T0sfhvZizOc8mYxUlOn8s/Q8ovm48gNNNxeBaIVipy5rXEAdup+gKJq85y2uRjhctVG0mtD2yM+KJfz79gi6fJPqcvl7YDoG26Nn6GOrBMUhCFdvSARagXE3cNJfu+8Akld0ZrqsKOcknt93pvblaZpZEO0/cKpMQWCDtjnv2zJ7GNmMS3aUzk/hJHkp6TrtFp3dQm4cHrczcHW3XvuW51GNFKSRuKH1OD5spXP25MY2lF4yYasFU8cCqol2rZvQqQiAJGRNU41yRZTIK+YvhAC5y5hGsMgmFeYLw== Received: from CH0PR04CA0050.namprd04.prod.outlook.com (2603:10b6:610:77::25) by IA0PPF6E99B1BC1.namprd12.prod.outlook.com (2603:10b6:20f:fc04::bd1) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.8; Thu, 6 Nov 2025 10:28:48 +0000 Received: from CH2PEPF00000146.namprd02.prod.outlook.com (2603:10b6:610:77:cafe::e) by CH0PR04CA0050.outlook.office365.com (2603:10b6:610:77::25) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.12 via Frontend Transport; Thu, 6 Nov 2025 10:28:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Thu, 6 Nov 2025 10:28:48 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:28:35 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:28:35 -0800 Received: from inno-vm-xubuntu (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 6 Nov 2025 02:28:25 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 2/7] rust: devres: style for imports Date: Thu, 6 Nov 2025 12:27:48 +0200 Message-ID: <20251106102753.2976-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106102753.2976-1-zhiw@nvidia.com> References: <20251106102753.2976-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|IA0PPF6E99B1BC1:EE_ X-MS-Office365-Filtering-Correlation-Id: b577c515-4c52-4845-a8ee-08de1d1f45cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ENxH5NPFtvtzhuuQhpaEAcFWsaUeag78iwkJS7RsFj6E9PH/9dy9voUzka/P?= =?us-ascii?Q?BeSwQwAlx/5j9Lc8tErB/pi5Y0DRMKK4LKVxSHbmugn9dD96uckym2kb8bhk?= =?us-ascii?Q?oH0L2MJLQYCVmBZ7+OfyHZzMER8Zx6J5FvBE/GX11gvHmPV6q/fH5iOawPn+?= =?us-ascii?Q?Ywj/JYBlo1x0pRYYMSZ/BzZ/Rju4IIVB5L3zPTaRw+1k6oeT3AaM6CfJ9U6Q?= =?us-ascii?Q?LLLT6adCFzApbpeEH/27sYKy8tYf4L7tMeIBhaQB7Gfk0KFrI08AfkPnd4S6?= =?us-ascii?Q?YdzO6BwMvoJPgQ2HjmU8DDlxeUMq5eEcvl2jwq3J93M0/91D7DmiYSeIX1d2?= =?us-ascii?Q?2T5kDmjEUpwJLqs6otwoKdWvCANplTfD8vEn0NFrZia0Lhn9syrQB4cwPUu0?= =?us-ascii?Q?FYuFEWJU9r7v/JGQ0aLCb5vqltRHCT1E5gAzLe+pU+ySemHr9LJzYmCHR9bm?= =?us-ascii?Q?F7QOCLcg5+4ZJG6lPjzogOBWuvDyP9G/XViVoUmF2s70bJsxwrQg1odBJb7k?= =?us-ascii?Q?A7DSf3Oi/NRhXKGJP6VzzDAJL05UlVM3WoRRKykmtn5TruD9zYW528UIrX+R?= =?us-ascii?Q?UtVVoikJj0lY4K4LZJqursoWVZxv2xG7MctJyROS5XPLoz7ZdkNUBMeEDamG?= =?us-ascii?Q?rXjDfq/h3sgvM/DSPsO96JOx3mK6m6OvQ4fo8+MJ5xDPMl1etTia5lRUGF0G?= =?us-ascii?Q?7xTnFXXKL/327aT/FZ8hOIB+ylm9Bsz9f88RwuK2eEDxdyzAMoLL8O5udhvP?= =?us-ascii?Q?GW5ORp5wrRGucZKQItiu2QcknHNUc9PTYWVdecc/fc8Sebt3CSooRDwW17/W?= =?us-ascii?Q?PSUhEQo4erdovdV6fRXbcuZ2k8wwKYwi4GMmUnSmV4kpUcb5zn8bqzntho/C?= =?us-ascii?Q?UWULUfJcgBIvXiu1MNsioV0odGxyF2dHWGSW8PL+/1A3gF8cLsi3ymb/C8pX?= =?us-ascii?Q?R6YMXl8aRxvi/y8tBYMnO7xAW+7ZsidthIL7NieLJVMEVlQvuk1qoa/FcYQ9?= =?us-ascii?Q?iq1jn/+6T9IdVFhFcTJL6wg8IcRo+cJ3RuLohvk2k2g3q52+gC5rLklfoiC4?= =?us-ascii?Q?2aFzpSJ9PXxDftYykC1wK2FaY0foVN12oPoWn4KIv80vn1Lmgwmh53VgbEzg?= =?us-ascii?Q?qWPO50Nz6gabD5ZFXP14Um3Jz1YAQeT08ABziLl2r6owvpAnCBGF1TnNEzIX?= =?us-ascii?Q?ddSzDRy4fsp6UEcDJEvPEQiFVrjcqB5zvsJfwLIYBuJkDMoVCcQ6iKHkE0bp?= =?us-ascii?Q?kshDYclg06f84F0brKFb446DJPQdqdLoZ+sVcCZiGTRF5fZj0BlOzi4706/z?= =?us-ascii?Q?mhgfkJdzezK2GKuhXQ9CWDYtqkw/AiXK3Ob+dQSP9h/rUYsh7HYvUwV8wNqo?= =?us-ascii?Q?yOU7xxP/etwvxmD9GG0I1upAriKU/+mQO67vFTlaXhkFXVjbQZNK5Bdl5GNl?= =?us-ascii?Q?Dzt+zyt0AT1Eujs94obKzQ5fd7LJ+wUsTpQwpB7ofBmziMqiT2ucYuKvqY4N?= =?us-ascii?Q?HGyKK+GZrkG06713cSadocLRvgZsBJwGHOa9ZWJOgNFODm0xMASZCwg93/+M?= =?us-ascii?Q?XUk560LGMLeg7/HEiJA=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:28:48.3968 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b577c515-4c52-4845-a8ee-08de1d1f45cd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPF6E99B1BC1 Content-Type: text/plain; charset="utf-8" Convert all imports in the devres to use "kernel vertical" style. Signed-off-by: Zhi Wang --- rust/kernel/devres.rs | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs index 10a6a1789854..d4f3169248df 100644 --- a/rust/kernel/devres.rs +++ b/rust/kernel/devres.rs @@ -52,7 +52,15 @@ struct Inner { /// # Examples /// /// ```no_run -/// # use kernel::{bindings, device::{Bound, Device}, devres::Devres, io::= {Io, IoRaw}}; +/// # use kernel::{ +/// bindings, +/// device::{Bound, Device}, +/// devres::Devres, +/// io::{ +/// Io, +/// IoRaw, // +/// }, // +/// }; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. @@ -230,7 +238,11 @@ pub fn device(&self) -> &Device { /// /// ```no_run /// # #![cfg(CONFIG_PCI)] - /// # use kernel::{device::Core, devres::Devres, pci}; + /// # use kernel::{ + /// device::Core, + /// devres::Devres, + /// pci, // + /// }; /// /// fn from_core(dev: &pci::Device, devres: Devres= >) -> Result { /// let bar =3D devres.access(dev.as_ref())?; @@ -333,7 +345,13 @@ fn register_foreign

(dev: &Device, data: P) -= > Result /// # Examples /// /// ```no_run -/// use kernel::{device::{Bound, Device}, devres}; +/// use kernel::{ +/// device::{ +/// Bound, +/// Device, // +/// }, +/// devres, // +/// }; /// /// /// Registration of e.g. a class device, IRQ, etc. /// struct Registration; --=20 2.51.0 From nobody Fri Dec 19 15:48:09 2025 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010042.outbound.protection.outlook.com [40.93.198.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B483727146A; Thu, 6 Nov 2025 10:29:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424948; cv=fail; b=P2FEfGzoFe/tueiuzD9d77ZvOJ9qaI2elLY3eBHazt0zqRfSfEYP0lVQ74qA5hcui+mJQMuHf/07ytAEzyy8AwwoAbXks0HxStIkB5KvtWKb0YcS23dwNOaUKSt2GBRTGCksjtFHxHkwCJafcZKQkd7jgDTFtRS5aNR7ZfWQ4B4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424948; c=relaxed/simple; bh=1ey69uQ52DpCkFl4X6o0l/HSpZYJI/4HTWB2yK2xweA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SmoRztJju8ypl8oWo6P1sQcmITYV0+MFPZE+WrGvmqr+8Rhu4VY8xfJre2CnkQW4tonBO5/C6hFNlWQesX5jX5Gy9+tlnKGv8GL1r6YI6qn5zYa5Z19Q9z8CiNxBjQMBYrODx/eKgUx5Dr5oYHoVo0gMpNuzvnFnNMiUDy5otf8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=F5d4tQAh; arc=fail smtp.client-ip=40.93.198.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="F5d4tQAh" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=bA/SKDMwxvRGTc+zU0pZoNrD2klXZebksWkRWOUDYn+C79uT/qTiFmPR7sqbc2YLXXe6C2aUL92ClV+QhcYnS1kxTtkqvHlXdIa5OJ7oOr9pY7/iQLa/jsGOOvXM1qEe+Qmr8F+uT+/qwB50L+MLu4gF15Z6HEyHvaNvCsFLdDD0jYox585pod4GWSe4npTDJjmQpdmx4h1fmm1hTdnjvIy58RzEUJp1u6lJJLhiGv9LfG/HjC5R9EQ6z1lcUsAKjcLagLIJmqKpkTxMJLOk7JOV08WbU6Fs7/SIYV0Sl6bpeHUOhv4p5uTMR7LJyhttq3qPIiljDlst3nedaR0lSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UNQ+uPcwG3K1Zou3EZfp/PaCvV+74n+fUoGFaKlIAQw=; b=olmiv749JooAgxp93BPFIqXBRDTf7Erhgh9kqb5xTtCFE2F1tKRjfyHSqDjERJDYi8TToIF/lLuKQ69thaYDB/1xZ8CCFc1NVH3aFrIpPmM61W9M5wg555IHiLpSTR4Taj22qpbyiikXf80YYhPmsmeCJtmvlsL+LU4h7zS7jbNO/AdtCiODO7/DI1C6m6Tijobhqha9b/O/nlU22y+2cOgohdl+bdmSkaXJrQ46CxQIyNq7b13PSm7dhGw9Hc1/oL0C8h4oSrNz90sCmNdgJia55I/paybbB678iEDESsrtOgDtOlcmzah5rgwVkJ/8kPQibE5X3IODFBdo//1Jxg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UNQ+uPcwG3K1Zou3EZfp/PaCvV+74n+fUoGFaKlIAQw=; b=F5d4tQAhaAmxyEc50PsxX+WTAgbhI1YXNNt9BBc1eXZ/g7RXX22hotzt2jhJRq+Ev24rE1law7DFUVCKUdDnH1Ppxq+52SoQJ+2Fx+UCQav/0Pnt9iHG3z5t1YpvxmU5VKq3ITPbziJobJuxQ8EY5t9NEmte2oOYk6I2qwVpz0VQrWJE13vUFt2wGB+KXmEvmLcnpPzn1C1gCsGum6Z/jdpnaXkeqIYN4QdvQuAHG631h34qOYMMvRk3qy/W8wAvzAKgVEux6qiDzedR1QjLRCLT37YYAqGFOQ5N48mxbWHHkIB6Q/XjpRNruPaeHH5o192d3jICAJxvGfi8L2L3AQ== Received: from CH2PR16CA0004.namprd16.prod.outlook.com (2603:10b6:610:50::14) by LV8PR12MB9271.namprd12.prod.outlook.com (2603:10b6:408:1ff::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.7; Thu, 6 Nov 2025 10:29:00 +0000 Received: from CH2PEPF00000148.namprd02.prod.outlook.com (2603:10b6:610:50:cafe::34) by CH2PR16CA0004.outlook.office365.com (2603:10b6:610:50::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.12 via Frontend Transport; Thu, 6 Nov 2025 10:28:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF00000148.mail.protection.outlook.com (10.167.244.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Thu, 6 Nov 2025 10:29:00 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:28:46 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:28:45 -0800 Received: from inno-vm-xubuntu (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 6 Nov 2025 02:28:35 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 3/7] rust: io: style for imports Date: Thu, 6 Nov 2025 12:27:49 +0200 Message-ID: <20251106102753.2976-4-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106102753.2976-1-zhiw@nvidia.com> References: <20251106102753.2976-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000148:EE_|LV8PR12MB9271:EE_ X-MS-Office365-Filtering-Correlation-Id: 302260f0-694c-4064-f34c-08de1d1f4cd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KYv6B32UHYqfedW51Hku1k8QXCIAySTeiNXy+RsD4zf79aWUURbAXCz2b7Hk?= =?us-ascii?Q?sK/aU/rt8e7RQTfM9xKPmRRbtRRfoJl4GJY5RyD5aoumf4vQqVwennASZA/2?= =?us-ascii?Q?ehJaskfLqNjxQymzHSk//MguVV3HQQfw651H+i9+Z2Hvy10HoqkhL8ieTqYm?= =?us-ascii?Q?2Mf4YMRPKpR2Cu3k5I7IAni+0cJWUn62CqWTun3nrl9j7e/GivSRPbczhPRO?= =?us-ascii?Q?TR3QoGQnuhluAeflrmd/Kbnic+RW32oa9k8vgeeTWVUV2qLZ/ISKeMI1kwLV?= =?us-ascii?Q?gSBPiVLe2y5VDlubs6sigdEnnZax5/SLvUe2nuWa/sYVkJpDA62jaoSfJK6l?= =?us-ascii?Q?wfpTkkkWYgRFFpglNaB5NmROfjf5q/O06KD7rVfM1egjXaqQYDDZ/IcKVmJ3?= =?us-ascii?Q?1UvkcBDFiNzvA7xAaJy8SoMhD2//7c2yaMtTzgZ1fnuqMUDa1Nnn7rJuOPWK?= =?us-ascii?Q?lRcB5mHKCPJYLsSTzXhZu6NViQRb/ukp8cuJZvDg4/JHv+jqt8PHkaHeUPbF?= =?us-ascii?Q?lLukONhoNriJIRYw+YUhzbYKKCU+DGFcrehyTYaTy5XcDBo67L0cb5kq7m1o?= =?us-ascii?Q?8AMwcTyoBH1EBK9kl9gM237kwUWihKnCCLxdLKjZZ590HMP29t6BHK7IUAmr?= =?us-ascii?Q?ILNZ+CnseDgyqE+Qhv7KJV3cO06lalMW3qSob+9AjZUJJi27acrGPi1NtOHO?= =?us-ascii?Q?BP/WmWdMbPWv8v/UmTQ1j3ZAsSca1P9o1fSARfcmxhlj5UcJ28/YwY6aivYw?= =?us-ascii?Q?AYa9xNLxqIXnMLxFCKOCpbRd1sTa1tO3OzeDahdZ439Bt/TZcAxJBfPFr92c?= =?us-ascii?Q?SSJN7P6AuQ6IQxJQBNwc20tpOfPzi7jGr4K6Axs1MoroOZ+kPeAurZK0JaFQ?= =?us-ascii?Q?2cVosqNK+Qv2umks38cPtfrNj4YdkWCTBDEII5l3XuaicG4jA/xg7HaSIS5P?= =?us-ascii?Q?7qhFR2ocfaLctYiZTo9jKqoX8mTdl9fRqUNEMCquytcBjxWVU4mwwK2Es5KR?= =?us-ascii?Q?+3Y177RfjEBLKuAmtKloVKRxKyGhc21kvxVO7kL7eLW9uiTDk45Gkf7QWt2G?= =?us-ascii?Q?t/b7G1jQ18lnhTnvGTXl1iDy7b9TonW2dY+HRv5qhviwJA9y9k5P+trHxtLi?= =?us-ascii?Q?cIKmbQnv5cfpiNxMn9ZSGVx482tiOV2GqNaUuPgfG0hw4P0iz7cDdXz1veP0?= =?us-ascii?Q?7tlNlCLnRcLJCuD5RVLng+MWparNRa6t7sjTjo8dHNZkU+MLQq9bosnqw6XQ?= =?us-ascii?Q?Mo/jN6U1fJmWvlGHfCFC82wACCEt6e7ldFb81qPEwLz+sVLpSDP7qeh3zVkm?= =?us-ascii?Q?VL/zgIg3scaN8z04rKClNQ6froUPV7JhEf7VDgekwOsC3Jav89LeicvKbdvp?= =?us-ascii?Q?kOcRdVrIxw0EL7ISSFv/xg/fSVDns+wY6nHROsubz/CWBCxhdZzt8gus3J+2?= =?us-ascii?Q?APmsLbJXaADFSp3d/1MERgAu2wIWgHGlTk3FPezvktgmhowQnUqO6sdaGOOY?= =?us-ascii?Q?cqGt8A40clfH+dnSkSKcdI282d5+DeYfEv3o3w4HIh4lgxL41CBld1mI3KlT?= =?us-ascii?Q?q8KrTfARTAjQLDnhllM=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:29:00.1442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 302260f0-694c-4064-f34c-08de1d1f4cd7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000148.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9271 Content-Type: text/plain; charset="utf-8" Convert the imports in the commit in io to use "kernel vertical" style. Signed-off-by: Zhi Wang --- rust/kernel/io.rs | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 1aa9495f7774..6f1e22613f8b 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -64,7 +64,14 @@ pub fn maxsize(&self) -> usize { /// # Examples /// /// ```no_run -/// # use kernel::{bindings, ffi::c_void, io::{Io, IoRaw}}; +/// # use kernel::{ +/// bindings, +/// ffi::c_void, +/// io::{ +/// Io, +/// IoRaw, // +/// }, // +/// }; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. --=20 2.51.0 From nobody Fri Dec 19 15:48:09 2025 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010017.outbound.protection.outlook.com [52.101.56.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A39122C15A2; Thu, 6 Nov 2025 10:29:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.17 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424969; cv=fail; b=ervR03+PVTAs5Nsgdyqxz+eFtkBln81fkS+uRBum9LENVsBFeFLkHb605zeRy5ZyWDeIt/BsdHh4sKjGm/ohBbD3YwB6ImIP12s7ej1J4/jjeLaR4aJbREkojfKVykQ1QhDp/8g5wsYp2kJd1A9TUnN0RalggAtPhd9PqlL3h/g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424969; c=relaxed/simple; bh=pJU6Dsl2Tt2/lnQwq9Wbd2VjQt8qltIJCeCOJViHvXQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KfH78rwg8NxGXme2s1Kr6zdqlR5hfqO/PX5OzGnul8LsRVAZLR/FZJXAd9c86+m7WaepxZXnkw746acLWH2ib3U6v0pR4BajPQvRD7jH3mGtiQ88sxN3s1Rz+yLTRC43KHFKLQgoQGVGmu61mKQlh7NSUB7xl83/0xO0ffVmDV8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=PwtU1aek; arc=fail smtp.client-ip=52.101.56.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="PwtU1aek" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VLSkqedEH7C8/OMFqJACl03OtBfHyKpj6oSeY6bMGW5rwojjcnWl+Y8odLFhvh4ZcB8sdpgaOMZeJQEJk+Qw1fdpDFZvrb+uPjHnKKO0oWY/jCnOovPQXZn85Pvl1yvnCCIsB9ZPhCqzpp4v51SbzYeEzg/1SilqCD/BTabd9Pn8zQvpTGM91SN0Lg9b1BLDUt903CS3RdiLUSHPzddEI5Kdl4oTHYBnzuRJUuHFnYvVl42m9vaX1paYnilnYGhGl499Qq3QO/K/uTDa8it6jmta4AsOGv2ibHpBj9rtm1sQ2uNihqW7LNlGY1vMGV2w1VhaEF0JwNrGJAYaX8bS2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+0RIm8YSJNe0G9DEDfigAb4Yyr6wgLjX0gnDeeaQ9WU=; b=Scue137egWYA09zxTCalOPTIV75bBl+YrAm6umyUN8tjU9nkWPyGdMDXHuuwFc7c0hI20q0Mlso6zelJWdniDPLUj90RaASbOXC6zdQlV9N90TNc6dQT0wLxsIkoznzh/mzFkB3P2zfUD0QAYajFCwtWMVlaWTk/esPb/7cD2bgHYtFGJPRtY2GV1rdSHmJkCbyLDdqbqST93E4RI12JN0Kg4/J6ZFW5t6UfhHsQ7KQZMn9+Dku8OWaXUsdUWHU2Y4DA2djHuhtqJbP46okerMpJ30mh0KcBACWR4iFLvkjAKZS+9+L5hEcefYTf6iiclYr9u32Qy6LGTGPkQqZ8AA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+0RIm8YSJNe0G9DEDfigAb4Yyr6wgLjX0gnDeeaQ9WU=; b=PwtU1aekOlEOYqedBeWtFJh7HzsJ3MZSH4qr1Gd1yfSLEqNgcjMJPfzMCjgOm6c/vUYHi5OB1oAWomL7qOI4VRBbvVJD9+9/JW8AAuZFsuHc15i6epAu5v3N0mF6ZKxzDLblKmcuQNPRQivtyKNHfnvOiAv8PoWrkeBJoYvQbFv5KEAU2Gf1jAAj72Rtkuet6GVceWM13L+JsSICyyZWbYXQuFBXsErj3g8ZqXo3VmFHygoJ8ap4LelQbB7Qrz4KxKCH3jEt5Bzb44hw5oTIaIC2NufCvbtuYFh8Myur1SYdk7KQH5cFO13iDt1537qTqLBQTdoIy/6XPLb2GTU30g== Received: from MW4PR04CA0388.namprd04.prod.outlook.com (2603:10b6:303:81::33) by MN2PR12MB4221.namprd12.prod.outlook.com (2603:10b6:208:1d2::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.12; Thu, 6 Nov 2025 10:29:15 +0000 Received: from SJ1PEPF00002323.namprd03.prod.outlook.com (2603:10b6:303:81:cafe::32) by MW4PR04CA0388.outlook.office365.com (2603:10b6:303:81::33) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.9 via Frontend Transport; Thu, 6 Nov 2025 10:29:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF00002323.mail.protection.outlook.com (10.167.242.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Thu, 6 Nov 2025 10:29:14 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:28:57 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:28:56 -0800 Received: from inno-vm-xubuntu (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 6 Nov 2025 02:28:46 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 4/7] rust: io: factor common I/O helpers into Io trait Date: Thu, 6 Nov 2025 12:27:50 +0200 Message-ID: <20251106102753.2976-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106102753.2976-1-zhiw@nvidia.com> References: <20251106102753.2976-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002323:EE_|MN2PR12MB4221:EE_ X-MS-Office365-Filtering-Correlation-Id: f3d8477f-da56-4055-8f7a-08de1d1f551a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?9a2xdVmoBG2R8SUrBWbEXTBkAh+VC36DEaoD2XMmulI8w6HndUIy0Uiwfl9o?= =?us-ascii?Q?ZoweH4UhBXTUs7pWqW9vraQLB+vWSeKdMqTyJX+GL8IGCYjCEgpAEp+pSoks?= =?us-ascii?Q?r//73VjVtfAMz8DCs/94IahH6f1TAbca4KDgJP5PC5ybSWMu0pNb/w/NZYNw?= =?us-ascii?Q?sJ+yo1qoLnEjwzg/ypVDP+pvtkjpV3/nL412HVXdkRcFeEL8VfWLo23xnvri?= =?us-ascii?Q?DLsCZXBH6XV3lS86mi6A5MR0vu2vgQY3Qzzy2CEcQ3zvjutm81wyM0fwLUUu?= =?us-ascii?Q?uoiDikNbKrnoML+wKQLacu8VtRfcf8g2teB8aVa+AXAenGCVR+s6BuZiNgxq?= =?us-ascii?Q?fa55HJijzkwzE+hVTYpE70b9OrXP56Ig2m+F+9eLav6pdIh7aSvV8xlqcAvV?= =?us-ascii?Q?/99afvPQGK3xQgJI/nZWiKKhXjxBkYfuXuk9+VUk6siHad8DkWXurjpZJkAs?= =?us-ascii?Q?m1X709VLTe32YGK9+d7qUWRqr9Y+pVYBnHt/C4PiITdJrficrCxPeET3aAmz?= =?us-ascii?Q?eAmlpctw+fRh9SIgQD5iNaqbQB6f2GpAMPRrlYRuvEbiES4MgGa7LU/hq2xH?= =?us-ascii?Q?MZSHPaFadO158eBsQANcH9o+AloI6FBaSr7afft8xVD0GLQHDjmRDz4mMFUW?= =?us-ascii?Q?TRpYYvzvyVD/nbG9KK9cgoFDrgVHVA3/IzGx9kjPcwqAY1dpqUArPzDBC1Cn?= =?us-ascii?Q?TEz69by3uMdyaslvLzqLv0c90caqe7QR73H+khf0ipy6n1Dr9CE2vfZHDTdx?= =?us-ascii?Q?oMTb/3jieIlj32a3++3KkKm9za4sAOmBzyJ/Qm7+celXgQi6uNjCDYxGO7et?= =?us-ascii?Q?RxAJ+zguChHA57bLOX1k9Cyvgrf6RBOWpV08jh168pyytR/irA34+uGhKqq3?= =?us-ascii?Q?YucRzV+DE/rHfDqiE0e7uWqY1E9Q9r0HvinEFhW04TVY0byizx9spGj6V2VF?= =?us-ascii?Q?KfuGcdDr2KaGRtk0cf6JIXQaPW4fkd2NNoGHBauHhEztV7yJp+95zADpE5ax?= =?us-ascii?Q?aSHuZZ+uaONvOoE7XduWKDCyeL+Ng29WVcrQ57grS292Gx3Lako/ynLNKtP1?= =?us-ascii?Q?tiJxqwKtOInXyzgT3SKr4B0wG0q5NvCFmNaZfyeHwJdmDsioJ3dbUF9F/AfM?= =?us-ascii?Q?VTDOFKg8mV4lMF7CkcmWtQe0UN/CRHEGLsd0vdr4QwD6kbvaaa3yHY6gv57x?= =?us-ascii?Q?CZpvzdktGlz6WCoO6slgt0ncgZsW19C10DFMAzSieAi64OIf6+Kun/ebH/mB?= =?us-ascii?Q?GU10ap6gQox7VWletJ3jbhX8rpE74NGoHd4zC7Myy3jppBeZcTT2wCqv5dMc?= =?us-ascii?Q?Zv5Mzzf7a4GtsmaWKwcvQNJQY9q9vlb2DS3u/bh0ZbYbVJk1UmrLmEeXEO2P?= =?us-ascii?Q?QVCzLVIU56ckof2oOhUWdAiiUGjl7szsfiQAxjiSRfGGIkl8+t+BwnAf0DLn?= =?us-ascii?Q?miIDRVMPVXwoTU3AWfRuFvofMsRMgB6CKP7HHsRaoJ2qQbI/69aCmf1CvvIB?= =?us-ascii?Q?dhDKDqml9gGyXNxH7yaPjB1UbD4ULNaYtPibUqpfsuF4RBslYhPjbVQRDenS?= =?us-ascii?Q?gDWVL8UpCParS2h5kyo=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:29:14.1904 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3d8477f-da56-4055-8f7a-08de1d1f551a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002323.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4221 Content-Type: text/plain; charset="utf-8" The previous Io type combined both the generic I/O access helpers and MMIO implementation details in a single struct. To establish a cleaner layering between the I/O interface and its concrete backends, paving the way for supporting additional I/O mechanisms in the future, Io need to be factored. Factor the common helpers into a new Io trait, and move the MMIO-specific logic into a dedicated Mmio type implementing that trait. Rename the IoRaw to MmioRaw and update the bus MMIO implementations to use MmioRaw. No functional change intended. Cc: Alexandre Courbot Cc: Bjorn Helgaas Cc: Danilo Krummrich Cc: John Hubbard Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/regs/macros.rs | 90 +++++---- drivers/gpu/nova-core/vbios.rs | 1 + rust/kernel/devres.rs | 14 +- rust/kernel/io.rs | 264 ++++++++++++++++++++------- rust/kernel/io/mem.rs | 16 +- rust/kernel/io/poll.rs | 8 +- rust/kernel/pci/io.rs | 12 +- samples/rust/rust_driver_pci.rs | 2 + 8 files changed, 277 insertions(+), 130 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 8058e1696df9..39b1069a3429 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -608,16 +608,18 @@ impl $name { =20 /// Read the register from its address in `io`. #[inline(always)] - pub(crate) fn read(io: &T) -> Self where - T: ::core::ops::Deref>, + pub(crate) fn read(io: &T) -> Self where + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { Self(io.read32($offset)) } =20 /// Write the value contained in `self` to the register addres= s in `io`. #[inline(always)] - pub(crate) fn write(self, io: &T) where - T: ::core::ops::Deref>, + pub(crate) fn write(self, io: &T) where + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { io.write32(self.0, $offset) } @@ -625,11 +627,12 @@ pub(crate) fn write(self, io: &= T) where /// Read the register from its address in `io` and run `f` on = its value to obtain a new /// value to write back. #[inline(always)] - pub(crate) fn alter( + pub(crate) fn alter( io: &T, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io)); @@ -647,12 +650,13 @@ impl $name { /// Read the register from `io`, using the base address provid= ed by `base` and adding /// the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, #[allow(unused_variables)] base: &B, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -667,13 +671,14 @@ pub(crate) fn read( /// Write the value contained in `self` to `io`, using the bas= e address provided by /// `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, #[allow(unused_variables)] base: &B, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -688,12 +693,13 @@ pub(crate) fn write( /// the register's offset to it, then run `f` on its value to = obtain a new value to /// write back. #[inline(always)] - pub(crate) fn alter( + pub(crate) fn alter( io: &T, base: &B, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -713,11 +719,12 @@ impl $name { =20 /// Read the array register at index `idx` from its address in= `io`. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { build_assert!(idx < Self::SIZE); =20 @@ -729,12 +736,13 @@ pub(crate) fn read( =20 /// Write the value contained in `self` to the array register = with index `idx` in `io`. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { build_assert!(idx < Self::SIZE); =20 @@ -746,12 +754,13 @@ pub(crate) fn write( /// Read the array register at index `idx` in `io` and run `f`= on its value to obtain a /// new value to write back. #[inline(always)] - pub(crate) fn alter( + pub(crate) fn alter( io: &T, idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io, idx)); @@ -763,11 +772,12 @@ pub(crate) fn alter( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_read( + pub(crate) fn try_read( io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { if idx < Self::SIZE { Ok(Self::read(io, idx)) @@ -781,12 +791,13 @@ pub(crate) fn try_read( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_write( + pub(crate) fn try_write( self, io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, { if idx < Self::SIZE { Ok(self.write(io, idx)) @@ -801,12 +812,13 @@ pub(crate) fn try_write( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_alter( + pub(crate) fn try_alter( io: &T, idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, F: ::core::ops::FnOnce(Self) -> Self, { if idx < Self::SIZE { @@ -832,13 +844,14 @@ impl $name { /// Read the array register at index `idx` from `io`, using th= e base address provided /// by `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, #[allow(unused_variables)] base: &B, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -853,14 +866,15 @@ pub(crate) fn read( /// Write the value contained in `self` to `io`, using the bas= e address provided by /// `base` and adding the offset of array register `idx` to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, #[allow(unused_variables)] base: &B, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -875,13 +889,14 @@ pub(crate) fn write( /// by `base` and adding the register's offset to it, then run= `f` on its value to /// obtain a new value to write back. #[inline(always)] - pub(crate) fn alter( + pub(crate) fn alter( io: &T, base: &B, idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -895,12 +910,13 @@ pub(crate) fn alter( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_read( + pub(crate) fn try_read( io: &T, base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -916,13 +932,14 @@ pub(crate) fn try_read( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_write( + pub(crate) fn try_write( self, io: &T, base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -939,13 +956,14 @@ pub(crate) fn try_write( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_alter( + pub(crate) fn try_alter( io: &T, base: &B, idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoInfallible, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs index 71fbe71b84db..7a0121ab9b09 100644 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@ -8,6 +8,7 @@ use core::convert::TryFrom; use kernel::device; use kernel::error::Result; +use kernel::io::IoFallible; use kernel::prelude::*; use kernel::ptr::{Alignable, Alignment}; use kernel::types::ARef; diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs index d4f3169248df..45739350f7cb 100644 --- a/rust/kernel/devres.rs +++ b/rust/kernel/devres.rs @@ -57,14 +57,15 @@ struct Inner { /// device::{Bound, Device}, /// devres::Devres, /// io::{ -/// Io, -/// IoRaw, // +/// IoInfallible, +/// Mmio, +/// MmioRaw, // /// }, // /// }; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -79,7 +80,7 @@ struct Inner { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -91,11 +92,11 @@ struct Inner { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// # fn no_run(dev: &Device) -> Result<(), Error> { @@ -241,6 +242,7 @@ pub fn device(&self) -> &Device { /// # use kernel::{ /// device::Core, /// devres::Devres, + /// io::IoInfallible, /// pci, // /// }; /// diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 6f1e22613f8b..6221dea9c8c3 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -20,16 +20,16 @@ /// By itself, the existence of an instance of this structure does not pro= vide any guarantees that /// the represented MMIO region does exist or is properly mapped. /// -/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an `Io` -/// instance providing the actual memory accessors. Only by the conversion= into an `Io` structure -/// any guarantees are given. -pub struct IoRaw { +/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an +/// `Mmio` instance providing the actual memory accessors. Only by the con= version into an `Mmio` +/// structure any guarantees are given. +pub struct MmioRaw { addr: usize, maxsize: usize, } =20 -impl IoRaw { - /// Returns a new `IoRaw` instance on success, an error otherwise. +impl MmioRaw { + /// Returns a new `MmioRaw` instance on success, an error otherwise. pub fn new(addr: usize, maxsize: usize) -> Result { if maxsize < SIZE { return Err(EINVAL); @@ -68,14 +68,16 @@ pub fn maxsize(&self) -> usize { /// bindings, /// ffi::c_void, /// io::{ -/// Io, -/// IoRaw, // +/// IoFallible, +/// IoInfallible, +/// Mmio, +/// MmioRaw, // /// }, // /// }; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -90,7 +92,7 @@ pub fn maxsize(&self) -> usize { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -102,11 +104,11 @@ pub fn maxsize(&self) -> usize { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// @@ -120,29 +122,31 @@ pub fn maxsize(&self) -> usize { /// # } /// ``` #[repr(transparent)] -pub struct Io(IoRaw); +pub struct Mmio(MmioRaw); =20 macro_rules! define_read { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_= name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident -> $t= ype_name:ty) =3D> { /// Read IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile /// time, the build will fail. $(#[$attr])* #[inline] - pub fn $name(&self, offset: usize) -> $type_name { + $vis fn $name(&self, offset: usize) -> $type_name { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. unsafe { bindings::$c_fn(addr as *const c_void) } } + }; =20 + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident -> = $type_name:ty) =3D> { /// Read IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is /// out of bounds. $(#[$attr])* - pub fn $try_name(&self, offset: usize) -> Result<$type_name> { + $vis fn $try_name(&self, offset: usize) -> Result<$type_name> { let addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. @@ -152,26 +156,28 @@ pub fn $try_name(&self, offset: usize) -> Result<$typ= e_name> { } =20 macro_rules! define_write { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_= name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident <- $t= ype_name:ty) =3D> { /// Write IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile /// time, the build will fail. $(#[$attr])* #[inline] - pub fn $name(&self, value: $type_name, offset: usize) { + $vis fn $name(&self, value: $type_name, offset: usize) { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. unsafe { bindings::$c_fn(value, addr as *mut c_void) } } + }; =20 + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident <- = $type_name:ty) =3D> { /// Write IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is /// out of bounds. $(#[$attr])* - pub fn $try_name(&self, value: $type_name, offset: usize) -> Resul= t { + $vis fn $try_name(&self, value: $type_name, offset: usize) -> Resu= lt { let addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. @@ -181,43 +187,38 @@ pub fn $try_name(&self, value: $type_name, offset: us= ize) -> Result { }; } =20 -impl Io { - /// Converts an `IoRaw` into an `Io` instance, providing the accessors= to the MMIO mapping. - /// - /// # Safety - /// - /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size - /// `maxsize`. - pub unsafe fn from_raw(raw: &IoRaw) -> &Self { - // SAFETY: `Io` is a transparent wrapper around `IoRaw`. - unsafe { &*core::ptr::from_ref(raw).cast() } +/// Checks whether an access of type `U` at the given `offset` +/// is valid within this region. +#[inline] +const fn offset_valid(offset: usize, size: usize) -> bool { + let type_size =3D core::mem::size_of::(); + if let Some(end) =3D offset.checked_add(type_size) { + end <=3D size && offset % type_size =3D=3D 0 + } else { + false } +} + +/// Represents a region of I/O space of a fixed size. +/// +/// Provides common helpers for offset validation and address +/// calculation on top of a base address and maximum size. +/// +pub trait Io { + /// Minimum usable size + const MIN_SIZE: usize; =20 /// Returns the base address of this mapping. - #[inline] - pub fn addr(&self) -> usize { - self.0.addr() - } + fn addr(&self) -> usize; =20 /// Returns the maximum size of this mapping. - #[inline] - pub fn maxsize(&self) -> usize { - self.0.maxsize() - } - - #[inline] - const fn offset_valid(offset: usize, size: usize) -> bool { - let type_size =3D core::mem::size_of::(); - if let Some(end) =3D offset.checked_add(type_size) { - end <=3D size && offset % type_size =3D=3D 0 - } else { - false - } - } + fn maxsize(&self) -> usize; =20 + /// Returns the absolute I/O address for a given `offset`. + /// Performs runtime bounds checks using [`offset_valid`] #[inline] fn io_addr(&self, offset: usize) -> Result { - if !Self::offset_valid::(offset, self.maxsize()) { + if !offset_valid::(offset, self.maxsize()) { return Err(EINVAL); } =20 @@ -226,50 +227,173 @@ fn io_addr(&self, offset: usize) -> Result= { self.addr().checked_add(offset).ok_or(EINVAL) } =20 + /// Returns the absolute I/O address for a given `offset`, + /// performing compile-time bound checks. #[inline] fn io_addr_assert(&self, offset: usize) -> usize { - build_assert!(Self::offset_valid::(offset, SIZE)); + build_assert!(offset_valid::(offset, Self::MIN_SIZE)); =20 self.addr() + offset } +} + +/// Types implementing this trait (e.g. MMIO BARs or PCI config +/// regions) can share the same Infallible accessors. +pub trait IoInfallible: Io { + /// Infallible 8-bit read with compile-time bounds check. + fn read8(&self, offset: usize) -> u8; + + /// Infallible 16-bit read with compile-time bounds check. + fn read16(&self, offset: usize) -> u16; + + /// Infallible 32-bit read with compile-time bounds check. + fn read32(&self, offset: usize) -> u32; + + /// Infallible 8-bit write with compile-time bounds check. + fn write8(&self, value: u8, offset: usize); + + /// Infallible 16-bit write with compile-time bounds check. + fn write16(&self, value: u16, offset: usize); + + /// Infallible 32-bit write with compile-time bounds check. + fn write32(&self, value: u32, offset: usize); +} + +/// Types implementing this trait (e.g. MMIO BARs or PCI config +/// regions) can share the same Fallible accessors. +pub trait IoFallible: Io { + /// Fallible 8-bit read with runtime bounds check. + fn try_read8(&self, offset: usize) -> Result; + + /// Fallible 16-bit read with runtime bounds check. + fn try_read16(&self, offset: usize) -> Result; + + /// Fallible 32-bit read with runtime bounds check. + fn try_read32(&self, offset: usize) -> Result; + + /// Fallible 8-bit write with runtime bounds check. + fn try_write8(&self, value: u8, offset: usize) -> Result; + + /// Fallible 16-bit write with runtime bounds check. + fn try_write16(&self, value: u16, offset: usize) -> Result; + + /// Fallible 32-bit write with runtime bounds check. + fn try_write32(&self, value: u32, offset: usize) -> Result; +} + +impl Io for Mmio { + const MIN_SIZE: usize =3D SIZE; + + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + self.0.addr() + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.0.maxsize() + } +} + +impl IoInfallible for Mmio { + define_read!(infallible, read8, readb -> u8); + define_read!(infallible, read16, readw -> u16); + define_read!(infallible, read32, readl -> u32); + + define_write!(infallible, write8, writeb <- u8); + define_write!(infallible, write16, writew <- u16); + define_write!(infallible, write32, writel <- u32); +} + +impl IoFallible for Mmio { + define_read!(fallible, try_read8, readb -> u8); + define_read!(fallible, try_read16, readw -> u16); + define_read!(fallible, try_read32, readl -> u32); + + define_write!(fallible, try_write8, writeb <- u8); + define_write!(fallible, try_write16, writew <- u16); + define_write!(fallible, try_write32, writel <- u32); +} + +impl Mmio { + /// Converts an `MmioRaw` into an `Mmio` instance, providing the acces= sors to the MMIO mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size + /// `maxsize`. + pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { + // SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`. + unsafe { &*core::ptr::from_ref(raw).cast() } + } =20 - define_read!(read8, try_read8, readb -> u8); - define_read!(read16, try_read16, readw -> u16); - define_read!(read32, try_read32, readl -> u32); define_read!( + infallible, #[cfg(CONFIG_64BIT)] - read64, - try_read64, + pub read64, readq -> u64 ); =20 - define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8); - define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16); - define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32); + define_write!( + infallible, + #[cfg(CONFIG_64BIT)] + pub write64, + writeq <- u64 + ); + define_read!( + fallible, #[cfg(CONFIG_64BIT)] - read64_relaxed, - try_read64_relaxed, - readq_relaxed -> u64 + pub try_read64, + readq -> u64 ); =20 - define_write!(write8, try_write8, writeb <- u8); - define_write!(write16, try_write16, writew <- u16); - define_write!(write32, try_write32, writel <- u32); define_write!( + fallible, #[cfg(CONFIG_64BIT)] - write64, - try_write64, + pub try_write64, writeq <- u64 ); =20 - define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8= ); - define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- = u16); - define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- = u32); + define_read!(infallible, pub read8_relaxed, readb_relaxed -> u8); + define_read!(infallible, pub read16_relaxed, readw_relaxed -> u16); + define_read!(infallible, pub read32_relaxed, readl_relaxed -> u32); + define_read!( + infallible, + #[cfg(CONFIG_64BIT)] + pub read64_relaxed, + readq_relaxed -> u64 + ); + + define_read!(fallible, pub try_read8_relaxed, readb_relaxed -> u8); + define_read!(fallible, pub try_read16_relaxed, readw_relaxed -> u16); + define_read!(fallible, pub try_read32_relaxed, readl_relaxed -> u32); + define_read!( + fallible, + #[cfg(CONFIG_64BIT)] + pub try_read64_relaxed, + readq_relaxed -> u64 + ); + + define_write!(infallible, pub write8_relaxed, writeb_relaxed <- u8); + define_write!(infallible, pub write16_relaxed, writew_relaxed <- u16); + define_write!(infallible, pub write32_relaxed, writel_relaxed <- u32); + define_write!( + infallible, + #[cfg(CONFIG_64BIT)] + pub write64_relaxed, + writeq_relaxed <- u64 + ); + + define_write!(fallible, pub try_write8_relaxed, writeb_relaxed <- u8); + define_write!(fallible, pub try_write16_relaxed, writew_relaxed <- u16= ); + define_write!(fallible, pub try_write32_relaxed, writel_relaxed <- u32= ); define_write!( + fallible, #[cfg(CONFIG_64BIT)] - write64_relaxed, - try_write64_relaxed, + pub try_write64_relaxed, writeq_relaxed <- u64 ); } diff --git a/rust/kernel/io/mem.rs b/rust/kernel/io/mem.rs index b03b82cd531b..5dcd7c901427 100644 --- a/rust/kernel/io/mem.rs +++ b/rust/kernel/io/mem.rs @@ -17,8 +17,8 @@ Region, Resource, // }, - Io, - IoRaw, // + Mmio, + MmioRaw, // }, prelude::*, }; @@ -203,7 +203,7 @@ pub fn new<'a>(io_request: IoRequest<'a>) -> impl PinIn= it, Error> + } =20 impl Deref for ExclusiveIoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { &self.iomem @@ -217,10 +217,10 @@ fn deref(&self) -> &Self::Target { /// /// # Invariants /// -/// [`IoMem`] always holds an [`IoRaw`] instance that holds a valid pointe= r to the +/// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid poin= ter to the /// start of the I/O memory mapped region. pub struct IoMem { - io: IoRaw, + io: MmioRaw, } =20 impl IoMem { @@ -255,7 +255,7 @@ fn ioremap(resource: &Resource) -> Result { return Err(ENOMEM); } =20 - let io =3D IoRaw::new(addr as usize, size)?; + let io =3D MmioRaw::new(addr as usize, size)?; let io =3D IoMem { io }; =20 Ok(io) @@ -278,10 +278,10 @@ fn drop(&mut self) { } =20 impl Deref for IoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { // SAFETY: Safe as by the invariant of `IoMem`. - unsafe { Io::from_raw(&self.io) } + unsafe { Mmio::from_raw(&self.io) } } } diff --git a/rust/kernel/io/poll.rs b/rust/kernel/io/poll.rs index b1a2570364f4..543a4b7cea0d 100644 --- a/rust/kernel/io/poll.rs +++ b/rust/kernel/io/poll.rs @@ -45,12 +45,12 @@ /// # Examples /// /// ```no_run -/// use kernel::io::{Io, poll::read_poll_timeout}; +/// use kernel::io::{IoFallible, Mmio, poll::read_poll_timeout}; /// use kernel::time::Delta; /// /// const HW_READY: u16 =3D 0x01; /// -/// fn wait_for_hardware(io: &Io) -> Result { +/// fn wait_for_hardware(io: &Mmio) -> Result { /// read_poll_timeout( /// // The `op` closure reads the value of a specific status regis= ter. /// || io.try_read16(0x1000), @@ -128,12 +128,12 @@ pub fn read_poll_timeout( /// # Examples /// /// ```no_run -/// use kernel::io::{poll::read_poll_timeout_atomic, Io}; +/// use kernel::io::{poll::read_poll_timeout_atomic, IoFallible, Mmio}; /// use kernel::time::Delta; /// /// const HW_READY: u16 =3D 0x01; /// -/// fn wait_for_hardware(io: &Io) -> Result { +/// fn wait_for_hardware(io: &Mmio) -> Result { /// read_poll_timeout_atomic( /// // The `op` closure reads the value of a specific status regis= ter. /// || io.try_read16(0x1000), diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index 0d55c3139b6f..2bbb3261198d 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -8,8 +8,8 @@ device, devres::Devres, io::{ - Io, - IoRaw, // + Mmio, + MmioRaw, // }, prelude::*, sync::aref::ARef, // @@ -24,7 +24,7 @@ /// memory mapped PCI BAR and its size. pub struct Bar { pdev: ARef, - io: IoRaw, + io: MmioRaw, num: i32, } =20 @@ -60,7 +60,7 @@ pub(super) fn new(pdev: &Device, num: u32, name: &CStr) -= > Result { return Err(ENOMEM); } =20 - let io =3D match IoRaw::new(ioptr, len as usize) { + let io =3D match MmioRaw::new(ioptr, len as usize) { Ok(io) =3D> io, Err(err) =3D> { // SAFETY: @@ -114,11 +114,11 @@ fn drop(&mut self) { } =20 impl Deref for Bar { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { // SAFETY: By the type invariant of `Self`, the MMIO range in `sel= f.io` is properly mapped. - unsafe { Io::from_raw(&self.io) } + unsafe { Mmio::from_raw(&self.io) } } } =20 diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci= .rs index ee6248b8cda5..74b93ca7c338 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -8,6 +8,8 @@ c_str, device::Core, devres::Devres, + io::IoFallible, + io::IoInfallible, pci, prelude::*, sync::aref::ARef, // --=20 2.51.0 From nobody Fri Dec 19 15:48:09 2025 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010039.outbound.protection.outlook.com [52.101.56.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4404127146A; Thu, 6 Nov 2025 10:29:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.39 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424968; cv=fail; b=S4rEHGc5QEKVBd7bcMqFxcUxiIUuv5Arh9vCKAAZ2r+wWtzh9Mnn/h1y4n/86Xs0pR94BOz9hbcneX4bs/5uztipgQqrxPXLxGKEYdav99opoy3uEWgkOVyohUqfd3ekVOOPf3yBxFYErmH5VJvtVphRG97M6sspl5fwLX9QDBE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424968; c=relaxed/simple; bh=nZ5uRjvnikG3UlcRMk+bstrOo3egTlsAUroBORPOTUM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KkH7sx74PdyNZu3y2fAcxl3SLSPk51G2SpRX2x4hJ6ag/rho7gpzVag9oTfnaG+x6iI+QaI7bP687nmDt+o3Wq5dQJrJrmL67oSx7gS1J+p5tq65itBGiSRxDP4J1ypZMirSyNIegptziHz1J99kSB+uQm3zk94n5NfJ/bXzFRQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=jK9t/1uS; arc=fail smtp.client-ip=52.101.56.39 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="jK9t/1uS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=M/D19swRSlnYPyBx6jS27Kw0PhE2MRgK7F1uRpx6hwWjrkEX9kACiNzLc42KtOMh8KA2AavqkrtNlmkR1P8pNks8ScqFCgUK3KvVWy75SXFLYQsh8Hx/IBc3TNLxCYXHidua36zl5YWjREB34zFccfB1yYXMsdhsWrY1jBMXKB3Lxg1+kuOneeuD1fgl2bZOXOxiLrFgPSJB1z5YtBKHZ9bTZfHUb1nm7tp82LyTUaDuMosDRl07z6ZRhmq9aNmlxRpXiMLztGimKiK7IQCd0v6reNJNBGqmvPVY4VsGlQx4/K52szNPsgPbcVXGxQzPvpKYVIQFZldutZAPP3tIEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5u0CQC1dytt2lFOLipyZ7wwoMLgyfW2BgnBaGjBMjwg=; b=vd+GXL4+4c1t00MnztDi/v+zW4DfdO/klGOlWdWga/gS94LS+G8184goQlwjyHEB+nx7yGQi24Qej8Wvl0Agc3UkxM3eBppaT6IIcZywc3uIhCap/0LBgR+U5RK4Bk4pmVaqKbHRwPUkr4HBORzUGIK6HWJk/fTeMZPCY+b4lhxeeul0ZTaHNexcm8LV5WTafKo0otS1ovxCrAIOCT019BHqtaNDGYRF+IiSfQrRu/raXPDzqj6VHYyUSQv1Iedb6WRzhkkBaakgzaQdB0jqL4UFbcnGLzarvAf7ZHQziD14B5dJGxfzO2hmQWZBOKcnP/dgSsfCWkdjjm6n886HQg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5u0CQC1dytt2lFOLipyZ7wwoMLgyfW2BgnBaGjBMjwg=; b=jK9t/1uSzObFi9gm61+yK2J0rHA7uM7/0MN74ImvWD8Dw8tVgOlEjINAhQpUMUc6P/3XG3SDVcxHYMSstJeW0OJmRRAoEhsprUA1ogHtH4wb6b14f7gXJ7FLKrwKjFGmKTYSJXSfEt66vKh+pAaEgy8FqhnfrwdOLH3RaHfsoQejN+n3n0Wd6O8nyRp3o+3uAn53cmGMtWBGshDjBrXGTuwCHzZFzuJ0Zzaab6N+v4K5nem+Y0KLmYJ63uAHZqgdSbiPM90SOwXW/WmVb4vJBsspkGs5bFQMQgdZ0UIhDjSBV49Dacn7cazGLM+R3FzpHz614M1LuQImeKH0HCUH/g== Received: from CH0PR07CA0007.namprd07.prod.outlook.com (2603:10b6:610:32::12) by SA1PR12MB5657.namprd12.prod.outlook.com (2603:10b6:806:234::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.9; Thu, 6 Nov 2025 10:29:20 +0000 Received: from CH2PEPF0000014A.namprd02.prod.outlook.com (2603:10b6:610:32:cafe::ce) by CH0PR07CA0007.outlook.office365.com (2603:10b6:610:32::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.9 via Frontend Transport; Thu, 6 Nov 2025 10:29:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000014A.mail.protection.outlook.com (10.167.244.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Thu, 6 Nov 2025 10:29:20 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:29:08 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:29:07 -0800 Received: from inno-vm-xubuntu (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 6 Nov 2025 02:28:57 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 5/7] rust: io: factor out MMIO read/write macros Date: Thu, 6 Nov 2025 12:27:51 +0200 Message-ID: <20251106102753.2976-6-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106102753.2976-1-zhiw@nvidia.com> References: <20251106102753.2976-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000014A:EE_|SA1PR12MB5657:EE_ X-MS-Office365-Filtering-Correlation-Id: 691b0fee-1194-4527-99eb-08de1d1f58b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?FIV6r4Ll7h4G3JvmD+F7gn4m9IyFe7dhsNo1gv7Rzuz+yys3BYaCOUA1VawK?= =?us-ascii?Q?PBkSx2R+BbskFOVdqdVg8nv7BLzZo+c+/01eJjXV+Yd2ABbzvXqoGHz03SdS?= =?us-ascii?Q?Tlm0WmYOJBg/ywo0JGpUnX9dmdhUuFgC9XgzxASf6tLBOygckCS6hSwRLFQ/?= =?us-ascii?Q?mIgPvR6NY/kxuswpAGnXis1LFagdgrfi8TCUDZPDyM/jth5Hm7YdXAFEQ+Bn?= =?us-ascii?Q?cGswGTS6DycCSdFpvgPrG1UqRZv8ZMDFWiDXvbJDWoCIgiqdxS7g2yDgFd4g?= =?us-ascii?Q?s1+nbH3ks4EoEOA+1wzAgE9LGFgIWIn/9xuJGRnqmPboGO6eqNI4fuJsPbTq?= =?us-ascii?Q?LusCil6S4X/TDHSob7pnfHBM7Q6wcziAidJaVlHucT0+10P7FKAlIoNzzg2o?= =?us-ascii?Q?umMuxRkIZ0psMFVAmYlwA2Xq1AP8QwJGyYnAv0nt9zMgIc5mtPlrTHUfT9G9?= =?us-ascii?Q?sFC6fOVnlFxwZyPoAfOSBx2BV0CqmCMKkQECEIq0vDD4PwOCe+iK7e7gFfEA?= =?us-ascii?Q?P1l6MuX97SKURDAvzx7tYj3PLA1o5nbQ8rPDtkT4rxiGeweD6V48rplSmdR8?= =?us-ascii?Q?NDyFr04+SVN0m8u2Y4+AYpPOtfqoooxYULxgXlGWWUJ77r1Q+Apn8TMP6IsV?= =?us-ascii?Q?H2JUd6XOMnOyLxRrUQgMsq85JdQltatwGGfRkqvsNJiCszOwAUonAq6Q4Haz?= =?us-ascii?Q?rYsr0uWZK23D/0fd6b0JQGrjPIlZ8W0X2VmJOURPXRaIensr2TjXyN+oiN1e?= =?us-ascii?Q?YzuK0los740CTzAFicUzOLTJWCY5Oh+l93Q5Xa5RLhYv/0NzVE/na60NrCl9?= =?us-ascii?Q?DuxfWsTVjqLqzXIzsbzYhPbEtHDtgFBij/hM4my4wWR8MxZDR6BOaSZcyDZJ?= =?us-ascii?Q?CyFKc9Gf/l1aA8AAxU4ZQKVqqNXZ55WwQFulnUGIQBATPs/9AQkaAorEm60Y?= =?us-ascii?Q?AdnD15IWIt/iwfjzf09z9otkP4O1Vs0l5AD8sCsErWXk26OwB+GSoR5jz2NN?= =?us-ascii?Q?EZ+U8FZV7VSFPPVzmsS8CBemAxVR/2USp2ubfeA2IhwVJ4kMgy+dVoVG8Es8?= =?us-ascii?Q?Y4J3EiFCBJEBhubdXf0BY3rThIynBQFrtgbu/7bdscEosqmFxjM9XdyLTaPT?= =?us-ascii?Q?C5jDsuhHoXqAvu6Fe6+wXXYz/pkEyuhdY5citxqCM2TT1UA7sX0IhKoRzdOr?= =?us-ascii?Q?9PZAwjNYa7Wh4pheLNNGL2JMg6/wPlJVzMgL38I1rc5VODjs9rhKep6ChCfO?= =?us-ascii?Q?EMJEkeKKeU64zjC+KAMNHaz8cs5uU1sZzyIQaj4LKd73B99fk6/VEar+tm0O?= =?us-ascii?Q?mp1H2EEmnbL1LOQuR3mBnodYcTkxjAugla8wdhCQS4aufxfKibaNjIaYpKAG?= =?us-ascii?Q?ONmqCI85bYvmNrkpXdau3DYdvPLgjnkhxR/2pCwf1+KXLXjWZJfvfgbt4aIt?= =?us-ascii?Q?H3CjoHRTPySp2e6zeVNSY8a8SlaUxR/XsadQkKrexvZtsWAEyUZC2x0RyvCY?= =?us-ascii?Q?eRJaJ9n//Z1DdnXsKQANLNYrrub/v15blRToTMQ4/j5Hht1BVvu/duZVS3zC?= =?us-ascii?Q?W2vKQtlmhK1C2xBqBRQ=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:29:20.1434 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 691b0fee-1194-4527-99eb-08de1d1f58b9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5657 Content-Type: text/plain; charset="utf-8" Refactor the existing MMIO accessors to use common call macros instead of inlining the bindings calls in each `define_{read,write}!` expansion. This factoring separates the common offset/bounds checks from the low-level call pattern, making it easier to add additional I/O accessor families. No functional change intended. Signed-off-by: Zhi Wang --- rust/kernel/io.rs | 110 ++++++++++++++++++++++++++++++---------------- 1 file changed, 73 insertions(+), 37 deletions(-) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 6221dea9c8c3..9401c6c21689 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -124,8 +124,34 @@ pub fn maxsize(&self) -> usize { #[repr(transparent)] pub struct Mmio(MmioRaw); =20 +macro_rules! call_mmio_read { + (infallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) =3D> { + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + unsafe { bindings::$c_fn($addr as *const c_void) as $type } + }; + + (fallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) =3D> {{ + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + Ok(unsafe { bindings::$c_fn($addr as *const c_void) as $type }) + }}; +} + +macro_rules! call_mmio_write { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr= ) =3D> { + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + unsafe { bindings::$c_fn($value, $addr as *mut c_void) } + }; + + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) = =3D> {{ + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + unsafe { bindings::$c_fn($value, $addr as *mut c_void) }; + Ok(()) + }}; +} + macro_rules! define_read { - (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident -> $t= ype_name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident= , $c_fn:ident -> + $type_name:ty) =3D> { /// Read IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile @@ -135,12 +161,13 @@ macro_rules! define_read { $vis fn $name(&self, offset: usize) -> $type_name { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(addr as *const c_void) } + // SAFETY: By the type invariant `addr` is a valid address for= IO operations. + $call_macro!(infallible, $c_fn, self, $type_name, addr) } }; =20 - (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident -> = $type_name:ty) =3D> { + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ide= nt, $c_fn:ident -> + $type_name:ty) =3D> { /// Read IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is @@ -149,14 +176,16 @@ macro_rules! define_read { $vis fn $try_name(&self, offset: usize) -> Result<$type_name> { let addr =3D self.io_addr::<$type_name>(offset)?; =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - Ok(unsafe { bindings::$c_fn(addr as *const c_void) }) + // SAFETY: By the type invariant `addr` is a valid address for= IO operations. + $call_macro!(fallible, $c_fn, self, $type_name, addr) } }; } +pub(crate) use define_read; =20 macro_rules! define_write { - (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident <- $t= ype_name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident= , $c_fn:ident <- + $type_name:ty) =3D> { /// Write IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile @@ -166,12 +195,12 @@ macro_rules! define_write { $vis fn $name(&self, value: $type_name, offset: usize) { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as *mut c_void) } + $call_macro!(infallible, $c_fn, self, $type_name, addr, value); } }; =20 - (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident <- = $type_name:ty) =3D> { + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ide= nt, $c_fn:ident <- + $type_name:ty) =3D> { /// Write IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is @@ -180,12 +209,11 @@ macro_rules! define_write { $vis fn $try_name(&self, value: $type_name, offset: usize) -> Resu= lt { let addr =3D self.io_addr::<$type_name>(offset)?; =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as *mut c_void) } - Ok(()) + $call_macro!(fallible, $c_fn, self, $type_name, addr, value) } }; } +pub(crate) use define_write; =20 /// Checks whether an access of type `U` at the given `offset` /// is valid within this region. @@ -298,23 +326,23 @@ fn maxsize(&self) -> usize { } =20 impl IoInfallible for Mmio { - define_read!(infallible, read8, readb -> u8); - define_read!(infallible, read16, readw -> u16); - define_read!(infallible, read32, readl -> u32); + define_read!(infallible, read8, call_mmio_read, readb -> u8); + define_read!(infallible, read16, call_mmio_read, readw -> u16); + define_read!(infallible, read32, call_mmio_read, readl -> u32); =20 - define_write!(infallible, write8, writeb <- u8); - define_write!(infallible, write16, writew <- u16); - define_write!(infallible, write32, writel <- u32); + define_write!(infallible, write8, call_mmio_write, writeb <- u8); + define_write!(infallible, write16, call_mmio_write, writew <- u16); + define_write!(infallible, write32, call_mmio_write, writel <- u32); } =20 impl IoFallible for Mmio { - define_read!(fallible, try_read8, readb -> u8); - define_read!(fallible, try_read16, readw -> u16); - define_read!(fallible, try_read32, readl -> u32); + define_read!(fallible, try_read8, call_mmio_read, readb -> u8); + define_read!(fallible, try_read16, call_mmio_read, readw -> u16); + define_read!(fallible, try_read32, call_mmio_read, readl -> u32); =20 - define_write!(fallible, try_write8, writeb <- u8); - define_write!(fallible, try_write16, writew <- u16); - define_write!(fallible, try_write32, writel <- u32); + define_write!(fallible, try_write8, call_mmio_write, writeb <- u8); + define_write!(fallible, try_write16, call_mmio_write, writew <- u16); + define_write!(fallible, try_write32, call_mmio_write, writel <- u32); } =20 impl Mmio { @@ -333,6 +361,7 @@ pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { infallible, #[cfg(CONFIG_64BIT)] pub read64, + call_mmio_read, readq -> u64 ); =20 @@ -340,6 +369,7 @@ pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { infallible, #[cfg(CONFIG_64BIT)] pub write64, + call_mmio_write, writeq <- u64 ); =20 @@ -347,6 +377,7 @@ pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { fallible, #[cfg(CONFIG_64BIT)] pub try_read64, + call_mmio_read, readq -> u64 ); =20 @@ -354,46 +385,51 @@ pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { fallible, #[cfg(CONFIG_64BIT)] pub try_write64, + call_mmio_write, writeq <- u64 ); =20 - define_read!(infallible, pub read8_relaxed, readb_relaxed -> u8); - define_read!(infallible, pub read16_relaxed, readw_relaxed -> u16); - define_read!(infallible, pub read32_relaxed, readl_relaxed -> u32); + define_read!(infallible, pub read8_relaxed, call_mmio_read, readb_rela= xed -> u8); + define_read!(infallible, pub read16_relaxed, call_mmio_read, readw_rel= axed -> u16); + define_read!(infallible, pub read32_relaxed, call_mmio_read, readl_rel= axed -> u32); define_read!( infallible, #[cfg(CONFIG_64BIT)] pub read64_relaxed, + call_mmio_read, readq_relaxed -> u64 ); =20 - define_read!(fallible, pub try_read8_relaxed, readb_relaxed -> u8); - define_read!(fallible, pub try_read16_relaxed, readw_relaxed -> u16); - define_read!(fallible, pub try_read32_relaxed, readl_relaxed -> u32); + define_read!(fallible, pub try_read8_relaxed, call_mmio_read, readb_re= laxed -> u8); + define_read!(fallible, pub try_read16_relaxed, call_mmio_read, readw_r= elaxed -> u16); + define_read!(fallible, pub try_read32_relaxed, call_mmio_read, readl_r= elaxed -> u32); define_read!( fallible, #[cfg(CONFIG_64BIT)] pub try_read64_relaxed, + call_mmio_read, readq_relaxed -> u64 ); =20 - define_write!(infallible, pub write8_relaxed, writeb_relaxed <- u8); - define_write!(infallible, pub write16_relaxed, writew_relaxed <- u16); - define_write!(infallible, pub write32_relaxed, writel_relaxed <- u32); + define_write!(infallible, pub write8_relaxed, call_mmio_write, writeb_= relaxed <- u8); + define_write!(infallible, pub write16_relaxed, call_mmio_write, writew= _relaxed <- u16); + define_write!(infallible, pub write32_relaxed, call_mmio_write, writel= _relaxed <- u32); define_write!( infallible, #[cfg(CONFIG_64BIT)] pub write64_relaxed, + call_mmio_write, writeq_relaxed <- u64 ); =20 - define_write!(fallible, pub try_write8_relaxed, writeb_relaxed <- u8); - define_write!(fallible, pub try_write16_relaxed, writew_relaxed <- u16= ); - define_write!(fallible, pub try_write32_relaxed, writel_relaxed <- u32= ); + define_write!(fallible, pub try_write8_relaxed, call_mmio_write, write= b_relaxed <- u8); + define_write!(fallible, pub try_write16_relaxed, call_mmio_write, writ= ew_relaxed <- u16); + define_write!(fallible, pub try_write32_relaxed, call_mmio_write, writ= el_relaxed <- u32); define_write!( fallible, #[cfg(CONFIG_64BIT)] pub try_write64_relaxed, + call_mmio_write, writeq_relaxed <- u64 ); } --=20 2.51.0 From nobody Fri Dec 19 15:48:09 2025 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010047.outbound.protection.outlook.com [52.101.46.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF57E2E7199; Thu, 6 Nov 2025 10:29:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.46.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424977; cv=fail; b=p2i9bA312pLaNjTB0AIoS8Q0Xk7ML2n40w4fxKscmk/rbxxCnsT3yzclRMHIFVzvPkDr69aNNGYUbOTZCid2vYgJ4obt2d77iUPDNrAuR4X1G1etD1nR7lYdlM1bt1AP8fK5cfPhj/cuf0vc5UKCgp8BivMNLyBOqg+GVNdqwl0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424977; c=relaxed/simple; bh=qKDCT6Fot5kl54evkbyTZBLuEQHU8xgLMuqpN44Yy38=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dn9zg9pRBitT7viy8NPLQ5l0930mm0cjGGJSzIPI+eJVKRdssh3I5mmQ1ZIB1xJCRq/ekfJBx9gK2D97vvNo8jUwZWffjlqGgAPncy/5klWzVSjJc7lAcvZr8//mQJUxoW+vvNbi1sJZCyntmh4V/PGYo4rs2Npa5urI4HbTmsI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ehgZK9pI; arc=fail smtp.client-ip=52.101.46.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ehgZK9pI" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Bv4NkRNe0PA9T1N9oZtEw+xgio9Fw7kEP9ana7yY+j1idVjdMWt8cajuYqyBP+XEVdeucoW1FvdrjWZT2l9VP9VEJop5AHvLImbUCuF2ISpbUBXxoZrm/EvmGva6fikRblqRU1H0UVay5eyGoTqyO7H1ZWEi3XKACpPx1t3rnnv2LJDsf97SfE9dj2+Yn0hs6QApTvYKkSnJdBMp0F+x+Zf+rb+rhY+rsrvmM/Q+KDWRv0tavYaLEek47jMpzFwAq7nk/vAtnSXdoUexiiKq7jFmSUvsGK6WA8iD5c8uOs91P3C5rPzZmnW/27946qs3AXjxCGjWDs4JVt8VBorfzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7tx0ay8hk//g5AWfF2x24wcJ2+KfbskWCXsboIWUQ+Y=; b=sKFn/qpUkWOiF/Fzm2p3YYbKhnJQ/mTk+dZsPaGP9OjceILICbtr0JFkJGLiiOQZWEaqIC9hB+hgRMVC9L/lTSW0ImqBIcjWtOubVzIFqO3KpOGkgttgAb/nRg2VIvMCz5e49eQ/tpvDlnELp2RqShwJ+bW4GMoac8OFAeotkc8OJtiWIV1K37pWj87dlsnMt/X784UC6LZqJTI1j82c5kDduiy2yB0fttYcZxiL96m3OOb80S2lf+SWzAnf0CUY825zWUJsmRNr+vMYvFerv9JrSt+2sxZoky+7scaBV9lH8fXIxQoZGnOY7A+R7wtyd2lBUD25dTa6g1UkYyexZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7tx0ay8hk//g5AWfF2x24wcJ2+KfbskWCXsboIWUQ+Y=; b=ehgZK9pIq+mveNbp7m2N7P3JAkOvXiDIbjO7PNfLDICgDi0GnKmJLZVGLuViSO5LsRE8Uv+VYtOE66IEn3nkAWc4QTmRutABvO5JjfoQ2wBrUfVpXj4CFHNjvNn+Eu3aZp1YmvWsmIhURaMstBoTiPUB1424/sq5H8BihfQDRNvca0sMaXPshi7KiYSH+0Qte3JyGN1g/vLzkG5aLnI/5BEUR6hIp5j69OcBPBZrcKJA4Vt7GxDT2MNK+3U/8YKRxqmuglxMZ1AneKGi2g6/2XqEQoRc4zi3dmYRWkpn/iD2TkFMsD5HAU6X1HPnBU++Lbv5DOf3gYurNgx1tuEwRw== Received: from BYAPR05CA0043.namprd05.prod.outlook.com (2603:10b6:a03:74::20) by CH0PR12MB8461.namprd12.prod.outlook.com (2603:10b6:610:183::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.12; Thu, 6 Nov 2025 10:29:31 +0000 Received: from SJ1PEPF00002322.namprd03.prod.outlook.com (2603:10b6:a03:74:cafe::f0) by BYAPR05CA0043.outlook.office365.com (2603:10b6:a03:74::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9320.6 via Frontend Transport; Thu, 6 Nov 2025 10:29:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF00002322.mail.protection.outlook.com (10.167.242.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Thu, 6 Nov 2025 10:29:31 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:29:18 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:29:18 -0800 Received: from inno-vm-xubuntu (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 6 Nov 2025 02:29:08 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 6/7] rust: pci: add config space read/write support Date: Thu, 6 Nov 2025 12:27:52 +0200 Message-ID: <20251106102753.2976-7-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106102753.2976-1-zhiw@nvidia.com> References: <20251106102753.2976-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|CH0PR12MB8461:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e3ab7ef-7e10-4f20-c4ef-08de1d1f5f5f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QONL+4d+op2oqinNNc0XKYASABocY/PVmyu8STBHWQqNxKG3MA2c572kpnUf?= =?us-ascii?Q?lBypVNIhVqWKrzp8eEF6hzLU5DcM1akFKFhnlcSPQ5OpgZBecYP+QraqHzPZ?= =?us-ascii?Q?XNhfmQa9K43RBicvQfy/v7BzciBzXEyDrTvV+07UOB5CwxtiG0FT0STe2EzQ?= =?us-ascii?Q?l6p7hDS2tU/exdagfdQzNuXpaK+EbOBeX9ubXmTdMgduKIOf76iEHp+Hki1t?= =?us-ascii?Q?yhulDsdxo6mYUbTpl7bmT6csJnVS+TstL9iRtgCJSiPUqjqL7ivuVhEPrBzc?= =?us-ascii?Q?K7wF87LjH2/d3b1kx/7ClUXeEs5pbgoXUdqrykDkYSYpVlZUidaXs/5toQrC?= =?us-ascii?Q?hQTJvmeNr3oXawGASKE1eR/u6RqrpIV/Ko1AsI+mIpRHxNliCRofd81UPTTe?= =?us-ascii?Q?BHuhlTlOomvHxmjBNmTjn0M1z4VsmrKCTvh0xYMkVTkY6brrNdjLKKJZ2tXy?= =?us-ascii?Q?WGZDN4i+Wfw19E/e9V3lM585KNw8KZrRUjIE+ng/6NzTGwhhVdZVEP942Ohp?= =?us-ascii?Q?HEgrb7eg/kYLC4iVmApi0xl/yzwJWAXUaMcexBGIm1vW0ldYWBdUzEPJAhjh?= =?us-ascii?Q?SzUZWL5ZTvS9eMLAZcLUP2S6I3UrJN5E7n8wNP2MLXCuvafOY41KWUgWtE/6?= =?us-ascii?Q?oht6FGP3C8kFZzP7RtDOK09aGlYgU/Wm0P7EYxD5msFuqgnE/Il4X7goGF99?= =?us-ascii?Q?RWTMhUzpD+O9Eh/Cod9T9FYJR3sj3908jGZBinmerkflxJDXgLyoUoGJyIuQ?= =?us-ascii?Q?cXaSXmz8mQoNV71FtDHHzQoWtg7m9KPVkN170//+2FrYZHJhmrMt81v5BNHS?= =?us-ascii?Q?wWRmoUgJLaYf7drqFt6+AA+jr1AHvj+D1/BlW4Mar58wwgaF2B/D526U9AkR?= =?us-ascii?Q?A6TYQqzMnBJA4Wy3iKoCm2rz0MgVuJRkT+4OpYYi2RtbGVl+I33b7/IurhqX?= =?us-ascii?Q?VJ28XkAq8jpqYyiLcCDURvRhyb1wKu1kQM6AliZs0XTDAPBm1skPGkKKhDpy?= =?us-ascii?Q?NX5pA1I01uWb5Ch1c7njkpMRvdzQFqD99VLqlayjPMJIj8sG3cFy9K9Tb8kg?= =?us-ascii?Q?Ek+bMEL3htCng5RU7EDh2eZfEl7uk2XC6aimk40Vhh5BTo6luLV+0QdeEOBN?= =?us-ascii?Q?FMxNQlZ0RIwhM/jC5+6Diaojv6ZgDaX5vYFm4FSaJynS0cYueLHwB+e9ucVi?= =?us-ascii?Q?1rP7wJE1X2iry3OSFrYwUp6ZkgV0ZRXgObyYKlEeQleqGd5/jsivErvI0Dwb?= =?us-ascii?Q?taasPsfVsuGxhi7Memm3aBRJk/oMTnfHrRcWRhV8PEAZxlL4cqbq6JeC2x/d?= =?us-ascii?Q?1BrZfRQhCwPCSTO3Z0XUlJZUcXKu8ORI2r1EG+CPSp1cHuE8ldeuG1RS99FQ?= =?us-ascii?Q?XPKzZPCm+OQZKM8+KtRAoxo4D7HdowzsON2TjP1BUQ/VtMXQntrc9TzL2o1N?= =?us-ascii?Q?f8w3eAM+hGZCYE3abDjYhBn5EyS0ufeKnUsnwY6vTsDcb0ogy2gfWu7Kqa7e?= =?us-ascii?Q?x7/7VwbMhw30X0h7zhKk1Gy/pZoOGe4sOdRhHFDZrZRQEpdi5ZYkYw1Dkw0q?= =?us-ascii?Q?0A809adlBXKxd/nCWYg=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:29:31.4060 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e3ab7ef-7e10-4f20-c4ef-08de1d1f5f5f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002322.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8461 Content-Type: text/plain; charset="utf-8" Drivers might need to access PCI config space for querying capability structures and access the registers inside the structures. For Rust drivers need to access PCI config space, the Rust PCI abstraction needs to support it in a way that upholds Rust's safety principles. Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe accessors for PCI config space. The new type implements the `Io` trait to share offset validation and bound-checking logic with others. Cc: Danilo Krummrich Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 55 +++++++++++++++++++++++++++++++++++++- rust/kernel/pci/io.rs | 62 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 115 insertions(+), 2 deletions(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 410b79d46632..0b8064d6c0d1 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -39,7 +39,10 @@ ClassMask, Vendor, // }; -pub use self::io::Bar; +pub use self::io::{ + Bar, + ConfigSpace, // +}; pub use self::irq::{ IrqType, IrqTypes, @@ -330,6 +333,28 @@ fn as_raw(&self) -> *mut bindings::pci_dev { } } =20 +/// Represents the size of a PCI configuration space. +/// +/// PCI devices can have either a *normal* (legacy) configuration space of= 256 bytes, +/// or an *extended* configuration space of 4096 bytes as defined in the P= CI Express +/// specification. +#[repr(usize)] +pub enum ConfigSpaceSize { + /// 256-byte legacy PCI configuration space. + Normal =3D 256, + + /// 4096-byte PCIe extended configuration space. + Extended =3D 4096, +} + +impl ConfigSpaceSize { + /// Get the raw value of this enum. + #[inline(always)] + pub const fn as_raw(self) -> usize { + self as usize + } +} + impl Device { /// Returns the PCI vendor ID as [`Vendor`]. /// @@ -426,6 +451,20 @@ pub fn pci_class(&self) -> Class { // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. Class::from_raw(unsafe { (*self.as_raw()).class }) } + + /// Returns the size of configuration space. + fn cfg_size(&self) -> Result { + // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. + let size =3D unsafe { (*self.as_raw()).cfg_size }; + match size { + 256 =3D> Ok(ConfigSpaceSize::Normal), + 4096 =3D> Ok(ConfigSpaceSize::Extended), + _ =3D> { + debug_assert!(false); + Err(EINVAL) + } + } + } } =20 impl Device { @@ -441,6 +480,20 @@ pub fn set_master(&self) { // SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid = `struct pci_dev`. unsafe { bindings::pci_set_master(self.as_raw()) }; } + + /// Return an initialized config space object. + pub fn config_space<'a>( + &'a self, + ) -> Result> { + Ok(ConfigSpace { pdev: self }) + } + + /// Return an initialized config space object. + pub fn config_space_exteneded<'a>( + &'a self, + ) -> Result> { + Ok(ConfigSpace { pdev: self }) + } } =20 // SAFETY: `Device` is a transparent wrapper of a type that doesn't depend= on `Device`'s generic diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index 2bbb3261198d..a9895ee2c5c8 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -2,12 +2,19 @@ =20 //! PCI memory-mapped I/O infrastructure. =20 -use super::Device; +use super::{ + Device, + ConfigSpaceSize, // +}; use crate::{ bindings, device, devres::Devres, io::{ + define_read, + define_write, + Io, + IoInfallible, Mmio, MmioRaw, // }, @@ -16,6 +23,59 @@ }; use core::ops::Deref; =20 +/// Represents the PCI configuration space of a device. +/// +/// Provides typed read and write accessors for configuration registers +/// using the standard `pci_read_config_*` and `pci_write_config_*` helper= s. +/// +/// The generic const parameter `SIZE` can be used to indicate the +/// maximum size of the configuration space (e.g. 256 bytes for legacy, +/// 4096 bytes for extended config space). The actual size is obtained +/// from the underlying `struct pci_dev` via [`Device::cfg_size`]. +pub struct ConfigSpace<'a, const SIZE: usize =3D { ConfigSpaceSize::Extend= ed as usize }> { + pub(crate) pdev: &'a Device, +} + +macro_rules! call_config_read { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =3D> {{ + let mut val: $ty =3D 0; + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, &mut val) }; + val + }}; +} + +macro_rules! call_config_write { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr= ) =3D> { + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, $value) }; + }; +} + +impl<'a, const SIZE: usize> Io for ConfigSpace<'a, SIZE> { + const MIN_SIZE: usize =3D SIZE; + + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + 0 + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.pdev.cfg_size().map_or(0, |v| v as usize) + } +} + +impl<'a, const SIZE: usize> IoInfallible for ConfigSpace<'a, SIZE> { + define_read!(infallible, read8, call_config_read, pci_read_config_byte= -> u8); + define_read!(infallible, read16, call_config_read, pci_read_config_wor= d -> u16); + define_read!(infallible, read32, call_config_read, pci_read_config_dwo= rd -> u32); + + define_write!(infallible, write8, call_config_write, pci_write_config_= byte <- u8); + define_write!(infallible, write16, call_config_write, pci_write_config= _word <- u16); + define_write!(infallible, write32, call_config_write, pci_write_config= _dword <- u32); +} + /// A PCI BAR to perform I/O-Operations on. /// /// # Invariants --=20 2.51.0 From nobody Fri Dec 19 15:48:09 2025 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012065.outbound.protection.outlook.com [52.101.48.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EF9F29346F; Thu, 6 Nov 2025 10:29:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424989; cv=fail; b=sQ9PO/IRiHgiM6XJ2wiVWSkui8lfmOooE+EVPyWBsH6qRyMctnwWTlsWHBV8+9XyCOa7kSQIu7myVv5WRorUFVAXu5k//yPkT7jR4vbSzIxipNG4Beh2kGclKKGpTrbAsX3XB0+A1bzCrF3rNpTv45tJa9Yq1mECLvyTuHQa1Jw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762424989; c=relaxed/simple; bh=UAlVehZO/BQ/Gxn53y1vcfvwyawrTeQ7k4WK965Triw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DHzwG+P3Ji8EE770yqeEPDS07acbzp2uBM3K+HZLKg9+6JDPbgwpxN3+0wjWRWEoEZ4BXYF8mJyu+iWOx77UWwYBYY5MCZddivHHhzX0JlZ8qVuck2Uf+wrjVaSp9bLCLVXltto27sE8vsYJDEv1BM50J0B1RFbv46Mxo1yDSh4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=sH4Y02Q9; arc=fail smtp.client-ip=52.101.48.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="sH4Y02Q9" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=SI5A23IGXAQzk6GDAGvUs9L1gHYOOH84PtoD1ZSWT9rh6WNn0hQC2Bg4R2PKLHuCbGD9uywoB/lFHLEnWkuvuKquAaLx77gMqYxAzRcONxtiEgy3V0gqUAfYHhr3HgU1evynrOpQXyMIyjcMCPvgcuJayAOLhcI1V5HWzOL9CcmgtIIzFN/p2KGnF5+MB1e6VcLiCUcKjCYNq5WFBLaAMAClnWKYSDSwvgDcZhvPNSJ3DJA2s9+CGPGIxZPxs1P368y8UztMqkP0/dokJ3Jhfc5R9ZmMoxM8X+Z4huGc+sD/fq5GxeNiBYpLyVo900fiege7mPIbKodluJcayyADQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ttAQUT9oaBSccgpLNPFsHih6Q/up1j5LBKjPOrlSrGU=; b=VfbIILAxF/fw21J1eAT45PEN2CzEVUFqcaCnltq4VOluuvZSyEdaQdph6HJVeU/QYxYsWElFEFJeBXzesgjaRIt1senNX1vJ9fYOyOeATec8tUrAUXNzaX+vW6Lz2pZRVVEM9Sq5HUhSo0O+rJnROKPAqlqlTO++8Al8zLf80ZM4eEz4QVmlliwO9MKjNoyBha1ppYurHwhzZ5DmR4Dz6hB+zK04HLve8QqkEjMO/ndEEp5bUB0YRu4HlHhACX6K5zScud056+ISPuuCm7xKo3B6nT/rN0VqY2hROQgoFgWF8ozVKSB8mrrHbOEa0MtqqF0zyvEsRR+LBcdG/fg/0Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ttAQUT9oaBSccgpLNPFsHih6Q/up1j5LBKjPOrlSrGU=; b=sH4Y02Q9gLChj3Lrd2jkljpYqQEwC+RWxSYdviCS4Gobfwy4vdyh1MyDibULTWPm3FfzstAgEKMy28E5XddmfkzB75TceDS0VeUgzZ3xW4bIp3y3D+aCxbEov5JV8d3FM1Ri/XwfG3XwlWEswKrBA80NgQDLsLvZXKpDiXIo/utu8CZP8L02+/kg24MSlWp3ADRaIRbUhByLL8VacOUkgvNDBh6HfBUcZcsBG0T/kUAc7rKo8yOAjtdZ5ApuxLrC48GlPk+BlAZLeAPFqqL5wEFEf/nsUD8gihpT3CDMNE94OM8J8NrGrTeDG86740CBtChQUmz9/O+WrZm64eh64Q== Received: from BYAPR05CA0070.namprd05.prod.outlook.com (2603:10b6:a03:74::47) by IA1PR12MB7734.namprd12.prod.outlook.com (2603:10b6:208:422::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.12; Thu, 6 Nov 2025 10:29:40 +0000 Received: from SJ1PEPF00002322.namprd03.prod.outlook.com (2603:10b6:a03:74:cafe::3b) by BYAPR05CA0070.outlook.office365.com (2603:10b6:a03:74::47) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9320.5 via Frontend Transport; Thu, 6 Nov 2025 10:29:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF00002322.mail.protection.outlook.com (10.167.242.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Thu, 6 Nov 2025 10:29:40 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:29:29 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 6 Nov 2025 02:29:29 -0800 Received: from inno-vm-xubuntu (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 6 Nov 2025 02:29:19 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 7/7] sample: rust: pci: add tests for config space routines Date: Thu, 6 Nov 2025 12:27:53 +0200 Message-ID: <20251106102753.2976-8-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106102753.2976-1-zhiw@nvidia.com> References: <20251106102753.2976-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|IA1PR12MB7734:EE_ X-MS-Office365-Filtering-Correlation-Id: 484bdd1e-b9ec-462c-946f-08de1d1f64b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?qtNgyf1s0jxWiWFe8Y/08wUIqvd2wakb5iHLgJa8ydL53IDSQHygDQh7s1TP?= =?us-ascii?Q?d2oUmE2ilWjGCqrqOfS0+NCJRXYuvYCw0FuN1oNckfeIjoSL47cGJwWx3dX1?= =?us-ascii?Q?L9HlLQmldG1OVVyIjJ522+a4CNDWtKV6ONoukSoXyTTDXOWQn+caGpyd2aOe?= =?us-ascii?Q?vOjaO99zQMnat36n2JM2l9hcuQH+gxLBhYM37VyDyhFi/yBZHmXgsiWdC8pO?= =?us-ascii?Q?fXMbXi7jHwG6Vn/9n50KcADw6SKKaqD8EC6nGqVCRugDZVrzy67yY6h/eKHh?= =?us-ascii?Q?lyaYbroImKFgj1w+grAi1KJoFXGYGm3GT7Ag6lOxJ65nYWID5jVOMSrIt0Qf?= =?us-ascii?Q?qS64CfcatXELDbWzyrW9DKZHoTxeHwtYOfiEPFHuC0QcNu0Edlr0KrxJ0Sw0?= =?us-ascii?Q?SenG1+FWxR5N+vf59KVn4UnHfH7WRuaDppfITc51HtGPd/ZQvoRHejz37vvl?= =?us-ascii?Q?eC+QHUh+RLWbUF0sW04DZpV6uDpyBaeOIfLGcTV50y71ZC7g1SqK2oAVRFJ3?= =?us-ascii?Q?1AP78F0raFTeXVlji+QsH6J/0pWj5eA224WqoDzW4JwuLBBmlt8ruSDIM5hm?= =?us-ascii?Q?2ZwsgDnAnOOZ3kOuJz0/9RUSj3hxifua/TtJz0SdnKYzJn10ij258BCM5Ldx?= =?us-ascii?Q?ECWOGzmP1j6ZOSku9DZZuY66FlDKC9a16AnclDN4lyOosd60LlW/iDROgiPx?= =?us-ascii?Q?d86jcH40iu6zMvmJ4NoZTHyeV3oNy/e9rUQTfD67xrjlyLqUqPhdiiUly1QR?= =?us-ascii?Q?XRPLHw4dDvDVAa6oj7jlcgAJpLu1lgkDidBeTzJlFH2naH4/gHMVogVGH1H1?= =?us-ascii?Q?38kfAwL8X9YuQn/oTjX8znvOs7Pe+ejPKgnlhznKBFDU6fpCEbRYOZnULG9I?= =?us-ascii?Q?BHDCjtvtg9W1jb7trAb/9U9WkeuPgfFL3pGIWURkxbWtZEnzzCKZLYPqkQP6?= =?us-ascii?Q?zunqZFhCAXyoo5FTbTsVtkswo0uFgqR8NhZ0sY3hmZgk0YwIgAYs9WJuD9gr?= =?us-ascii?Q?n7DjHuj7jfEiJ8DFJiEeTOPaLWPmh/bv7I2srxlb66JIs/5av3n0oqe8mn78?= =?us-ascii?Q?ZW7Y63OMA2cYLCnHfObOWTOXki7MuZx1M3VfKWBEtlxyJMAQ1QEqOdvteE1E?= =?us-ascii?Q?clqDA5di0vfPnHR5D3bI9dN0gGItTDc0Tak53ln1ZNBODflsdrWkKQ7Ck+5L?= =?us-ascii?Q?FHmb6bpbEtzVTO+bAfzoxyLCuOn2XE+RzT0Atti0hUmoT18yBxpFo+lwsL58?= =?us-ascii?Q?c6rQ06q69JPjHKkcsjl4GRqBBv2adJv1r0aJEU4oseKlsBVh7kmM4KNkpurp?= =?us-ascii?Q?YV15ZXneqbnU74ePOka5e6/bl0sZFNaKFLtL3f0wUJn1dvnFeM0eaj81bqdp?= =?us-ascii?Q?9YjvBF8Zsj+9A0v+BY1OalOWDCW9FdCQ8cjLrsgFiXac3sdrQ7NTwbksPVNG?= =?us-ascii?Q?Q5YGHYJId6WIKU1Lke07D8OtBJ0ZdRl/AqyVwrT2ikJsCF/XOexp7jbCYW2E?= =?us-ascii?Q?oaa/ErEoueVKzt1WQofitYuecNvK979FprxWUvxuUUa8ckyc1HDbnuWnPbg0?= =?us-ascii?Q?guA15hggGF9IkAgIqK8=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:29:40.3758 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 484bdd1e-b9ec-462c-946f-08de1d1f64b7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002322.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7734 Content-Type: text/plain; charset="utf-8" Add tests exercising the PCI configuration space helpers. Suggested-by: Danilo Krummrich Signed-off-by: Zhi Wang --- samples/rust/rust_driver_pci.rs | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci= .rs index 74b93ca7c338..8f549b2100bc 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -67,6 +67,32 @@ fn testdev(index: &TestIndex, bar: &Bar0) -> Result= { =20 Ok(bar.read32(Regs::COUNT)) } + + fn config_space(pdev: &pci::Device) -> Result { + let config =3D pdev.config_space()?; + + // TODO: use the register!() macro for defining PCI configuration = space registers once it + // has been move out of nova-core. + dev_info!( + pdev.as_ref(), + "pci-testdev config space read8 rev ID: {:x}\n", + config.read8(0x8) + ); + + dev_info!( + pdev.as_ref(), + "pci-testdev config space read16 vendor ID: {:x}\n", + config.read16(0) + ); + + dev_info!( + pdev.as_ref(), + "pci-testdev config space read32 BAR 0: {:x}\n", + config.read32(0x10) + ); + + Ok(()) + } } =20 impl pci::Driver for SampleDriver { @@ -98,6 +124,7 @@ fn probe(pdev: &pci::Device, info: &Self::IdInfo) = -> impl PinInit