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Thu, 06 Nov 2025 03:34:38 -0800 (PST) From: Bartosz Golaszewski Date: Thu, 06 Nov 2025 12:34:05 +0100 Subject: [PATCH v8 09/11] crypto: qce - Add BAM DMA support for crypto register I/O Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251106-qcom-qce-cmd-descr-v8-9-ecddca23ca26@linaro.org> References: <20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org> In-Reply-To: <20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org> To: Vinod Koul , Jonathan Corbet , Thara Gopinath , Herbert Xu , "David S. Miller" , Udit Tiwari , Daniel Perez-Zoghbi , Md Sadre Alam Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6220; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=M4HnnFvam5oHPkSCa/uXNClDyduly5DTAPL1JsMNmgQ=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBpDIe9uaFsYlEGaYn2NGGdVlGgTHNmB4zrBOISN JQXO9aEbQmJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaQyHvQAKCRARpy6gFHHX cloMD/9OF3fFH2ocL8Z7nOwKg8hP3vnD3EG40rjc7S45XAgFiuaaVtEYGt47J1hn5auhZhE2IAK kljR1tQxdyDJW1iqFp7nDuO/6cR87scNn07feUv4MqrP/yjCnDSRBaY8DfzMzyeioKtW0c4E0cO u4IM29wIE7jBKe7FvbkNWyEqyNTA9yE/4pKY26qtWErFlFGfGis6PogGVvL34xh0vrPOTclL5b/ I61MlHHlV/T5frrjCBD+E6okzpEbUhXzDWewFOeWArXuPtzbtu4PkrIuG81lVG9nFBmjEDpP67w akLLNOZ0l7MfRCa61ndHr1qc5Dk9mmL2ch8OKfzHr0KuCfngaNyNaCxKv69yLKsvd89UdhYVgxB uF0y5bbl3nX9j0zu+UqZjNhJcaSenCGyAZIHrw5wOZp+IXQ6UP4JWJqaIdLEqSWBcp88s8sdQYD +a3Tk2pfDYFS+iE76C7u8daHc0E27rpHcvFF4KQJnC0WQEFWrCkM7ORDJf8ZuqREmTewbUCVDmC fbxCzT4h0rlJIZmqVX4W7zUMhiGoOjVUgHGBeHPodk0P4qfOcGEfvmlKmktTJvJdFoie8341Nxu VJ8ghg8DGUAysH97WgUNNEdnQ3twkr0TPoMUzlF5u+5kcn7n7kCsGA+P8DKBcvFDV0HwPL22Nz7 HlMl68BdRVIuL1w== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Implement the infrastructure for performing register I/O over BAM DMA, not CPU. No functional change yet. Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/core.h | 4 ++ drivers/crypto/qce/dma.c | 109 ++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/crypto/qce/dma.h | 5 +++ 3 files changed, 118 insertions(+) diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index a80e12eac6c87e5321cce16c56a4bf5003474ef0..d238097f834e4605f3825f23d03= 16d4196439116 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -30,6 +30,8 @@ * @base_dma: base DMA address * @base_phys: base physical address * @dma_size: size of memory mapped for DMA + * @read_buf: Buffer for DMA to write back to + * @read_buf_dma: Mapped address of the read buffer * @async_req_enqueue: invoked by every algorithm to enqueue a request * @async_req_done: invoked by every algorithm to finish its request */ @@ -49,6 +51,8 @@ struct qce_device { dma_addr_t base_dma; phys_addr_t base_phys; size_t dma_size; + __le32 *read_buf; + dma_addr_t read_buf_dma; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index bfa54d3401ca095a089656e81a37474d6f788acf..9bb9a8246cb054dd16b9ab6cf5c= fabef51b1ef83 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -4,6 +4,8 @@ */ =20 #include +#include +#include #include #include =20 @@ -11,6 +13,98 @@ #include "dma.h" =20 #define QCE_IGNORE_BUF_SZ (2 * QCE_BAM_BURST_SIZE) +#define QCE_BAM_CMD_SGL_SIZE 128 +#define QCE_BAM_CMD_ELEMENT_SIZE 128 +#define QCE_MAX_REG_READ 8 + +struct qce_desc_info { + struct dma_async_tx_descriptor *dma_desc; + enum dma_data_direction dir; +}; + +struct qce_bam_transaction { + struct bam_cmd_element bam_ce[QCE_BAM_CMD_ELEMENT_SIZE]; + struct scatterlist wr_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct qce_desc_info *desc; + u32 bam_ce_idx; + u32 pre_bam_ce_idx; + u32 wr_sgl_cnt; +}; + +void qce_clear_bam_transaction(struct qce_device *qce) +{ + struct qce_bam_transaction *bam_txn =3D qce->dma.bam_txn; + + bam_txn->bam_ce_idx =3D 0; + bam_txn->wr_sgl_cnt =3D 0; + bam_txn->bam_ce_idx =3D 0; + bam_txn->pre_bam_ce_idx =3D 0; +} + +int qce_submit_cmd_desc(struct qce_device *qce) +{ + struct qce_desc_info *qce_desc =3D qce->dma.bam_txn->desc; + struct qce_bam_transaction *bam_txn =3D qce->dma.bam_txn; + struct dma_async_tx_descriptor *dma_desc; + struct dma_chan *chan =3D qce->dma.rxchan; + unsigned long attrs =3D DMA_PREP_CMD; + dma_cookie_t cookie; + unsigned int mapped; + int ret; + + mapped =3D dma_map_sg_attrs(qce->dev, bam_txn->wr_sgl, bam_txn->wr_sgl_cn= t, + DMA_TO_DEVICE, attrs); + if (!mapped) + return -ENOMEM; + + dma_desc =3D dmaengine_prep_slave_sg(chan, bam_txn->wr_sgl, bam_txn->wr_s= gl_cnt, + DMA_MEM_TO_DEV, attrs); + if (!dma_desc) { + dma_unmap_sg(qce->dev, bam_txn->wr_sgl, bam_txn->wr_sgl_cnt, DMA_TO_DEVI= CE); + return -ENOMEM; + } + + qce_desc->dma_desc =3D dma_desc; + cookie =3D dmaengine_submit(qce_desc->dma_desc); + + ret =3D dma_submit_error(cookie); + if (ret) + return ret; + + qce_dma_issue_pending(&qce->dma); + + return 0; +} + +static void qce_prep_dma_cmd_desc(struct qce_device *qce, struct qce_dma_d= ata *dma, + unsigned int addr, void *buf) +{ + struct qce_bam_transaction *bam_txn =3D dma->bam_txn; + struct bam_cmd_element *bam_ce_buf; + int bam_ce_size, cnt, idx; + + idx =3D bam_txn->bam_ce_idx; + bam_ce_buf =3D &bam_txn->bam_ce[idx]; + bam_prep_ce_le32(bam_ce_buf, addr, BAM_WRITE_COMMAND, *((__le32 *)buf)); + + bam_ce_buf =3D &bam_txn->bam_ce[bam_txn->pre_bam_ce_idx]; + bam_txn->bam_ce_idx++; + bam_ce_size =3D (bam_txn->bam_ce_idx - bam_txn->pre_bam_ce_idx) * sizeof(= *bam_ce_buf); + + cnt =3D bam_txn->wr_sgl_cnt; + + sg_set_buf(&bam_txn->wr_sgl[cnt], bam_ce_buf, bam_ce_size); + + ++bam_txn->wr_sgl_cnt; + bam_txn->pre_bam_ce_idx =3D bam_txn->bam_ce_idx; +} + +void qce_write_dma(struct qce_device *qce, unsigned int offset, u32 val) +{ + unsigned int reg_addr =3D ((unsigned int)(qce->base_phys) + offset); + + qce_prep_dma_cmd_desc(qce, &qce->dma, reg_addr, &val); +} =20 int devm_qce_dma_request(struct qce_device *qce) { @@ -29,6 +123,21 @@ int devm_qce_dma_request(struct qce_device *qce) if (!dma->result_buf) return -ENOMEM; =20 + dma->bam_txn =3D devm_kzalloc(dev, sizeof(*dma->bam_txn), GFP_KERNEL); + if (!dma->bam_txn) + return -ENOMEM; + + dma->bam_txn->desc =3D devm_kzalloc(dev, sizeof(*dma->bam_txn->desc), GFP= _KERNEL); + if (!dma->bam_txn->desc) + return -ENOMEM; + + sg_init_table(dma->bam_txn->wr_sgl, QCE_BAM_CMD_SGL_SIZE); + + qce->read_buf =3D dmam_alloc_coherent(qce->dev, QCE_MAX_REG_READ * sizeof= (*qce->read_buf), + &qce->read_buf_dma, GFP_KERNEL); + if (!qce->read_buf) + return -ENOMEM; + return 0; } =20 diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 483789d9fa98e79d1283de8297bf2fc2a773f3a7..f05dfa9e6b25bd60e32f45079a8= bc7e6a4cf81f9 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -8,6 +8,7 @@ =20 #include =20 +struct qce_bam_transaction; struct qce_device; =20 /* maximum data transfer block size between BAM and CE */ @@ -32,6 +33,7 @@ struct qce_dma_data { struct dma_chan *txchan; struct dma_chan *rxchan; struct qce_result_dump *result_buf; + struct qce_bam_transaction *bam_txn; }; =20 int devm_qce_dma_request(struct qce_device *qce); @@ -43,5 +45,8 @@ int qce_dma_terminate_all(struct qce_dma_data *dma); struct scatterlist * qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, unsigned int max_len); +void qce_write_dma(struct qce_device *qce, unsigned int offset, u32 val); +int qce_submit_cmd_desc(struct qce_device *qce); +void qce_clear_bam_transaction(struct qce_device *qce); =20 #endif /* _DMA_H_ */ --=20 2.51.0