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Thu, 06 Nov 2025 03:34:37 -0800 (PST) From: Bartosz Golaszewski Date: Thu, 06 Nov 2025 12:34:04 +0100 Subject: [PATCH v8 08/11] crypto: qce - Map crypto memory for DMA Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251106-qcom-qce-cmd-descr-v8-8-ecddca23ca26@linaro.org> References: <20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org> In-Reply-To: <20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org> To: Vinod Koul , Jonathan Corbet , Thara Gopinath , Herbert Xu , "David S. Miller" , Udit Tiwari , Daniel Perez-Zoghbi , Md Sadre Alam Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3084; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=YrlK+FCBMpnN0mtgQnv4x5y020oK7SmjbrJXDNXzn5g=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBpDIe9PAKKUyb4afZt0r5bIvZ+oWZJdtCAEcub9 pOHJZBRI7qJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaQyHvQAKCRARpy6gFHHX chpXD/9NByZYb24rxG/Ghz2t9YYbHOU4a7LXMIg07ieVmtBqJwlhLP7h0sKuRaxHxREFUKO2Cac XvK0LjqloxZ6+ORHjrLB9zCDOAYud6CAbxZASMdM7nlv4LdWV8xPTxtHpM5KkGRPDSOkSW5WCch eBBrjBHTUQSdNUi+Z3/KrrBzuIIlk+LQzgQ4wPLqDf9mJ0YMemD2clgtLdILmqyYzWX8Wzt5iBp Clru+Ab+RQ8AD4rZP8+UMMUcQ1QMCZZ8C54WNeJPUgDsRlGJ/oGhZBiMuFOZrFIHB3UqdrrnRR5 e8Zl4xh90DX51C9Ga5vCx6lgB37BT+dMpUTzW4vI6MnO6VRDLHRN2oudv2jv0MI/5HtC3rzFdMD sSR4wRIz+hVgpOj3t1jjdn2l5wmf7Ri/UzhbnfZKIY+PVFqBlcV4HnNG1eHKo+2x4imE5UGYd/J FWP/rUBnoI7G9ld+50zwCE2kNXsFcRB0ug5fDM0VCvja8L4UxhvbYY0MqL40j3BiwdKJapuRBY2 iYbjGh9rI6R5NFLgeCEeYKNk2jrCi8sRZTlzpXP0rERk2yPNHSbaBi1T+52NzxOry3uZ6BGN/Yg hEpEM2VJXEIiH/UBD+o1L3l0Cln4piKV9RagSk83wK3BgvIfskBCmMikKWvtFqJqU2oFMeGd2yw WsgEqAgozobeU4A== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski As the first step in converting the driver to using DMA for register I/O, let's map the crypto memory range. Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/core.c | 25 +++++++++++++++++++++++-- drivers/crypto/qce/core.h | 6 ++++++ 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index aac65041f585221b800f4d7756e4bf9d9f21d0a0..e486d366c0d63aa0e1f545da926= 5e8ce689b50e0 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -186,10 +186,19 @@ static int qce_check_version(struct qce_device *qce) return 0; } =20 +static void qce_crypto_unmap_dma(void *data) +{ + struct qce_device *qce =3D data; + + dma_unmap_resource(qce->dev, qce->base_dma, qce->dma_size, + DMA_BIDIRECTIONAL, 0); +} + static int qce_crypto_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct qce_device *qce; + struct resource *res; int ret; =20 qce =3D devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); @@ -199,7 +208,7 @@ static int qce_crypto_probe(struct platform_device *pde= v) qce->dev =3D dev; platform_set_drvdata(pdev, qce); =20 - qce->base =3D devm_platform_ioremap_resource(pdev, 0); + qce->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(qce->base)) return PTR_ERR(qce->base); =20 @@ -245,7 +254,19 @@ static int qce_crypto_probe(struct platform_device *pd= ev) qce->async_req_enqueue =3D qce_async_request_enqueue; qce->async_req_done =3D qce_async_request_done; =20 - return devm_qce_register_algs(qce); + ret =3D devm_qce_register_algs(qce); + if (ret) + return ret; + + qce->dma_size =3D resource_size(res); + qce->base_dma =3D dma_map_resource(dev, res->start, qce->dma_size, + DMA_BIDIRECTIONAL, 0); + qce->base_phys =3D res->start; + ret =3D dma_mapping_error(dev, qce->base_dma); + if (ret) + return ret; + + return devm_add_action_or_reset(qce->dev, qce_crypto_unmap_dma, qce); } =20 static const struct of_device_id qce_crypto_of_match[] =3D { diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index f092ce2d3b04a936a37805c20ac5ba78d8fdd2df..a80e12eac6c87e5321cce16c56a= 4bf5003474ef0 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -27,6 +27,9 @@ * @dma: pointer to dma data * @burst_size: the crypto burst size * @pipe_pair_id: which pipe pair id the device using + * @base_dma: base DMA address + * @base_phys: base physical address + * @dma_size: size of memory mapped for DMA * @async_req_enqueue: invoked by every algorithm to enqueue a request * @async_req_done: invoked by every algorithm to finish its request */ @@ -43,6 +46,9 @@ struct qce_device { struct qce_dma_data dma; int burst_size; unsigned int pipe_pair_id; + dma_addr_t base_dma; + phys_addr_t base_phys; + size_t dma_size; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); --=20 2.51.0