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Thu, 06 Nov 2025 03:34:42 -0800 (PST) From: Bartosz Golaszewski Date: Thu, 06 Nov 2025 12:34:07 +0100 Subject: [PATCH v8 11/11] crypto: qce - Switch to using BAM DMA for crypto I/O Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251106-qcom-qce-cmd-descr-v8-11-ecddca23ca26@linaro.org> References: <20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org> In-Reply-To: <20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org> To: Vinod Koul , Jonathan Corbet , Thara Gopinath , Herbert Xu , "David S. Miller" , Udit Tiwari , Daniel Perez-Zoghbi , Md Sadre Alam Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6106; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=2zlVAHXO/DOwordNK3r9sCFLHH3vkgBdbL2WMJAKOzQ=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBpDIe9+1fIkMp/fEXn98fhQgw9tFW/4REfExT+H vU/2dMogemJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaQyHvQAKCRARpy6gFHHX crcnEADK/TmYg5xmjUrAjllFl8IKDa0f455O8YfKfKz4A4LxicVDLIxSp8O5LTaP6UvBKGtCTxV r4hadowYw+W2k/Xdt8Kw/27fBjoy4CnByQhWvNIsIWb6HbePWFP+0lpdCRd3hiurvyXEnYexLN2 P+bO7meTR3UwUrCAPOYv/GHerTQgDBV+HZKHwI70CRqLwA2CadFjVWkYKTu07/pvICd5gCTv6EP eXmIuISa1Nb2sxnSJjzcIhzX7QtSzxZUZB+NhhBB1W3lyHAvin0ZjhV9GGzScUhKKQA+GsYWsIT XlOGfGNk+nlJm0lK8/3xFWu5n57z6iewexnhZvXhOo7LF+VZxyI1e4OOhI5D0hvhA7uPHxbj8Os oNAXqKAi+pOTivBdtMQZs8lVzpHi7TTTUH6MeZpTOTglj5zLtBVJ1jhSaOY+gLz992XLBcv2+D+ ryDD89nYOoB7p8EVyBGc3biZlxhsTNCHXdWriVCAmt698iupYt44Ba2X1KUotJV1DndTdHjmzAV 8laH52cTwVV/JKDoiWbA+l92liEZz0YT36YyfOsIH9wKF896gdVLbG2qTjW05wKZhfiFq7oWUnG V+1OvqIdw/WIYOMGomtxserWMNTz/64RcLxz7LQZpF5xYE451IcSOZcROwHayijUE+d2xTSpwx4 2nmFiD4tTZ11bdw== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski With everything else in place, we can now switch to actually using the BAM DMA for register I/O with DMA engine locking. Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/aead.c | 10 ++++++++++ drivers/crypto/qce/common.c | 21 ++++++++++----------- drivers/crypto/qce/sha.c | 8 ++++++++ drivers/crypto/qce/skcipher.c | 7 +++++++ 4 files changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index 11cec08544c912e562bf4b33d9a409f0e69a0ada..0fc69b019929342e14d3af8e24d= 7629ab171bc60 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -63,6 +63,10 @@ static void qce_aead_done(void *data) sg_free_table(&rctx->dst_tbl); } =20 + error =3D qce_bam_unlock(qce); + if (error) + dev_err(qce->dev, "aead: failed to unlock the BAM\n"); + error =3D qce_check_status(qce, &status); if (error < 0 && (error !=3D -EBADMSG)) dev_err(qce->dev, "aead operation error (%x)\n", status); @@ -188,6 +192,8 @@ qce_aead_ccm_prepare_buf_assoclen(struct aead_request *= req) struct crypto_aead *tfm =3D crypto_aead_reqtfm(req); struct qce_aead_reqctx *rctx =3D aead_request_ctx_dma(req); struct qce_aead_ctx *ctx =3D crypto_aead_ctx(tfm); + struct qce_alg_template *tmpl =3D to_aead_tmpl(crypto_aead_reqtfm(req)); + struct qce_device *qce =3D tmpl->qce; unsigned int assoclen =3D rctx->assoclen; unsigned int adata_header_len, cryptlen, totallen; gfp_t gfp; @@ -200,6 +206,10 @@ qce_aead_ccm_prepare_buf_assoclen(struct aead_request = *req) cryptlen =3D rctx->cryptlen; totallen =3D cryptlen + req->assoclen; =20 + ret =3D qce_bam_lock(qce); + if (ret) + return ret; + /* Get the msg */ msg_sg =3D scatterwalk_ffwd(__sg, req->src, req->assoclen); =20 diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 74756c222fed6d0298eb6c957ed15b8b7083b72f..930006aaba4accb51576ecfb84a= a9cf20849a72f 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -14,6 +14,7 @@ #include "cipher.h" #include "common.h" #include "core.h" +#include "dma.h" #include "regs-v5.h" #include "sha.h" #include "aead.h" @@ -25,7 +26,7 @@ static inline u32 qce_read(struct qce_device *qce, u32 of= fset) =20 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val) { - writel(val, qce->base + offset); + qce_write_dma(qce, offset, val); } =20 static inline void qce_write_array(struct qce_device *qce, u32 offset, @@ -82,6 +83,8 @@ static void qce_setup_config(struct qce_device *qce) { u32 config; =20 + qce_clear_bam_transaction(qce); + /* get big endianness */ config =3D qce_config_reg(qce, 0); =20 @@ -90,12 +93,14 @@ static void qce_setup_config(struct qce_device *qce) qce_write(qce, REG_CONFIG, config); } =20 -static inline void qce_crypto_go(struct qce_device *qce, bool result_dump) +static int qce_crypto_go(struct qce_device *qce, bool result_dump) { if (result_dump) qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); else qce_write(qce, REG_GOPROC, BIT(GO_SHIFT)); + + return qce_submit_cmd_desc(qce); } =20 #if defined(CONFIG_CRYPTO_DEV_QCE_SHA) || defined(CONFIG_CRYPTO_DEV_QCE_AE= AD) @@ -223,9 +228,7 @@ static int qce_setup_regs_ahash(struct crypto_async_req= uest *async_req) config =3D qce_config_reg(qce, 1); qce_write(qce, REG_CONFIG, config); =20 - qce_crypto_go(qce, true); - - return 0; + return qce_crypto_go(qce, true); } #endif =20 @@ -386,9 +389,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_= request *async_req) config =3D qce_config_reg(qce, 1); qce_write(qce, REG_CONFIG, config); =20 - qce_crypto_go(qce, true); - - return 0; + return qce_crypto_go(qce, true); } #endif =20 @@ -535,9 +536,7 @@ static int qce_setup_regs_aead(struct crypto_async_requ= est *async_req) qce_write(qce, REG_CONFIG, config); =20 /* Start the process */ - qce_crypto_go(qce, !IS_CCM(flags)); - - return 0; + return qce_crypto_go(qce, !IS_CCM(flags)); } #endif =20 diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index 0c7aab711b7b8434d5f89ab4565ef4123fc5322e..286477a3001248e745d79b209ae= bb6ed6bf11f62 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -60,6 +60,10 @@ static void qce_ahash_done(void *data) rctx->byte_count[0] =3D cpu_to_be32(result->auth_byte_count[0]); rctx->byte_count[1] =3D cpu_to_be32(result->auth_byte_count[1]); =20 + error =3D qce_bam_unlock(qce); + if (error) + dev_err(qce->dev, "ahash: failed to unlock the BAM\n"); + error =3D qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "ahash operation error (%x)\n", status); @@ -90,6 +94,10 @@ static int qce_ahash_async_req_handle(struct crypto_asyn= c_request *async_req) rctx->authklen =3D AES_KEYSIZE_128; } =20 + ret =3D qce_bam_lock(qce); + if (ret) + return ret; + rctx->src_nents =3D sg_nents_for_len(req->src, req->nbytes); if (rctx->src_nents < 0) { dev_err(qce->dev, "Invalid numbers of src SG.\n"); diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index cab796cd7e43c548a49df468b2dde84942c5bd87..8317c79fb9c2b209884187d6565= 5d04c580e9cde 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -51,6 +51,9 @@ static void qce_skcipher_done(void *data) dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst); =20 sg_free_table(&rctx->dst_tbl); + error =3D qce_bam_unlock(qce); + if (error) + dev_err(qce->dev, "skcipher: failed to unlock the BAM\n"); =20 error =3D qce_check_status(qce, &status); if (error < 0) @@ -78,6 +81,10 @@ qce_skcipher_async_req_handle(struct crypto_async_reques= t *async_req) rctx->ivsize =3D crypto_skcipher_ivsize(skcipher); rctx->cryptlen =3D req->cryptlen; =20 + ret =3D qce_bam_lock(qce); + if (ret) + return ret; + diff_dst =3D (req->src !=3D req->dst) ? true : false; dir_src =3D diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst =3D diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL; --=20 2.51.0