From nobody Fri Dec 19 16:03:35 2025 Received: from mxout3.routing.net (mxout3.routing.net [134.0.28.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDEDB28C871; Wed, 5 Nov 2025 19:50:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762372254; cv=none; b=oQ/1FGOvkZXUam/SEn8ZnfqCzyuDsRYCIdhvMlm5to/E48U4xmwtFGEOuqmvmqIxbG9+H6FSE05zfLykI0/NVB/NOHaJLuUzs6hXF1TGJUYtVumhULrWrA/fB4uPa9DLQLqaL5YYJ2+m9MphUD2DtHT6YFDePeTt0mY2PvELyio= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762372254; c=relaxed/simple; bh=Eei/Fg44a1VAwWtgrFzmkgnsu8ar5EBy5bcRlU2z1fk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Zu51vBoDPgiZY7aWdxcQ/XenjNDhD8VlYEog0O/9wsr8ze1Yob4GgCSnNZb8o/hx38bwQxbrzm5cm5PUTP7/Si5o1c2NtVNxD+kTGLJ3yyt5/meoGEuPjIGnTmvi9jhy9teKQ4NemMuI3Glz6uLSA++SF1r/zqwdBMRXz80p4bM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=jIHC/H4T; arc=none smtp.client-ip=134.0.28.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="jIHC/H4T" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout3.routing.net (Postfix) with ESMTP id 914E16060E; Wed, 5 Nov 2025 19:50:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=routing; t=1762372246; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aW9wKfFFNtTI5Gb776bIaUwjTcw0cEaYja0hla1rLQ0=; b=jIHC/H4Tc2ouqaFcS8VtGCFHrJRpXlko7eF0CsyON+RgpgUbkf2sn0n/XkrZVD/NEPHz1y BUkxB4A3HHjGY0/uXkrrigl/6Slocs8DgE3oxb70cfTcIJ41ggkfJx/wP5MtOOnSY9WI8i 5lUt76ll42fGcQgigKvCM5JVJaZyqMk= Received: from frank-u24.. (fttx-pool-194.15.81.38.bambit.de [194.15.81.38]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id 4A40D122700; Wed, 5 Nov 2025 19:50:46 +0000 (UTC) From: Frank Wunderlich To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , Sean Wang , Daniel Golle , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 3/5] arm64: dts: mediatek: mt7988: Add devicetree for BananaPi R4 Pro Date: Wed, 5 Nov 2025 20:50:03 +0100 Message-ID: <20251105195007.199229-4-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105195007.199229-1-linux@fw-web.de> References: <20251105195007.199229-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add devicetree for Bpi-R4-Pro. BananaPi R4 Pro is a MT7988A based board which exists in 2 different hardware versions: - 4E: 4 GB RAM and using internal 2.5G Phy for WAN-Combo - 8X: 8 GB RAM and 2x Aeonsemi AS21010P 10G phys common parts: - MediaTek MT7988A Quad-core Arm Corex-A73,1.8GHz processor - 8GB eMMC flash - 256MB SPI-NAND Flash - Micro SD card slot - 1x 10G SFP+ WAN - 1x 10G SFP+ LAN - 4x 2.5G RJ45 LAN (MxL86252C) - 1x 1G RJ45 LAN (MT7988 internal switch) - 2x miniPCIe slots with PCIe3.0 2lane interface for Wi-Fi NIC - 2x M.2 M-KEY slots with PCIe3.0 1lane interface for NVME SSD - 3x M.2 B-KEY slots with USB3.2 for 5G Module (PCIe shared with key-m) - 1x USB3.2 slot - 1x USB2.0 slot - 1x USB TypeC Debug Console - 2x13 PIN Header for expanding application https://docs.banana-pi.org/en/BPI-R4_Pro/BananaPi_BPI-R4_Pro The PCIe is per default in key-m state and can be changed to key-b with the pcie-overlays. Signed-off-by: Frank Wunderlich --- v2: - squashed "mt7988a: Add label for ssusb0" - drop bootargs - update based on angelos review - drop gpio-header table comment because header is not yet part of this dts - dropped delete-property for non-existent "mediatek,p0_speed_fixup" - fix voltage displayed for buck4/ldo based on schematic - reorder fan after eth node (alphanumeric) - reorder spi-tx after spi-rx (alphanumeric) - follow reg first, then others also for spi-nand partitions - drop 2pg5 phy disabling node (due to new patch disabling by default) - change order of pinctrl (first number than names) - fix commit prefix (mediatek was missing) --- arch/arm64/boot/dts/mediatek/Makefile | 4 + .../mt7988a-bananapi-bpi-r4-pro-4e.dts | 16 + .../mt7988a-bananapi-bpi-r4-pro-8x.dts | 16 + .../mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 534 ++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- 5 files changed, 571 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pr= o-4e.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pr= o-8x.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pr= o.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index a4df4c21399e..8640e5f32d4b 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -24,6 +24,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7988a-bananapi-bpi-r4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7988a-bananapi-bpi-r4-2g5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7988a-bananapi-bpi-r4-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7988a-bananapi-bpi-r4-pro-4e.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7988a-bananapi-bpi-r4-pro-8x.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7988a-bananapi-bpi-r4-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8173-elm.dtb @@ -111,4 +113,6 @@ DTC_FLAGS_mt7986a-bananapi-bpi-r3 :=3D -@ DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini :=3D -@ DTC_FLAGS_mt7988a-bananapi-bpi-r4 :=3D -@ DTC_FLAGS_mt7988a-bananapi-bpi-r4-2g5 :=3D -@ +DTC_FLAGS_mt7988a-bananapi-bpi-r4-pro-4e :=3D -@ +DTC_FLAGS_mt7988a-bananapi-bpi-r4-pro-8x :=3D -@ DTC_FLAGS_mt8395-radxa-nio-12l :=3D -@ diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dt= s b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts new file mode 100644 index 000000000000..c7ea6e88c4f4 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; + +#include "mt7988a-bananapi-bpi-r4-pro.dtsi" + +/ { + model =3D "Bananapi BPI-R4"; + compatible =3D "bananapi,bpi-r4-pro-4e", + "bananapi,bpi-r4-pro", + "mediatek,mt7988a"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dt= s b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts new file mode 100644 index 000000000000..c9a0e69e9dd5 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; + +#include "mt7988a-bananapi-bpi-r4-pro.dtsi" + +/ { + model =3D "Bananapi BPI-R4"; + compatible =3D "bananapi,bpi-r4-pro-8x", + "bananapi,bpi-r4-pro", + "mediatek,mt7988a"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi = b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi new file mode 100644 index 000000000000..a48132f09411 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi @@ -0,0 +1,534 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam.Shih + * Author: Frank Wunderlich + */ + +/dts-v1/; + +#include "mt7988a.dtsi" +#include +#include +#include +#include + +/ { + aliases { + ethernet0 =3D &gmac0; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + /* PCA9548 (0-0070) provides 4 i2c channels */ + i2c3 =3D &imux0; + i2c4 =3D &imux1_sfp1; + i2c5 =3D &imux2_sfp2; + i2c6 =3D &imux3_wifi; + }; + + chosen { + stdout-path =3D &serial0; + }; + + fan: pwm-fan { + compatible =3D "pwm-fan"; + /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty)= */ + cooling-levels =3D <0 80 128 255>; + pinctrl-0 =3D <&pwm0_pins>; + pinctrl-names =3D "default"; + pwms =3D <&pwm 0 50000>; + #cooling-cells =3D <2>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + button-reset { + label =3D "reset"; + gpios =3D <&pio 13 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + button-wps { + label =3D "WPS"; + gpios =3D <&pio 14 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led_red: sys-led-red { + color =3D ; + gpios =3D <&pca9555 15 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + + led_blue: sys-led-blue { + color =3D ; + gpios =3D <&pca9555 14 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + }; + + reg_1p8v: regulator-dvdd1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "DVDD1V8_SOC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3v3vd { + compatible =3D "regulator-fixed"; + regulator-name =3D "3V3VD"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* SFP1 cage (LAN) */ + sfp1: sfp1 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&imux1_sfp1>; + los-gpios =3D <&pio 70 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&pio 69 GPIO_ACTIVE_LOW>; + tx-disable-gpios =3D <&pio 21 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt =3D <3000>; + }; + + /* SFP2 cage (WAN) */ + sfp2: sfp2 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&imux2_sfp2>; + los-gpios =3D <&pio 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&pio 1 GPIO_ACTIVE_LOW>; + tx-disable-gpios =3D <&pio 0 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt =3D <3000>; + }; +}; + +&cci { + proc-supply =3D <&rt5190_buck3>; +}; + +&cpu0 { + proc-supply =3D <&rt5190_buck3>; +}; + +&cpu1 { + proc-supply =3D <&rt5190_buck3>; +}; + +&cpu2 { + proc-supply =3D <&rt5190_buck3>; +}; + +&cpu3 { + proc-supply =3D <&rt5190_buck3>; +}; + +&cpu_thermal { + trips { + cpu_trip_hot: hot { + temperature =3D <120000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_trip_active_high: active-high { + temperature =3D <115000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + cpu_trip_active_med: active-med { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + cpu_trip_active_low: active-low { + temperature =3D <40000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map-cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device =3D <&fan 3 3>; + trip =3D <&cpu_trip_active_high>; + }; + + map-cpu-active-med { + /* active: set fan to cooling level 1 */ + cooling-device =3D <&fan 2 2>; + trip =3D <&cpu_trip_active_med>; + }; + + map-cpu-active-low { + /* active: set fan to cooling level 0 */ + cooling-device =3D <&fan 1 1>; + trip =3D <&cpu_trip_active_low>; + }; + }; +}; + +ð { + pinctrl-0 =3D <&mdio0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&fan { + pinctrl-0 =3D <&pwm0_pins>; + pinctrl-names =3D "default"; + pwms =3D <&pwm 0 50000>; + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; +}; + +&gsw_phy0 { + pinctrl-0 =3D <&gbe0_led0_pins>; + pinctrl-names =3D "gbe-led"; +}; + +&gsw_phy0_led0 { + color =3D ; + status =3D "okay"; +}; + +&gsw_port0 { + label =3D "mgmt"; +}; + +/* R4Pro has only port 0 connected, so disable the others */ +&gsw_phy1 { + status =3D "disabled"; +}; + +&gsw_port1 { + status =3D "disabled"; +}; + +&gsw_phy2 { + status =3D "disabled"; +}; + +&gsw_port2 { + status =3D "disabled"; +}; + +&gsw_phy3 { + status =3D "disabled"; +}; + +&gsw_port3 { + status =3D "disabled"; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + rt5190a_64: rt5190a@64 { + compatible =3D "richtek,rt5190a"; + reg =3D <0x64>; + vin2-supply =3D <&rt5190_buck1>; + vin3-supply =3D <&rt5190_buck1>; + vin4-supply =3D <&rt5190_buck1>; + + regulators { + rt5190_buck1: buck1 { + regulator-name =3D "rt5190a-buck1"; + regulator-min-microvolt =3D <5090000>; + regulator-max-microvolt =3D <5090000>; + regulator-allowed-modes =3D + ; + regulator-boot-on; + regulator-always-on; + }; + + buck2 { + regulator-name =3D "vcore"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + rt5190_buck3: buck3 { + regulator-name =3D "vproc"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4 { + regulator-name =3D "rt5190a-buck4"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-allowed-modes =3D + ; + regulator-boot-on; + regulator-always-on; + }; + + ldo { + regulator-name =3D "rt5190a-ldo"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2_1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pca9545: i2c-mux@70 { + compatible =3D "nxp,pca9545"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + imux0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pca9555: i2c-gpio-expander@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + rtc@51 { + compatible =3D "nxp,pcf8563"; + reg =3D <0x51>; + }; + + eeprom@57 { + compatible =3D "atmel,24c02"; + reg =3D <0x57>; + address-width =3D <8>; + pagesize =3D <8>; + size =3D <256>; + }; + }; + + imux1_sfp1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux2_sfp2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux3_wifi: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +/* mPCIe SIM2 (11300000) */ +&pcie0 { + status =3D "okay"; +}; + +/* mPCIe (11310000 near leds) SIM3 */ +&pcie1 { + status =3D "okay"; +}; + +/* M.2 (11280000) 1L0 key-m SSD1 CN13 / key-b SIM1 CN15 */ +&pcie2 { + status =3D "okay"; +}; + +/* M.2 (11290000) 1L1 key-m SSD2 CN14 / key-b SIM2 CN18 */ +&pcie3 { + status =3D "okay"; +}; + +&pio { + gbe0_led0_pins: gbe0-led0-pins { + mux { + function =3D "led"; + groups =3D "gbe0_led0"; + }; + }; + + i2c0_pins: i2c0-g0-pins { + mux { + function =3D "i2c"; + groups =3D "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-g0-pins { + mux { + function =3D "i2c"; + groups =3D "i2c1_0"; + }; + }; + + i2c2_1_pins: i2c2-g1-pins { + mux { + function =3D "i2c"; + groups =3D "i2c2_1"; + }; + }; + + mdio0_pins: mdio0-pins { + mux { + function =3D "eth"; + groups =3D "mdc_mdio0"; + }; + + conf { + pins =3D "SMI_0_MDC", "SMI_0_MDIO"; + drive-strength =3D <8>; + }; + }; + + mmc0_pins_emmc_51: mmc0-emmc-51-pins { + mux { + function =3D "flash"; + groups =3D "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-sdcard-pins { + mux { + function =3D "flash"; + groups =3D "sdcard"; + }; + }; + + /* 1L0 0=3Dkey-b (CN15), 1=3Dkey-m (CN13) */ + pcie-2-hog { + gpio-hog; + gpios =3D <79 GPIO_ACTIVE_HIGH>; + output-high; + }; + + /* 1L1 0=3Dkey-b (CN18), 1=3Dkey-m (CN14) */ + pcie-3-hog { + gpio-hog; + gpios =3D <63 GPIO_ACTIVE_HIGH>; + output-high; + }; + + pwm0_pins: pwm0-pins { + mux { + groups =3D "pwm0"; + function =3D "pwm"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function =3D "spi"; + groups =3D "spi0", "spi0_wp_hold"; + }; + }; +}; + +&pwm { + status =3D "okay"; +}; + +&serial0 { + status =3D "okay"; +}; + +&spi0 { + pinctrl-0 =3D <&spi0_flash_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + spi_nand: nand@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + spi-max-frequency =3D <52000000>; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + }; +}; + +&spi_nand { + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + reg =3D <0x0 0x200000>; + label =3D "bl2"; + }; + + partition@200000 { + compatible =3D "linux,ubi"; + reg =3D <0x200000 0xfe00000>; + label =3D "ubi"; + }; + }; +}; + +/* back USB */ +&ssusb0 { + /* Use U2P only instead of both U3P/U2P due to U3P serdes shared with pci= e2 */ + phys =3D <&xphyu2port0 PHY_TYPE_USB2>; + mediatek,u3p-dis-msk =3D <1>; + status =3D "okay"; +}; + +/* front USB */ +&ssusb1 { + status =3D "okay"; +}; + +&switch { + dsa,member =3D <1 0>; + status =3D "okay"; +}; + +&tphy { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; + +&xsphy { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index ed4b592c9dd5..5a7a9b2f954e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -418,7 +418,7 @@ lvts: lvts@1100a000 { nvmem-cell-names =3D "lvts-calib-data-1"; }; =20 - usb@11190000 { + ssusb0: usb@11190000 { compatible =3D "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg =3D <0 0x11190000 0 0x2e00>, <0 0x11193e00 0 0x0100>; --=20 2.43.0