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Wed, 5 Nov 2025 15:17:43 +0100 (CET) From: Matthias Schiffer To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH v2] arm64: dts: ti: k3-am642-tqma64xxl: add boot phase tags Date: Wed, 5 Nov 2025 15:17:26 +0100 Message-ID: <20251105141726.39579-1-matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.51.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: matthias.schiffer@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: matthias.schiffer@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay23-hz1.antispameurope.com with 4d1nTg6CRtz4NP6l X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: baa9b331185fd744344aa7d6361c3463 X-cloud-security: scantime:1.822 DKIM-Signature: a=rsa-sha256; bh=17in0dPu1cEXsBpoGpIQO8NBNGwqAQlLqZX3FuIiHHg=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1762352274; v=1; b=owc7GM0btC0VQAwPQjbbXgrDNkAasUNia+yB9RPQ+V0pCcEydBoy43V144iB7eQbXXGUjN4K noHHgxDmOVdvU9n9BjUJV1mUdFjtb4BUioeXCoDpDveL/iFNMsS+Rn/TUznfByY1Bb8soVcDPZ7 xPHfSmY8gIAbLa3fhbQwsLk/R9yiCU5XYXi648oe49Kmr7WqnDzcOxPUtqPybE2j/JmTgsgZi7Z dfU6HSjupEBS67iNNgL/jnGk+iDGxYVNzj4alw7yQoGnWg/Qcqi4bc7xQgOsieLrYNEHpkTJpAu tC4AV4jukYxuYfrfp9M1Q5aTO7inR0EOHezpfO7Da/sBA== Similar to other AM64x-based boards, add boot phase tags to make the Device Trees usable for firmware/bootloaders without modification. Supported boot devices are eMMC/SD card, SPI-NOR and USB (both mass storage and DFU). The I2C EEPROM is included to allow the firmware to select the correct RAM configuration for different TQMa64xxL variants. Signed-off-by: Matthias Schiffer --- v2: order boot phase tags after other standard properties .../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 15 +++++++++++++-- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/= arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 8f64d6272b1ba..7a69e729eae84 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -175,6 +175,7 @@ reg_sd: regulator-sd { regulator-max-microvolt =3D <3300000>; gpio =3D <&main_gpio1 43 GPIO_ACTIVE_HIGH>; enable-active-high; + bootph-all; }; }; =20 @@ -260,6 +261,7 @@ &main_gpio0 { "", "", "STATUS_OUT_3", "EN_DIG_OUT_4", /* 32-35 */ "", "", "STATUS_OUT_4", "DIG_IN_1", /* 36-39 */ "DIG_IN_2", "DIG_IN_3", "DIG_IN_4"; /* 40- */ + bootph-all; }; =20 &main_gpio1 { @@ -285,6 +287,7 @@ &main_gpio1 { "", "", "", "", /* 60-63 */ "", "", "", "ADC_INT#", /* 64-67 */ "BG95_PWRKEY", "BG95_RESET"; /* 68- */ + bootph-all; =20 line50-hog { /* See also usb0 */ @@ -334,6 +337,7 @@ &main_spi0 { &main_uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins>; + bootph-pre-ram; status =3D "okay"; }; =20 @@ -493,6 +497,11 @@ &mcu_uart1 { =20 &serdes_ln_ctrl { idle-states =3D ; + bootph-all; +}; + +&serdes_refclk { + bootph-all; }; =20 &serdes0 { @@ -500,6 +509,7 @@ serdes0_usb_link: phy@0 { reg =3D <0>; #phy-cells =3D <0>; resets =3D <&serdes_wiz0 1>; + bootph-all; cdns,num-lanes =3D <1>; cdns,phy-type =3D ; }; @@ -512,6 +522,7 @@ &sdhci1 { cd-gpios =3D <&main_gpio1 77 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; + bootph-all; ti,fails-without-test-cd; /* Enabled by overlay */ }; @@ -535,9 +546,11 @@ &usb0 { maximum-speed =3D "super-speed"; phys =3D <&serdes0_usb_link>; phy-names =3D "cdns3,usb3-phy"; + bootph-all; }; =20 &usbss0 { + bootph-all; ti,vbus-divider; }; =20 @@ -625,6 +638,7 @@ main_gpio0_hog_pins: main-gpio0-hog-pins { /* (P19) GPMC0_CSn2.GPIO0_43 - MMC1_CTRL */ AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7) >; + bootph-all; }; =20 main_gpio1_hog_pins: main-gpio1-hog-pins { @@ -748,6 +762,7 @@ AM64X_IOPAD(0x0298, PIN_INPUT, 7) /* (#N/A) MMC1_CLKLB */ AM64X_IOPAD(0x0290, PIN_INPUT, 0) >; + bootph-all; }; =20 main_mmc1_reg_pins: main-mmc1-reg-pins { @@ -755,6 +770,7 @@ main_mmc1_reg_pins: main-mmc1-reg-pins { /* (C13) SPI0_CS1.GPIO1_43 - MMC1_SD_EN */ AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) >; + bootph-all; }; =20 main_mmc1_wifi_pwrseq_pins: main-mmc1-wifi-pwrseq-pins { @@ -797,6 +813,7 @@ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (C16) UART0_TXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) >; + bootph-pre-ram; }; =20 main_uart1_pins: main-uart1-pins { @@ -865,6 +882,7 @@ main_usb0_pins: main-usb0-pins { /* (E19) USB0_DRVVBUS */ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) >; + bootph-all; }; =20 pru_icssg1_mdio_pins: pru-icssg1-mdio-pins { diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index ff3b2e0b8dd45..dde19d0784e31 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -17,7 +17,7 @@ memory@80000000 { device_type =3D "memory"; /* 1G RAM - default variant */ reg =3D <0x00000000 0x80000000 0x00000000 0x40000000>; - + bootph-pre-ram; }; =20 reserved_memory: reserved-memory { @@ -54,10 +54,15 @@ reg_1v8: regulator-1v8 { }; }; =20 +&fss { + bootph-all; +}; + &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins>; clock-frequency =3D <400000>; + bootph-pre-ram; status =3D "okay"; =20 tmp1075: temperature-sensor@4a { @@ -72,6 +77,7 @@ eeprom0: eeprom@50 { vcc-supply =3D <®_1v8>; pagesize =3D <16>; read-only; + bootph-pre-ram; }; =20 pcf85063: rtc@51 { @@ -89,9 +95,10 @@ eeprom1: eeprom@54 { }; =20 &ospi0 { - status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins>; + bootph-all; + status =3D "okay"; =20 flash@0 { compatible =3D "jedec,spi-nor"; @@ -99,6 +106,7 @@ flash@0 { spi-tx-bus-width =3D <8>; spi-rx-bus-width =3D <8>; spi-max-frequency =3D <84000000>; + bootph-all; cdns,tshsl-ns =3D <60>; cdns,tsd2d-ns =3D <60>; cdns,tchsh-ns =3D <60>; @@ -121,6 +129,7 @@ &sdhci0 { disable-wp; no-sdio; no-sd; + bootph-all; ti,driver-strength-ohm =3D <50>; }; =20 @@ -132,6 +141,7 @@ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) >; + bootph-pre-ram; }; =20 ospi0_pins: ospi0-pins { @@ -159,6 +169,7 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) >; + bootph-all; }; }; =20 --=20 TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ= any Amtsgericht M=C3=BCnchen, HRB 105018 Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch= neider https://www.tq-group.com/