From nobody Fri Dec 19 12:48:14 2025 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012025.outbound.protection.outlook.com [52.101.43.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE0313101AA; Wed, 5 Nov 2025 11:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.25 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342770; cv=fail; b=LSFbeESI7fOTOqghGjVhKywO2LCS9e+b4fsw6o3WjNA1YXM1rQdJrRAkKzCHLHbEDpi2nZw22aBe3oupUVav+BinAsfPV8LT9aDD9C4rt4PJhCgbcq4g+GsGuTMoLdCL+JzFbfcF4jaKGcc+nH/oFw9FI8/f/2MucjYpmYB1dCE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342770; c=relaxed/simple; bh=+Tsm2cqUkUWRAPpC3PltALPXg6d3xJulsQCFund548A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=F4Q5Y6/Gfj02OHOva9bBCnavhP/azBkjLI/bk2lo/gQd9NESd4xYFdVRS5M5tzkAdoPWNcxXJaZjCofmkJZwdzsYy3X84J6qQu3yNu9elGgcOg67yrJoFN20/CTsQYTonexnYfu9Vz9+t8y6fF4giVXhc6a/1YeGqtYCCeoPDnA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=eXoFdmDR; arc=fail smtp.client-ip=52.101.43.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="eXoFdmDR" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pZByYeh4Rcj4Q9AK1MK259xOaDsC4UUD90cbVGIVmn23cZ+hytKpvQuQ9wYsQp0PMyVNUu7TU+3DYEAOvJl6cKnQqIpWFtq3Q70SsYV1x+frjAC5tdLYtfPE1eTuU3gYyHucle9jsSSSoCtmBLzETOgxWdathKUzhrhYRMJsJ3nvEs+PbQ45TrEYM7WjVUutinGNB1pLFCEj20onvsQeMwaLsfUOmsyM2jyp0BwEACljXC7atYtv6UVLmL5+AHfUs2dRUMRAckY2vA8byBs+KXSBr6WxArS8SCjcGdV86lIWwiMiabxflAejg4aECjx9feMOTd7iYQToshVLHqEDfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AapsYuLtKjEA0dHyOwTWePsa3JKggILje8etQhzld70=; b=aSygnyKf1jLolx/dQrScuBp+vAN0pVS6hCRD/qMXpplmONDZjHXnFSuyGPmdK/LsEgwalPjfYBZeV7UVfafsN6His5pUHW/VrGAsXPwCfXror5rG9yyKXOq7Zt+zGPeZNJ0IJUKUcFzfhi3aZOoTxLSSW2Un0h6zxSWuX4fWccwYKt2vAGGfx/h5FDBjeXlR7Jgi0QIl2+g7EwUfzjD0RvelbBOAm1AX3n/P5rHAeLdvWUGpT9MS1ip7Y6To/5xYtTTa69ottt+RNSDrwCA6GSbtue7veFqcspiD2PURI9vy/99D9y/Vo90vJ7eABQP2y+3997ABDSTL4+TIWiZlDg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AapsYuLtKjEA0dHyOwTWePsa3JKggILje8etQhzld70=; b=eXoFdmDRBthSEn9Qcj1+LqGN6QLN7pdLURXxzyWS7XeZAhAa7ndc64Kee0SjknFlmkddjNnUfucFRAhDmWE90UqtIr1N13jeKG6W6evm70xb5BDGTjTmtN9c6suEN6SrnQUswI/tbib/sgXph38WLmXkXfJpOgpkcPX1ryp3o3IBotLNz1sXnhHmLL+tueUtDx2SqzEhY8kczQz2hD9Toud3SSqxhkbONMpsJJ4ErC0Y4eP+7s3Eo5aK87T1497fAWjO+ZsdFtFkmvZlrs9nkPprtf3JExQ+HI/nWgaxHKslxnQ52+rkpdb42g+4nTCxkt+oCdyqH8UD6qwVE0U8qQ== Received: from BL6PEPF00013E11.NAMP222.PROD.OUTLOOK.COM (2603:10b6:22e:400:0:1001:0:17) by LV2PR12MB5920.namprd12.prod.outlook.com (2603:10b6:408:172::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.8; Wed, 5 Nov 2025 11:39:24 +0000 Received: from BL6PEPF00020E63.namprd04.prod.outlook.com (2a01:111:f403:f901::5) by BL6PEPF00013E11.outlook.office365.com (2603:1036:903:4::4) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.9 via Frontend Transport; Wed, 5 Nov 2025 11:39:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF00020E63.mail.protection.outlook.com (10.167.249.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Wed, 5 Nov 2025 11:39:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:39:09 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:39:08 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 5 Nov 2025 03:39:01 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 1/8] cpufreq: CPPC: Add generic helpers for sysfs show/store Date: Wed, 5 Nov 2025 17:08:37 +0530 Message-ID: <20251105113844.4086250-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251105113844.4086250-1-sumitg@nvidia.com> References: <20251105113844.4086250-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E63:EE_|LV2PR12MB5920:EE_ X-MS-Office365-Filtering-Correlation-Id: 52ad3138-4de3-4461-e6c0-08de1c5ff841 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DY6OLlozP9Sn8esMkxvre83xYTSRPd3aeCrEC7VVH4eDOQTdugaYj69DdApO?= =?us-ascii?Q?U9g29vAKeImVPVt2EXlwhLtSj4SiBw4vd4p7nmsQ9PCczp/6ikj5qaMeb7P+?= =?us-ascii?Q?7c5rQi5aeQ0bS4H9kWjqpHES2ZeQDTlmpXn45uvGP3zLJI6J0bTtBq2JmmYf?= =?us-ascii?Q?r46jDYG1cq9Pawv8tRcQ0avSAnGzF5bkWI1ywh6LCrUTP2I3JWcY3x48ZJ1h?= =?us-ascii?Q?O1f4UJWMu/TjQQZXjgD0RPgFo87lQzqjXCjtl+kT+ZjRKwE0uKjFw4gBrqyg?= =?us-ascii?Q?E7VQ73fL2YtscOk127iMHNXn145WwZgdJx5ECaL2BMmMZ1FRYGShOe5DkOwO?= =?us-ascii?Q?87R1UZuAYU8dsnJfZomoJgJKJHlZ0LImDzAY7Tz8LZm5l45BXJap83NhHBz5?= =?us-ascii?Q?dygDfddpvs3hTPwPAGlrYrXMtGwHcybeEobeMHwcKG/OOLQZmHsnwVyWfS4j?= =?us-ascii?Q?fsmVbJaexGwqAAH0v+Qxq5ZuJAx4Y7O8NQiRwaTjdccteiSuYtYK6l93euqb?= =?us-ascii?Q?D69BIFL5NLbZxPdA7izMQz9zPDiI5DH3Lkx8jpZ6F1+KT/VgQ2J90xVm74mv?= =?us-ascii?Q?LeoaeRFw2KkHsnPgnYEj4v5LcFqkZw+IWwuhrCq1Fn6lathpW9zGmR255uw/?= =?us-ascii?Q?Qe56HVsJ5w/4DcF/uwmZl9HHzXncKPscWrsfTrcKR6Z8304q7YCs1LPj5rYv?= =?us-ascii?Q?89OLDwVLVx/qaVAnpux0KbB5GKnPSYB6UX25npX+C9Jc15TnZLY1Lj7+gxlw?= =?us-ascii?Q?Izk7wvP+/aAgHkO7u7Jdi9gzcpqUFg00OsoQIzeTH0XI8ab8X8DX3GZ7pzDz?= =?us-ascii?Q?23IgfcFYvwYqsJq9mQnfSZF8q0WxVyNJi1Q9SHjJARQJRDasHoNECVu/ld7D?= =?us-ascii?Q?U0ZyleDY69TjdjaJg7bTbwNAC4fcn75FtIOGEe2goDFv9Icm6EbDq0eJvMKV?= =?us-ascii?Q?Ms5Vfk3uftVe64EEIIsMZfVnSEzEnCbH4/nleYetgsoz4Ph59aAW+mC+JtGw?= =?us-ascii?Q?8LFc6cJesnXSas6pIPVxyOUAMNPxCd5u86ShbxQ38ZmTUW1ujpwj0DVux1x9?= =?us-ascii?Q?Kkwa6lXQNUQGig1W6EAlyd4PmcekXp45BXhWO4Nap2Gy+waW9Qm8Hajt6Nbp?= =?us-ascii?Q?5j7q4Wl4WeT9IWbVWXuajpYT4imsUNB07D/OzyIicds7UUS8pJjQ1vPLBiVA?= =?us-ascii?Q?rQ6zIoN1ZdNFulfmMpUhk8CIct10RcpOVIgW6OIOWe8G7iOWS0UUED3KKS/z?= =?us-ascii?Q?2M11uYCZ01qZfKJiw47Lhc6GE3sWcCnIaFZF1YWBfYwZOAPrH1Wi5sLMrGDD?= =?us-ascii?Q?24XN/8eFyz2vPf/u3SDUQQ1sA/nJm8E8BRhM7X/3BVpD6vr0JESUb4zig13U?= =?us-ascii?Q?GNsKrXLdqDsfHl+FxHW4yYIFwDeTFtbP2HCLdz1d04PjGxa1mWUo1R/5e1By?= =?us-ascii?Q?CYxd6cwmZg69JKb6WnRP8uQWsZEykqxPy9p1ZfsN/VSnuFqg+TtuJRaYO50Q?= =?us-ascii?Q?toWdk/+MTjAwkFD+7MBnKQ2LOpg5+DxAmrsOkHcMDcRGhHVDu8m5ibUpLI21?= =?us-ascii?Q?3RHrgLpDTqudKBTDOP26WT43uh3h5vx+F8IPbYTI?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 11:39:24.3777 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52ad3138-4de3-4461-e6c0-08de1c5ff841 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5920 Content-Type: text/plain; charset="utf-8" Add generic show/store helper functions for u64 sysfs attributes: - cppc_cpufreq_sysfs_show_u64() - cppc_cpufreq_sysfs_store_u64() Refactor auto_act_window and energy_performance_preference_val attributes to use these helpers, eliminating code duplication. No functional changes. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 57 ++++++++++++---------------------- 1 file changed, 19 insertions(+), 38 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index e23d9abea135..cf3ed6489a4f 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -832,72 +832,53 @@ static ssize_t store_auto_select(struct cpufreq_polic= y *policy, return count; } =20 -static ssize_t show_auto_act_window(struct cpufreq_policy *policy, char *b= uf) +static ssize_t cppc_cpufreq_sysfs_show_u64(unsigned int cpu, int (*get_fun= c)(int, u64 *), char *buf) { u64 val; - int ret; - - ret =3D cppc_get_auto_act_window(policy->cpu, &val); + int ret =3D get_func(cpu, &val); =20 - /* show "" when this register is not supported by cpc */ if (ret =3D=3D -EOPNOTSUPP) return sysfs_emit(buf, "\n"); - if (ret) return ret; =20 return sysfs_emit(buf, "%llu\n", val); } =20 -static ssize_t store_auto_act_window(struct cpufreq_policy *policy, - const char *buf, size_t count) +static ssize_t cppc_cpufreq_sysfs_store_u64(unsigned int cpu, int (*set_fu= nc)(int, u64), + const char *buf, size_t count) { - u64 usec; + u64 val; int ret; =20 - ret =3D kstrtou64(buf, 0, &usec); + ret =3D kstrtou64(buf, 0, &val); if (ret) return ret; =20 - ret =3D cppc_set_auto_act_window(policy->cpu, usec); - if (ret) - return ret; + ret =3D set_func((int)cpu, val); =20 - return count; + return ret ? ret : count; } =20 -static ssize_t show_energy_performance_preference_val(struct cpufreq_polic= y *policy, char *buf) +static ssize_t show_auto_act_window(struct cpufreq_policy *policy, char *b= uf) { - u64 val; - int ret; - - ret =3D cppc_get_epp_perf(policy->cpu, &val); - - /* show "" when this register is not supported by cpc */ - if (ret =3D=3D -EOPNOTSUPP) - return sysfs_emit(buf, "\n"); + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_auto_act_window,= buf); +} =20 - if (ret) - return ret; +static ssize_t store_auto_act_window(struct cpufreq_policy *policy, const = char *buf, size_t count) +{ + return cppc_cpufreq_sysfs_store_u64(policy->cpu, cppc_set_auto_act_window= , buf, count); +} =20 - return sysfs_emit(buf, "%llu\n", val); +static ssize_t show_energy_performance_preference_val(struct cpufreq_polic= y *policy, char *buf) +{ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_epp_perf, buf); } =20 static ssize_t store_energy_performance_preference_val(struct cpufreq_poli= cy *policy, const char *buf, size_t count) { - u64 val; - int ret; - - ret =3D kstrtou64(buf, 0, &val); - if (ret) - return ret; - - ret =3D cppc_set_epp(policy->cpu, val); - if (ret) - return ret; - - return count; + return cppc_cpufreq_sysfs_store_u64(policy->cpu, cppc_set_epp, buf, count= ); } =20 cpufreq_freq_attr_ro(freqdomain_cpus); --=20 2.34.1 From nobody Fri Dec 19 12:48:14 2025 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010064.outbound.protection.outlook.com [52.101.201.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BBE23101DC; Wed, 5 Nov 2025 11:39:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.201.64 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342789; cv=fail; b=LM/BSw5XzcW2nOdPioLoqMzIo1C/X6doqAKJdcxs8hOJsvMkWs2ZDSOnDqROo81fbmUBzChpp4f+qFKkxHI/Nb6NwATOpufobzvrCv4e5mCbMVd4/6GneMAlWEzhWROn9a9hIl554oQB3fSu406x431PK+EnM3BrskVWEWu6aAM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342789; c=relaxed/simple; bh=EOxpe2xiG/b60y30FFaOH+dp+7ldInpu5fnLSOSwnVI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o5179wlDgCUzaPBJBDMGXUlI6oD4tZh4KzLlFtZPDcB8YiK8ODQWLKWF6dhtkolyzDjI0jokBHq/BREU0vstajS5hWebnW+xtX6i1vmOtbD24BpRSnynXV4jITLQikMbSdn01rbyb+MDViprTeeYQiDV7Rdfu0eKvMJT5aGQafI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=c422Xdhe; arc=fail smtp.client-ip=52.101.201.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="c422Xdhe" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=YAfIu0cnz7B43Mdhb2chcFLJYANGDMKu8AhEMeOfFkSivmOISMKbxhaikYhxWrRL6WhqXwsNJM0NiocCZznFqu79L/8btljJwu9NhvBtjgnbxpegwoqIyAKCMTsbxNkrfValmOaoBd2JASHUOZohcUbPy+YB8zZPu2fYY+TTekIfFbpNQIKld7Rr45T03uQl+NbooRyV9kg7ZVuv7ooF6mB93lNXqMPGcwKHznh6Mp91kuUOIyI0kN9VjvxSnToIFf3tpW1BVgYPr1G9/5W5Xx/HHVuUigqdgIoPy/wgExxy0EvPsuMYOxZVO6qxze3WtrrRNf1gUAXTXQzyMkYfJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8cyDigDngr9ATGvhRUddVCSgqlh7AeX/G22+2WPU4Go=; b=w87JKZVQLF0zsA0a7deg4cAgtYpAPo9AkQExtffMdXpLabQgVDRQT6/AZDSSwq+FIIfjkHDFaq3QUnpv+W3MwlRCBr4MZ56nsTf2pPjac1mhVGpDAqHE4l57iLQs/yV1BQe8t2wFNQaZikRlK8W//WCpSp1YY0BPQIC7WPzXn8B2NlIeoeyYOzjGFySbGtGipmUaxNa51tu1BzQBnDbipHMi+79c3ZRJedkQK0YKKf6ln+qmgFy2mBEDnfnMv9mudpx1cP0z9pOpxiQDJFU2JWeX//QVnK0IqoH1q5yZ6YBWMKJN4SMXQ4+/q82ea9qRRkhAmqjJb9YIbPXvpauEMg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8cyDigDngr9ATGvhRUddVCSgqlh7AeX/G22+2WPU4Go=; b=c422Xdhes/FxaE2nKAowS/MQgsz4I8ghj69leaZrzGLe+ejQnFSknac14teeXlEb1DYcjwvJRtR2n1US6IWMwnyqvxlg4cpr/7Jo3moJiAnzba+jf2+IWVKZBc2Mbo6wW5UqkAitL7WX+7LyITetk1RlX90UNegRxQNHiGt+HbCcbxZRkonmZ+2ptnCFZr3N+alOD3E3yLh/gEkrGxJcA+dwpUa1KRaat0ReL07QOfOMqJ3OjwppgUZTm/rxX/eXubWEwN72AdQYBWUC8Bsf3RkUxfIHYyJ7rXQMRwo1KYivgM0Sz9AEuA+8VNOj+yr/1cMvb07zY8j5raENnv/e9Q== Received: from BLAPR03CA0119.namprd03.prod.outlook.com (2603:10b6:208:32a::34) by DS7PR12MB8346.namprd12.prod.outlook.com (2603:10b6:8:e5::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9275.16; Wed, 5 Nov 2025 11:39:43 +0000 Received: from BL6PEPF00020E64.namprd04.prod.outlook.com (2603:10b6:208:32a:cafe::b0) by BLAPR03CA0119.outlook.office365.com (2603:10b6:208:32a::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.8 via Frontend Transport; Wed, 5 Nov 2025 11:39:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF00020E64.mail.protection.outlook.com (10.167.249.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Wed, 5 Nov 2025 11:39:43 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:39:29 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:39:29 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 5 Nov 2025 03:39:22 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 2/8] ACPI: CPPC: Add cppc_get_perf() API to read performance controls Date: Wed, 5 Nov 2025 17:08:38 +0530 Message-ID: <20251105113844.4086250-3-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251105113844.4086250-1-sumitg@nvidia.com> References: <20251105113844.4086250-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E64:EE_|DS7PR12MB8346:EE_ X-MS-Office365-Filtering-Correlation-Id: c96fdb0a-0604-41e7-64e3-08de1c600374 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uVhsJ3KgyyS/oTKwCyncKn3c3YlMZ3bf0QAH6S7FwRCWafuX5GYAT2QgMevm?= =?us-ascii?Q?nywOrcA1cY4+cyfe/TnUvONWjyYMt4CiP1WElFBCutB30LH+IAmJ1R1RYE3X?= =?us-ascii?Q?nRPlpN3E+EjdOze6Zfw2qTPGhlBtty5zj3QkCUOZY3WHGNa3t+YmL+GQlarU?= =?us-ascii?Q?/PZ8+4d3UTzFy+ONVumqxDDJbjmE8/rJ7p+/zWkVVPhuRdxlsmb4KpP7WCQh?= =?us-ascii?Q?YKQuZisoGDvYLtk30AN5tbf4UlNzyk2y8ZDJE2QAFohA/lK1QNROQRFG/Lz8?= =?us-ascii?Q?N7vex4BGKQOs6R683e/e1sXaE2sLOjw57uuZUW1yw+0+wr3HvrnHKMqBKoQu?= =?us-ascii?Q?Jzp+Pp/WuzKPsOw2+qPVlVL/eEFafLeQWKb8NditX8qJuEP56U59sO6n1C/P?= =?us-ascii?Q?xPdygfjYD6EeHtV24BR6Ce+5JEdH7lTKkmVnlglgeXAecHcBryiZMKLo16p8?= =?us-ascii?Q?Q24Te/s2gCLYQejpnYQtZVFy6vOqTkRmfBNPoDRPq7vHiapnGuebss8c7Cuk?= =?us-ascii?Q?jbR2a7aXzysBAW7y8i+At0YqnJ2/KUQsGSJZADdAFQRnfuF5djWIWU44KDWg?= =?us-ascii?Q?tJRYlu8xD7XMJpzWwBO2imI+VM/j5hqxzNEvi6pBwPrE8XwJF7tY3lh8I3TS?= =?us-ascii?Q?OnXxjSIPQBep0ce02qwy8mvfrC6DBQRfeNXjBJm4TiwYzwpDhhP0aLdUjXZh?= =?us-ascii?Q?R01c2GVjblm/aMc3q3K8Jw1o8jKtyyrQVyD0hfBVsFSlhmPD7AUYbPj7jTmE?= =?us-ascii?Q?PonM/1DGcWpsAzr3jX5eiPRlXPRgcr4nkH2b8MZ2KppUe7ih9kLDitkEihQG?= =?us-ascii?Q?L4psESuMFt50pdNOgY5AVFkAGpuxEqryRIf5xvZLM7pf3SCrHltIGWfWiQLG?= =?us-ascii?Q?F8zUjG4gJeHFRTLhwtCCwNFlW7KLDi0o5Dq7ZGyjtUv+C9M3WODoeDcQ/N3h?= =?us-ascii?Q?62sQUr21UEKtjRWCxELxg61QAzuiGiFocGeP/8paaB4Ijz6TVl4OI/WxFfJ6?= =?us-ascii?Q?FL2I6qnOQF0fcC75NDg1DFpkpQi94SPscsuOEgx8PImEL3q25dMftiKcWI77?= =?us-ascii?Q?7+MRgmbAzIfJufBSNwEBl7H1lGjKTcxOytSgXnaYXQDjAnf0ODdwOh5es2l1?= =?us-ascii?Q?lPtZ+3iDENuTLhT3SR61TYedVcQBlFkRDHi9t5PIllMmh1pA7FxO4HZICYfe?= =?us-ascii?Q?L2ch2wYMd6P6XxMX6u5YT0C1I6ukA/DHVBPtGO+EIa4JX6ux49/kQTMw+rh+?= =?us-ascii?Q?TxoO8kp9RiNDRSIiR4yGIPYGg7vRL96nZHYrusoEKyOqhCecuvOzLLLTHBuV?= =?us-ascii?Q?OvmfPbY24hoZ9q3U3YX9vPgYkZx5ZYUaQ2sVumiZRbA4n2sIQSo9wX/QIGYC?= =?us-ascii?Q?eqEo7sAHf9p885BNEVni3EPsIXMhxyT8bcmneFePjZHz31tN23b33aAY0Xtb?= =?us-ascii?Q?h1xLscJJT476yD1qculi9pM1Y/1Rf5qIv0lB/fgeGv465NMK9LBIBk3yDeIH?= =?us-ascii?Q?pomLnAM1fhZK1LYc46uule9islERkFBdITSE9jPhWfpT34/GxSA09lK30Q8L?= =?us-ascii?Q?UJweA2f0koMppLkID3YPfTSXpVb5L6pB37GnfRQo?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 11:39:43.1640 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c96fdb0a-0604-41e7-64e3-08de1c600374 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8346 Content-Type: text/plain; charset="utf-8" Add cppc_get_perf() function to read values of performance control registers including desired_perf, min_perf, max_perf, and energy_perf. This provides a read interface to complement the existing cppc_set_perf() write interface for performance control registers. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 73 ++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 5 +++ 2 files changed, 78 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index ab4651205e8a..05672c30187c 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1731,6 +1731,79 @@ int cppc_set_enable(int cpu, bool enable) return cppc_set_reg_val(cpu, ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_enable); +/** + * cppc_get_perf - Get a CPU's performance controls. + * @cpu: CPU for which to get performance controls. + * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * + * Return: 0 for success with perf_ctrls, -ERRNO otherwise. + */ +int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_perf_reg, *min_perf_reg, *max_perf_= reg, + *energy_perf_reg; + u64 desired_perf =3D 0, min =3D 0, max =3D 0, energy_perf =3D 0; + int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); + struct cppc_pcc_data *pcc_ss_data =3D NULL; + int ret =3D 0, regs_in_pcc =3D 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + if (!perf_ctrls) { + pr_debug("Invalid perf_ctrls pointer\n"); + return -EINVAL; + } + + desired_perf_reg =3D &cpc_desc->cpc_regs[DESIRED_PERF]; + min_perf_reg =3D &cpc_desc->cpc_regs[MIN_PERF]; + max_perf_reg =3D &cpc_desc->cpc_regs[MAX_PERF]; + energy_perf_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; + + /* Are any of the regs PCC ?*/ + if (CPC_IN_PCC(desired_perf_reg) || CPC_IN_PCC(min_perf_reg) || + CPC_IN_PCC(max_perf_reg) || CPC_IN_PCC(energy_perf_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); + return -ENODEV; + } + pcc_ss_data =3D pcc_data[pcc_ss_id]; + regs_in_pcc =3D 1; + down_write(&pcc_ss_data->pcc_lock); + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + pr_debug("Failed to send PCC command for CPU:%d, ret:%d\n", cpu, ret); + ret =3D -EIO; + goto out_err; + } + } + + /* Read optional elements if present */ + if (CPC_SUPPORTED(max_perf_reg)) + cpc_read(cpu, max_perf_reg, &max); + perf_ctrls->max_perf =3D max; + + if (CPC_SUPPORTED(min_perf_reg)) + cpc_read(cpu, min_perf_reg, &min); + perf_ctrls->min_perf =3D min; + + if (CPC_SUPPORTED(desired_perf_reg)) + cpc_read(cpu, desired_perf_reg, &desired_perf); + perf_ctrls->desired_perf =3D desired_perf; + + if (CPC_SUPPORTED(energy_perf_reg)) + cpc_read(cpu, energy_perf_reg, &energy_perf); + perf_ctrls->energy_perf =3D energy_perf; + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf); =20 /** * cppc_set_perf - Set a CPU's performance controls. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 13fa81504844..7190afeead8b 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -151,6 +151,7 @@ extern int cppc_get_desired_perf(int cpunum, u64 *desir= ed_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_c= trs); +extern int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); @@ -192,6 +193,10 @@ static inline int cppc_get_perf_ctrs(int cpu, struct c= ppc_perf_fb_ctrs *perf_fb_ { return -EOPNOTSUPP; } +static inline int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrl= s) +{ + return -EOPNOTSUPP; +} static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrl= s) { return -EOPNOTSUPP; --=20 2.34.1 From nobody Fri Dec 19 12:48:14 2025 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011059.outbound.protection.outlook.com [52.101.52.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B0E1309F18; Wed, 5 Nov 2025 11:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.52.59 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342812; cv=fail; b=jz9/ro+vDwRghYk9PO1JEtFAO27Iwc4rtQPCJj5EEt/wCbGZj7G+x17vHXqlbZ6IbDr+4cfh+iAzk4ZIbgjlqyBxKVQXNBd0gwuVOwilkj26z/TTei+zUh+SfF7OLV5xmhLRJ1AAXOtlbOpbBerZBOB8Bl4qdgcW/McSlSodF5o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342812; c=relaxed/simple; bh=AkZ3zQWcxeErcvFTSL9kTptHaJX3jntu9cjnPnRPPRo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Z76ZLQD64XyMEg32hJvGbBUlUq38W92ZHNaPaWqxsFSyJ/XMj6OM0vYX/BLidCHT5gF44/Ap/CwOtK0niXnEiBbFKt/MOv+eYsJ4Mbjy/5L/pQvn6zdMuSh4ZiFjAlp9jMuVIM1fqk3B30JjVMVeGDNANkZ31iOxOJ/yk6czvqE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=axATF5NT; arc=fail smtp.client-ip=52.101.52.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="axATF5NT" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KfjqNcp8V5/0CNfIdVkvDEUtCEZjl/DEw6jLbGiJQ4U8eefjoUTCWm0ADpdYSiARkqcFH35jHjmWyg7U4f/QWeae4x3l+8nCkuNft2ksALoZzou7Q54Z4wja4LaA9g0ZuIFzRPSFcY9bGWJteADxviqHHhrnmbJOrMEbr07jQrZBM+d+zS+bWwkhYLlz0i0YLzAoihJnSlLDhDnJhS45uh/F3emGrsXJ9XMJAbHkVxwAB6d9wmrAsGCLikSpu1COz92mfqaVdCHoNyGzizp3UJuCmwmOzKWafleU9TtDp2V3UmeLalsmkX1FsOr2swPgj4CV3PaG3GpktCoItZNN/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZAiKQi/JDAH3gjjqogrfEkz54DkC7Ljbdkil5oJr/lo=; b=fMtFhXJ5p0svF4xqlK/QsTN4vU08sRiSgsu1yjveg50+Fo0U3bLPewaGjdakyJmK+FyZjeoMNTJhlCqbLQxI2P5MXLh9iI0TIM5emTpUrPtxgSO6a3zLyejen4lQ57z4YrzDDg8LBe1DmFlVhQ37HKDBEr2Kng6FGsb6psIFfZGC+SFfpMyETO/VdnuTwj9BE8IPZBosZWxOP7RWVbdpd7dwcz2jWtrAcV3jtQOv5fYHBDA6Dn+/P0CZ4Vrd15AKv39v+RjCxKMmqR6hIrm/0nzsMpy43CduP/rldtB+9ieD9RFvcaigyS3l65t9VvJ4AxqTxKRx+LWgScC0xN5BcA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZAiKQi/JDAH3gjjqogrfEkz54DkC7Ljbdkil5oJr/lo=; b=axATF5NTsFan66QjO2rg1V1oVYt2yAe5FY5g/+kfYK56vdAKvaFgFzrIr2SXQwWBk7ovarPi9w/SpYeopZaSAf6ebPXWO8f+B0miXB+Ma0ykHwY3FZvUIqlNNVtJZKCuFNf39znP/QaPb9sWX0ls/eGSxZrptWDK2jDGWZCkAh3+/QMFq/a6FdFdgaGdhGrY2tKRzq/i79iCYHGKBxUwJTxTN+W+jQ3U8nSZ8X7z/9o0eI33gypMpkLAaQ4jK7IlBkjinqcpNKs88Gq5JjXm83zS68RDEzD17ouGzQ2D88fU4zi7GEXesRkGSRJ76K46e39DBWd2KJGpdoERYkeLAw== Received: from BLAPR03CA0008.namprd03.prod.outlook.com (2603:10b6:208:32b::13) by DS0PR12MB7536.namprd12.prod.outlook.com (2603:10b6:8:11c::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9275.16; Wed, 5 Nov 2025 11:40:05 +0000 Received: from BL6PEPF00020E62.namprd04.prod.outlook.com (2603:10b6:208:32b:cafe::b0) by BLAPR03CA0008.outlook.office365.com (2603:10b6:208:32b::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9275.16 via Frontend Transport; Wed, 5 Nov 2025 11:40:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF00020E62.mail.protection.outlook.com (10.167.249.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Wed, 5 Nov 2025 11:40:05 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:39:51 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:39:50 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 5 Nov 2025 03:39:43 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 3/8] ACPI: CPPC: extend APIs to support auto_sel and epp Date: Wed, 5 Nov 2025 17:08:39 +0530 Message-ID: <20251105113844.4086250-4-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251105113844.4086250-1-sumitg@nvidia.com> References: <20251105113844.4086250-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E62:EE_|DS0PR12MB7536:EE_ X-MS-Office365-Filtering-Correlation-Id: 1473ad46-4590-4ca0-fa42-08de1c60108a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|1800799024|376014|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DDQNiUKKUzdWycUnTapiRspdawnnLmHWJ3wQPnN9Bz7i3sxFMXUGJz7VeN5D?= =?us-ascii?Q?dHeXkXlw+V6/tXmY3yRkLWLTiptYSt0MxBlnO/nBm5s/eJba39aF0MHIxgSO?= =?us-ascii?Q?RkeE+PVCUX6ztYw0OPIAKVJ7pXXA/M5wCL+kjFzYbl880L5q6ooVR5AWUIfH?= =?us-ascii?Q?OufMep1ekYdzUIa/jnYlpmNKr/Gy/DGRuUqsSWoYzxan168PvxZ0by0GgaN4?= =?us-ascii?Q?+VeB3HK27VkWdEQDBoY2Dc5qaiqcQw79gyvdy+Ktuu8wbEqu4WlnRz9GrrPw?= =?us-ascii?Q?j+Opb7DvFPsCEyDPr9D7TD0QTeEJlXEhtcWOR6KfsjIB/YsndT9Mw0qs7cE9?= =?us-ascii?Q?2bZ58xRc+suijjLxEpw8mwNfjFEFYJIotZiHLm7oxxzrYMC8qN/LURL5p5MI?= =?us-ascii?Q?oC7/+14oC0bEBaQP7cVBOEeqB+xaV0TZ4ZrtmsJF+Kz5zpxZvuiE8lKMrtfr?= =?us-ascii?Q?sl1lbLmpqxUthP636pEsji6qUWyLAj34D0Lq0fPCREcp1wq14KBVY+xEKqdS?= =?us-ascii?Q?BJfmUduM0Ecb1IeAzhbIO2AxlwfeoRVWWo8wIpntcE2UNlZl/6JOXCA/+Wbv?= =?us-ascii?Q?hLqJj/FfvErqYXti2d5vIafy/Z6Q/wpr0z0OagY/aB0Fh4ZF1ec9gQdqlxgB?= =?us-ascii?Q?ZIMB9QOtBAnumhJADrXzcq9H1DgdvF5bqA57EoiSb/KLrFoCGAv+T236vsMi?= =?us-ascii?Q?L8sv4XFQX8zhKI79YKdF4kbbzB4Rl6zsovN8R/8p8oxxR+bX+evjZxbyN0YY?= =?us-ascii?Q?PdhBeoN7Fteq76dxfvQA8iCYY7TZ1VR2FWJvJNVuMwM7Qw2SJ4I6Wk/fVAic?= =?us-ascii?Q?6Iyii3IcBjtqQ6Tfm9PsTwcoXJ1JzD5tp2QejiGIfTJId3L3nlzPVVFHXBaF?= =?us-ascii?Q?o1lHpeCHzJBWxe1NuYbz3JwF6i3i83r2RmX7aPY54WOp4WnfRi1A48yBVZAh?= =?us-ascii?Q?QXXttYwaixGq6GEoWMRXPnVWRmBDEL30b66GmpgewS4cIza5dIN6ERL7S8Lr?= =?us-ascii?Q?gZq0jMXtmMSjLGy2s/81qqeJkjq+LZ09Nz7gPWVu3ipXoYdGb4WLVooE4o9B?= =?us-ascii?Q?NOSVG4apqOweFX53nG9W9t9EoPvkQTkFaWjcq7v4xVjGfjmaKNzVo+br3x5S?= =?us-ascii?Q?heYmzqx6aYVDHs+aUV/durBKBl8Pw+S9F7Hs6B4NMT8/3EFvOCozyMA1DVg0?= =?us-ascii?Q?oRUQjXcBzACO3z2j2Xn2Vvs6IdvYPP2Y3jVkiTanyN3eQAJ6p6Sq+bL7rL5k?= =?us-ascii?Q?F46CqanhYB45LVh/XG5ypCyNv4aXr1s8qIwquFeFpN2lUgM0ZwX9oEoAykTp?= =?us-ascii?Q?4CScwCmERVnNKkYdxk/FewHRplT98lrERcuA/KSwO9YqBJaFktXL5ExDjXT1?= =?us-ascii?Q?tAsOb99Vw+tjPwHX04AEln4yGgGj5PIsdvNyolOfy9xCgXuDljV0649b9Pju?= =?us-ascii?Q?Eg1m9Op4eR5ihWbImKUTEDzYIwIqNUmdIn6aGNjQqyXl72XhM3Hwr/BK/Hlt?= =?us-ascii?Q?uKbh0DHiqUjjJpL8S/PGDJ6nZ30wed8Vr9cp4YQjGLnFrKsoLFjTOgLH/A05?= =?us-ascii?Q?RLSyk1ipTcxAfmOilomJSXczfAKcmM2GvalI5+2A?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(1800799024)(376014)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 11:40:05.1281 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1473ad46-4590-4ca0-fa42-08de1c60108a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E62.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7536 Content-Type: text/plain; charset="utf-8" - Add auto_sel read support in cppc_get_perf_caps(). - Add write of both auto_sel and energy_perf in cppc_set_epp_perf(). - Remove redundant energy_perf field from 'struct cppc_perf_caps' as the same is available in 'struct cppc_perf_ctrls' which is used. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 42 ++++++++++++++++++++++++++++++++-------- include/acpi/cppc_acpi.h | 1 - 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 05672c30187c..757e8ce87e9b 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1344,8 +1344,8 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_c= aps *perf_caps) struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *highest_reg, *lowest_reg, *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, - *low_freq_reg =3D NULL, *nom_freq_reg =3D NULL; - u64 high, low, guaranteed, nom, min_nonlinear, low_f =3D 0, nom_f =3D 0; + *low_freq_reg =3D NULL, *nom_freq_reg =3D NULL, *auto_sel_reg =3D NULL; + u64 high, low, guaranteed, nom, min_nonlinear, low_f =3D 0, nom_f =3D 0, = auto_sel =3D 0; int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum); struct cppc_pcc_data *pcc_ss_data =3D NULL; int ret =3D 0, regs_in_pcc =3D 0; @@ -1362,11 +1362,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf= _caps *perf_caps) low_freq_reg =3D &cpc_desc->cpc_regs[LOWEST_FREQ]; nom_freq_reg =3D &cpc_desc->cpc_regs[NOMINAL_FREQ]; guaranteed_reg =3D &cpc_desc->cpc_regs[GUARANTEED_PERF]; + auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; =20 /* Are any of the regs PCC ?*/ if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || - CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { + CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg) || CPC_IN_PCC(auto_= sel_reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -1414,6 +1415,9 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_c= aps *perf_caps) perf_caps->lowest_freq =3D low_f; perf_caps->nominal_freq =3D nom_f; =20 + if (CPC_SUPPORTED(auto_sel_reg)) + cpc_read(cpunum, auto_sel_reg, &auto_sel); + perf_caps->auto_sel =3D (bool)auto_sel; =20 out_err: if (regs_in_pcc) @@ -1555,6 +1559,8 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls= *perf_ctrls, bool enable) struct cpc_register_resource *auto_sel_reg; struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); struct cppc_pcc_data *pcc_ss_data =3D NULL; + bool autosel_support_in_ffh_or_sysmem; + bool epp_support_in_ffh_or_sysmem; int ret; =20 if (!cpc_desc) { @@ -1565,6 +1571,11 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrl= s *perf_ctrls, bool enable) auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; epp_set_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; =20 + epp_support_in_ffh_or_sysmem =3D CPC_SUPPORTED(epp_set_reg) && + (CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg)); + autosel_support_in_ffh_or_sysmem =3D CPC_SUPPORTED(auto_sel_reg) && + (CPC_IN_FFH(auto_sel_reg) || CPC_IN_SYSTEM_MEMORY(auto_sel_reg)); + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); @@ -1589,14 +1600,29 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctr= ls *perf_ctrls, bool enable) /* after writing CPC, transfer the ownership of PCC to platform */ ret =3D send_pcc_cmd(pcc_ss_id, CMD_WRITE); up_write(&pcc_ss_data->pcc_lock); - } else if (osc_cpc_flexible_adr_space_confirmed && - CPC_SUPPORTED(epp_set_reg) && CPC_IN_FFH(epp_set_reg)) { - ret =3D cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + } else if (osc_cpc_flexible_adr_space_confirmed) { + if (!epp_support_in_ffh_or_sysmem && !autosel_support_in_ffh_or_sysmem) { + ret =3D -EOPNOTSUPP; + } else { + if (autosel_support_in_ffh_or_sysmem) { + ret =3D cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + } + + if (epp_support_in_ffh_or_sysmem) { + ret =3D cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) + return ret; + } + } } else { - ret =3D -ENOTSUPP; - pr_debug("_CPC in PCC and _CPC in FFH are not supported\n"); + ret =3D -EOPNOTSUPP; } =20 + if (ret =3D=3D -EOPNOTSUPP) + pr_debug("_CPC in PCC and _CPC in FFH are not supported\n"); + return ret; } EXPORT_SYMBOL_GPL(cppc_set_epp_perf); diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 7190afeead8b..42e37a84cac9 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -119,7 +119,6 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; - u32 energy_perf; bool auto_sel; }; =20 --=20 2.34.1 From nobody Fri Dec 19 12:48:14 2025 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010015.outbound.protection.outlook.com [52.101.61.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6DE1310636; Wed, 5 Nov 2025 11:40:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342823; cv=fail; b=d9UGmra6PH6qTu82qdu4f8H31DmXgCsdm2Cg5Wd75gmBti0x4g9GAWuHH24LYj04kpJECp492XB8qoUTrQDVMszRI5UXC+8Y0Ave58Iy2z03aItMjeoNWewEBIst6XUesLY4Sja7vmJ92b3Dlh/v+3Na8G+r84F4vuqDbYOXmj8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342823; c=relaxed/simple; bh=1EHj5RfaQGuovMr7sQv7FVBm6BISdm+nE3hw+5NiiHo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lEuIvXobYxQDXNJBQG4SajoIosWRpT1Hre9a22utT7F9i7wAqb/wA0q8ygfS5QdX+fV46lX91D/7ZNAUmf19/fyNPChS5J5LZpaLG0yqAJWwiCudrcuFAVQHxTsl3m++1Z1NSuzKGFq9BMtXJf/R/uvPJhx4MRAgpRQjHAsSHR0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ChAPrVGZ; arc=fail smtp.client-ip=52.101.61.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ChAPrVGZ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=TEoVOMs8X2LpdA5ywII4LDX9NlFvFNr6HacvN3QW6WyoNqu9mub907DQJ6gv+7uNK0X1UKKMGId2cfF8G8OusAms9ZtuZrATBzTfwVmaYD3ij3cTF3U4v+LniYt7CJWOLgDSoPEp9+6F6UrjzO0jPZ9ymFxRFqVMeUO+u4CjU20ElM1NGkVvHSvK7friAhOLiWRRnBY4zvDJ2b6hoqG8OG3nCiwyhw0+m/EeF1jvJSNGANCNfGFmaUvZWXMpJBx+QopgttVjKks/aqfLqdDCXQ8YEdDeEHhNcyTbnRpfpXgJinmwyFyEUh+dd5Am4vlDpiRiiLLoqG5ksdcDHHODvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4KZoG7TnH77p92chjegSQtpyzMKo/cz+4u5Z/ZIzY2s=; b=pyEI5v4akgBbKle07Mky7Keu3ynynlL9o7rizJiAzKW3U6ct6ZLwhQ3g3qU2MuvJDYTwaK+eoBVfEpfm5I52aMcHxA97SY3mCpbxlUA1B9oaWKnF7e72l+FcKXbuKsCXi7B0SGgoTTsiGrhUozWiIc9oHLwte+slfE21FBAKc/c8FIUjP6xd0usajoU/2iDMcahUbppxsDymTxNNOf9nWUgpLjalNcdq+jOdo4ohdMyethqzwN1BxblvyxWryQ6vznCMhfa3TZmJPOT/UomVpez5iSX14KtPbXSKqJ01YpB4b0S7HwG2ghI2UPKCY10GhquGBH185EGYeek8JtyWSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4KZoG7TnH77p92chjegSQtpyzMKo/cz+4u5Z/ZIzY2s=; b=ChAPrVGZ5Hf04RAGGTPhqerSX9NJptbkTDqNUOY5UtVlULq+jeEXd7pt6PYqKtGBBvaxm2AenrazBhPr/Vyyal1SZvLr494mjwC9CgtIgyhte8f0V/blLzM/8nH4t3cOEEVgILCcQEAk6OHrPgMe6r6KCwuc4q6SjVVy/TafSpnqLaHHFQMngDoP1fT65327edL9BT4jtIFcgcnMa9vmw5C7jef4rvfksvbZImi18EheiBxepKwt+MrYb8LiaUOyZH9BK+lqZ5Yb5yZxX0dqQFFUzo4Viq/OYS9DUFRSt5Q7vZIcmomll480pWU4m34VQbBgCpsILD6uy1o2PTvJFA== Received: from BLAPR03CA0117.namprd03.prod.outlook.com (2603:10b6:208:32a::32) by SJ0PR12MB6685.namprd12.prod.outlook.com (2603:10b6:a03:478::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9275.15; Wed, 5 Nov 2025 11:40:15 +0000 Received: from BL6PEPF00020E64.namprd04.prod.outlook.com (2603:10b6:208:32a:cafe::91) by BLAPR03CA0117.outlook.office365.com (2603:10b6:208:32a::32) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9275.16 via Frontend Transport; Wed, 5 Nov 2025 11:40:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF00020E64.mail.protection.outlook.com (10.167.249.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Wed, 5 Nov 2025 11:40:13 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:00 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:00 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 5 Nov 2025 03:39:53 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 4/8] ACPI: CPPC: add APIs and sysfs interface for min/max_perf Date: Wed, 5 Nov 2025 17:08:40 +0530 Message-ID: <20251105113844.4086250-5-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251105113844.4086250-1-sumitg@nvidia.com> References: <20251105113844.4086250-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E64:EE_|SJ0PR12MB6685:EE_ X-MS-Office365-Filtering-Correlation-Id: 9eae6988-9714-4f2c-161a-08de1c6015d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6WGnCOYU6/lNJJVdb+F/RsuBWxciNgOkI+mFsd77EIUFwZOLeSBe9yW68XbZ?= =?us-ascii?Q?KWGDQpzlc+JBQRvRpYqWFWY46KqAJkW69v/JfhV7QrCXJhP6aDQKQCdIDi75?= =?us-ascii?Q?vz+nOIXIeGham+KdeP2tFhIAUmKSA7/vcL5+VgCrbMMqDq0h5V0Yqbqv1TDi?= =?us-ascii?Q?Pd8C+cnPrMoUzKpPHJz6ZymhW0yLKWtEGeO4MRhIzDMnpU1jY+KFc8hKwXDl?= =?us-ascii?Q?NCNzSvrdfSI635IRurKQ3hHfIWsegWeb8CJdT+GFyKp/3scAkXNPRrdw+RqK?= =?us-ascii?Q?lZVuf+HBpp+zZYsOo95YKkdJK2BSXzldBZnhsBNAF36EInAwZVYrZbr6yy3c?= =?us-ascii?Q?JWqPwUS7tdjaT32lcLjxw07c3xJyhkU9PFrL2gAHregMz4J4Vt3r9Ak4fVNw?= =?us-ascii?Q?zWKD5DCWErPq94Wwz9CNaxFIwdB+jgfbuaPQbDRu56FBU3eWamnrF5Mjr6gX?= =?us-ascii?Q?Lk8tLf8K6F6ZyEQAptx1m5DJkPvEPTqL/ZoaDvPfoGqNQShyPMSzpxm7vZV/?= =?us-ascii?Q?v8Rk61Qu3HhLXfkEMaMgdb2p8pgMQ2fAKd/9lcTaifwth0h4pYqfvXpndnoA?= =?us-ascii?Q?h6lEp/3BJ5DnvaE+QpKgq0TzsPhqdWKDKSJLFIuSF3Z0+QP6LeEJBd7p+A7B?= =?us-ascii?Q?KoXKFkz7P34qigTP6vzfDSaOiKbuay26qRnH1IS0TSUnxFHVikaGDRQfHhOL?= =?us-ascii?Q?S+54JzeX3W8Du2Dngjr+Kg2Znasj6Eiw9ILZ59ENqylryCdfit/8YuduMcEH?= =?us-ascii?Q?1jj3xzCjbRaOgLVNI17RMieCbp3HqI8SLN3P7zhkHbPbdmj129PDc/7oCqwe?= =?us-ascii?Q?/B4wLoo9r561dl2Rr7vZw+eOibbcG8qpw1mJ5RmPuSMbUM4vlajviOK+M8Gu?= =?us-ascii?Q?qbpAT/QLv+xO+fJDIab56P5D25TaDRHVgR/vOXM7jNshYBRFhQhp3oymKxfZ?= =?us-ascii?Q?jpS22noNq1MOndGG5DWk6PMz94XO5Rodvc2q9RXlBEpHja+LQtIARJ2Qjya0?= =?us-ascii?Q?I9R0aZ9PcU5qXqmDx2H0uO9vSVdCsNeK4sd4B5WFhQwSmrabFEPJW105NQzD?= =?us-ascii?Q?DhY2GurEsBN6ehUkvqham7Mv0qmHqgYT43yprSiV6BP8gjbgMVG69PJLNgbw?= =?us-ascii?Q?HrcUZJUZ2wk4btWlW+jit/kzVSSdTq9/S00MvaJ5GZKKMy1/dZTxR39pzlRh?= =?us-ascii?Q?4YW/5yN62tvYRv5OV3/1Um7MKJuV0z99TeLuYhEJgB8LpkbMmmWUSb3N0jjE?= =?us-ascii?Q?h+CGTj4AEQq+GAsbA0rNaKTfj0QspUTFwyJTyLmcqnVjGg6XXHCL0ARlRYcn?= =?us-ascii?Q?ZNSpn/CnaaZUWx8di21xxhUHxNYxkPUUxWgIs9rTlP0pL27a89QXNdLt/Jwd?= =?us-ascii?Q?37QG/buYugXs4b8SFWODk8DTTUunC3exkTY+CxZcj5mtsL9iWthDoP1sCCdm?= =?us-ascii?Q?kacrNadbAs473vc3ofwAbrXZzWlga9AM+QYb7IWTsgJ6OybKn+/QscT7rwAH?= =?us-ascii?Q?gRbGImM9sLKK6tuN709l4knxbNuqwP30o4zVOngzww5SEmJLBLvUMDXX8ujV?= =?us-ascii?Q?xCWTtlBwLBFy+Bi8rY/58+bEDecS9DahG0sh3CMQ?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 11:40:13.9766 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9eae6988-9714-4f2c-161a-08de1c6015d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6685 Content-Type: text/plain; charset="utf-8" CPPC allows platforms to specify minimum and maximum performance limits that constrain the operating range for CPU performance scaling when Autonomous Selection is enabled. These limits can be dynamically adjusted to implement power management policies or workload-specific optimizations. Add cppc_get_min_perf() and cppc_set_min_perf() functions to read and write the MIN_PERF register, allowing dynamic adjustment of the minimum performance floor. Add cppc_get_max_perf() and cppc_set_max_perf() functions to read and write the MAX_PERF register, enabling dynamic ceiling control for maximum performance. Expose these capabilities through cpufreq sysfs attributes that accept frequency values in kHz (which are converted to/from performance values internally): - /sys/.../cpufreq/policy*/min_perf: Read/write min perf as freq (kHz) - /sys/.../cpufreq/policy*/max_perf: Read/write max perf as freq (kHz) The frequency-based interface provides a user-friendly abstraction which is similar to other cpufreq sysfs interfaces, while the driver handles conversion to hardware performance values. Also update EPP constants for better clarity: - Rename CPPC_ENERGY_PERF_MAX to CPPC_EPP_ENERGY_EFFICIENCY_PREF - Add CPPC_EPP_PERFORMANCE_PREF for the performance-oriented setting Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 55 ++++++++++- drivers/cpufreq/cppc_cpufreq.c | 166 +++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 23 ++++- 3 files changed, 242 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 757e8ce87e9b..ef53eb8a1feb 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1634,7 +1634,7 @@ EXPORT_SYMBOL_GPL(cppc_set_epp_perf); */ int cppc_set_epp(int cpu, u64 epp_val) { - if (epp_val > CPPC_ENERGY_PERF_MAX) + if (epp_val > CPPC_EPP_ENERGY_EFFICIENCY_PREF) return -EINVAL; =20 return cppc_set_reg_val(cpu, ENERGY_PERF, epp_val); @@ -1757,6 +1757,59 @@ int cppc_set_enable(int cpu, bool enable) return cppc_set_reg_val(cpu, ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_enable); + +/** + * cppc_get_min_perf - Get the min performance register value. + * @cpu: CPU from which to get min performance. + * @min_perf: Return address. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if = not supported. + */ +int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return cppc_get_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_min_perf); + +/** + * cppc_set_min_perf() - Write the min performance register. + * @cpu: CPU on which to write register. + * @min_perf: Value to write to the MIN_PERF register. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_set_min_perf(int cpu, u64 min_perf) +{ + return cppc_set_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_min_perf); + +/** + * cppc_get_max_perf - Get the max performance register value. + * @cpu: CPU from which to get max performance. + * @max_perf: Return address. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if = not supported. + */ +int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return cppc_get_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_max_perf); + +/** + * cppc_set_max_perf() - Write the max performance register. + * @cpu: CPU on which to write register. + * @max_perf: Value to write to the MAX_PERF register. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_set_max_perf(int cpu, u64 max_perf) +{ + return cppc_set_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_max_perf); + /** * cppc_get_perf - Get a CPU's performance controls. * @cpu: CPU for which to get performance controls. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index cf3ed6489a4f..cde6202e9c51 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -23,10 +23,12 @@ #include =20 #include +#include =20 #include =20 static struct cpufreq_driver cppc_cpufreq_driver; +static DEFINE_MUTEX(cppc_cpufreq_update_autosel_config_lock); =20 #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { @@ -582,6 +584,68 @@ static void cppc_cpufreq_put_cpu_data(struct cpufreq_p= olicy *policy) policy->driver_data =3D NULL; } =20 +/** + * cppc_cpufreq_set_mperf_limit - Generic function to set min/max performa= nce limit + * @policy: cpufreq policy + * @val: performance value to set + * @update_reg: whether to update hardware register + * @update_policy: whether to update policy constraints + * @is_min: true for min_perf, false for max_perf + */ +static int cppc_cpufreq_set_mperf_limit(struct cpufreq_policy *policy, u64= val, + bool update_reg, bool update_policy, bool is_min) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + unsigned int cpu =3D policy->cpu; + struct freq_qos_request *req; + unsigned int freq; + u32 perf; + int ret; + + perf =3D clamp(val, caps->lowest_perf, caps->highest_perf); + freq =3D cppc_perf_to_khz(caps, perf); + + pr_debug("cpu%d, %s_perf:%llu, update_reg:%d, update_policy:%d\n", cpu, + is_min ? "min" : "max", (u64)perf, update_reg, update_policy); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + if (update_reg) { + ret =3D is_min ? cppc_set_min_perf(cpu, perf) : cppc_set_max_perf(cpu, p= erf); + if (ret) { + if (ret !=3D -EOPNOTSUPP) + pr_warn("Failed to set %s_perf (%llu) on CPU%d (%d)\n", + is_min ? "min" : "max", (u64)perf, cpu, ret); + return ret; + } + + if (is_min) + cpu_data->perf_ctrls.min_perf =3D perf; + else + cpu_data->perf_ctrls.max_perf =3D perf; + } + + if (update_policy) { + req =3D is_min ? policy->min_freq_req : policy->max_freq_req; + + ret =3D freq_qos_update_request(req, freq); + if (ret < 0) { + pr_warn("Failed to update %s_freq constraint for CPU%d: %d\n", + is_min ? "min" : "max", cpu, ret); + return ret; + } + } + + return 0; +} + +#define cppc_cpufreq_set_min_perf(policy, val, update_reg, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, true) + +#define cppc_cpufreq_set_max_perf(policy, val, update_reg, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, fals= e) + static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) { unsigned int cpu =3D policy->cpu; @@ -881,16 +945,118 @@ static ssize_t store_energy_performance_preference_v= al(struct cpufreq_policy *po return cppc_cpufreq_sysfs_store_u64(policy->cpu, cppc_set_epp, buf, count= ); } =20 +/** + * show_min_perf - Show minimum performance as frequency (kHz) + * + * Reads the MIN_PERF register and converts the performance value to + * frequency (kHz) for user-space consumption. + */ +static ssize_t show_min_perf(struct cpufreq_policy *policy, char *buf) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + u64 perf; + int ret; + + ret =3D cppc_get_min_perf(policy->cpu, &perf); + if (ret =3D=3D -EOPNOTSUPP) + return sysfs_emit(buf, "\n"); + if (ret) + return ret; + + /* Convert performance to frequency (kHz) for user */ + return sysfs_emit(buf, "%u\n", cppc_perf_to_khz(&cpu_data->perf_caps, per= f)); +} + +/** + * store_min_perf - Set minimum performance from frequency (kHz) + * + * Converts the user-provided frequency (kHz) to a performance value + * and writes it to the MIN_PERF register. + */ +static ssize_t store_min_perf(struct cpufreq_policy *policy, const char *b= uf, size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int freq_khz; + u64 perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq_khz); + if (ret) + return ret; + + /* Convert frequency (kHz) to performance value */ + perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); + + ret =3D cppc_cpufreq_set_min_perf(policy, perf, true, cpu_data->perf_caps= .auto_sel); + if (ret) + return ret; + + return count; +} + +/** + * show_max_perf - Show maximum performance as frequency (kHz) + * + * Reads the MAX_PERF register and converts the performance value to + * frequency (kHz) for user-space consumption. + */ +static ssize_t show_max_perf(struct cpufreq_policy *policy, char *buf) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + u64 perf; + int ret; + + ret =3D cppc_get_max_perf(policy->cpu, &perf); + if (ret =3D=3D -EOPNOTSUPP) + return sysfs_emit(buf, "\n"); + if (ret) + return ret; + + /* Convert performance to frequency (kHz) for user */ + return sysfs_emit(buf, "%u\n", cppc_perf_to_khz(&cpu_data->perf_caps, per= f)); +} + +/** + * store_max_perf - Set maximum performance from frequency (kHz) + * + * Converts the user-provided frequency (kHz) to a performance value + * and writes it to the MAX_PERF register. + */ +static ssize_t store_max_perf(struct cpufreq_policy *policy, const char *b= uf, size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int freq_khz; + u64 perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq_khz); + if (ret) + return ret; + + /* Convert frequency (kHz) to performance value */ + perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); + + ret =3D cppc_cpufreq_set_max_perf(policy, perf, true, cpu_data->perf_caps= .auto_sel); + if (ret) + return ret; + + return count; +} + cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); cpufreq_freq_attr_rw(auto_act_window); cpufreq_freq_attr_rw(energy_performance_preference_val); +cpufreq_freq_attr_rw(min_perf); +cpufreq_freq_attr_rw(max_perf); =20 static struct freq_attr *cppc_cpufreq_attr[] =3D { &freqdomain_cpus, &auto_select, &auto_act_window, &energy_performance_preference_val, + &min_perf, + &max_perf, NULL, }; =20 diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 42e37a84cac9..be7de1222eee 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -39,7 +39,8 @@ /* CPPC_AUTO_ACT_WINDOW_MAX_SIG is 127, so 128 and 129 will decay to 127 w= hen writing */ #define CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH 129 =20 -#define CPPC_ENERGY_PERF_MAX (0xFF) +#define CPPC_EPP_PERFORMANCE_PREF 0x00 +#define CPPC_EPP_ENERGY_EFFICIENCY_PREF 0xFF =20 /* Each register has the folowing format. */ struct cpc_reg { @@ -172,6 +173,10 @@ extern int cppc_get_auto_act_window(int cpu, u64 *auto= _act_window); extern int cppc_set_auto_act_window(int cpu, u64 auto_act_window); extern int cppc_get_auto_sel(int cpu, bool *enable); extern int cppc_set_auto_sel(int cpu, bool enable); +extern int cppc_get_min_perf(int cpu, u64 *min_perf); +extern int cppc_set_min_perf(int cpu, u64 min_perf); +extern int cppc_get_max_perf(int cpu, u64 *max_perf); +extern int cppc_set_max_perf(int cpu, u64 max_perf); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); extern int amd_detect_prefcore(bool *detected); @@ -264,6 +269,22 @@ static inline int cppc_set_auto_sel(int cpu, bool enab= le) { return -EOPNOTSUPP; } +static inline int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_min_perf(int cpu, u64 min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_max_perf(int cpu, u64 max_perf) +{ + return -EOPNOTSUPP; +} static inline int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf) { return -ENODEV; --=20 2.34.1 From nobody Fri Dec 19 12:48:14 2025 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013008.outbound.protection.outlook.com [40.93.201.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF071312800; Wed, 5 Nov 2025 11:40:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.8 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342836; cv=fail; b=Mw+4DbgskUQacvwa79XKqzqVJFASjOwaBut6n+QhXwhEbWNc6n5u1nP92BEbpP0zX84KLHyE5nsEVASpuJ6E/2HNOY39Cj3ffJ5qzorRDvmHQqGJh4NEZBmzFBFoT00LyzMu1fV6btGEk3yuxfEJ4isRf3q+bV9Q6flYBtHU/2k= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342836; c=relaxed/simple; bh=EpiQytv+g0LOsBuMiiPv15ldpRua3dEQTCtNxjUU3u0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=un3f9eNsDB7rax0OGaTQxenkwgVhTgY9uVNii1kQLocJwntHMsmw5gkNJfpIVkFHcriGea+b//rauGcDupj7JVY53EN9f0P5BovdVQV8JW8fmiGEki6IJWk/esHMikdsn7TWxZxR4I8SqtgImksJgsl3sU0wL13M0NBcHn1Y+Ac= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=VcFcYF4V; arc=fail smtp.client-ip=40.93.201.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="VcFcYF4V" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wDUDc50DoM87CAKKjCgigTWwNLgJw99pN2+fLecLsDiLmVUH51DsNWdm2vlXLEf/cqaoXYIkewTALCNhjXds5jOm2Wp9rahuAq1WG96mqHl5xuf6gfX/Ot9FrsYFnuhYQag535LPWno7lWeIV76cWz0ZE3kTDeKSiiYdcsehGhS71oRJAqmmBax5iZjYNRFtUFZiBDYcBFwap8Aw96vUAMIT8mLHQ58f9i4X9q5IKjqOpR7Uqx9xliuKuYx//NSqB36cVZmkd5IqQwat11ziXjf6rtPOEYvTE2SrTVt7O4mH+QnXiHJL5nwDgu1qznrtgVgppDUP/tCkqoU42OPYFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zuxtpy3RqKlzVocwFv4y0csducYI3J6WaUUEZReXMks=; b=Q5ZsWqkSmaX10ADHUfqMN404wrHMlcCp6gh8LuevfrKLZhaVs8d5rLqkM4BKzgSoO47GKNzEAK+42hUMrDDnlW+v7m1NNcd42ZQbaGESbNYWeGCBdgOmMmoJIEMwTWNoKmibkf3JX2SmDPzvIA1ozt6jSxyBBBg+3JD3IDgj2FraJ0UYjA/q81V36ScX0tqTq7t/QCDZSJPOfE5+ZL+zs6VNEh3Nl3IOllds6y0sCRDgmOBYPO/VjdicuV27a6TbWlvlhZemDdKpvztVlRd814ax0du8EhB+qkIg4/VX/jV22nbbvbUcYIu0/nO4IiIpUpfl9r4AvFpW96nU1U89pQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zuxtpy3RqKlzVocwFv4y0csducYI3J6WaUUEZReXMks=; b=VcFcYF4V3cPkwUY2B6DQDyR+HAKpFSY8v+INuw+E+0cm+vOplKAluAtQJBQpzk0T/43A8SoP4ewjH4XkSYfCyMcjlkKpcxlyVNpXUbqop4QgCFsbauSGoNWdR5vR9AGNFCBQi+Z2xNikDconjbzgd54iiugSPCbIofZqMUuiiv1oJCQm//F834Z4C90LR7omzOZLYhdiM20L/U4gcgRDGq3IPwkRKtaGboXcTQg2PcahtJAp5SMxXrBBFmj2Qw2+Iqti62EgVBsfB26kzQhZ1NOWT9KlTKXDGXgBWSoc2qpzeUQsx1Suc7gM6JVYckOgW4WeY26z8Zl6FAvyWfvjBg== Received: from BLAPR03CA0106.namprd03.prod.outlook.com (2603:10b6:208:32a::21) by BY5PR12MB4225.namprd12.prod.outlook.com (2603:10b6:a03:211::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9275.15; Wed, 5 Nov 2025 11:40:31 +0000 Received: from BL6PEPF00020E64.namprd04.prod.outlook.com (2603:10b6:208:32a:cafe::b0) by BLAPR03CA0106.outlook.office365.com (2603:10b6:208:32a::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9275.16 via Frontend Transport; Wed, 5 Nov 2025 11:40:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF00020E64.mail.protection.outlook.com (10.167.249.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Wed, 5 Nov 2025 11:40:31 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:11 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:11 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 5 Nov 2025 03:40:04 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 5/8] ACPI: CPPC: add APIs and sysfs interface for perf_limited register Date: Wed, 5 Nov 2025 17:08:41 +0530 Message-ID: <20251105113844.4086250-6-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251105113844.4086250-1-sumitg@nvidia.com> References: <20251105113844.4086250-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E64:EE_|BY5PR12MB4225:EE_ X-MS-Office365-Filtering-Correlation-Id: 59917347-9fa7-4d9a-49b5-08de1c60200b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gbPrJnjDEp8C8Ezwwr9ng/CM0iQ/ihjNHDahEafLxCBJqQl/1lJME3ujS+jj?= =?us-ascii?Q?RtPprW4yzkbHoTcO/TdSN0vrQc1YFiueydqIm04dG5+ARr7mt9+kYZWJCAmY?= =?us-ascii?Q?BY70bJKT2Ngl96aaPKQ0H9JlPPIIxHimKWDACGE1hUaWNs36QPOmkf9AZfem?= =?us-ascii?Q?MRDu/KVYFlWqPSa8G9JWf3fkOel1q/6oW9zVwYu5IIzkmIDmmwKXJT2tBfbA?= =?us-ascii?Q?nsuT4nxi0YOxTH6xCEEQvF9Q9canEmJOpquF4nAeS87LTeovRZQapuBLw44d?= =?us-ascii?Q?mBGFtdBSBNAyIPrhPcze0pz5xbGZ+JHNi3g38XJVMEu8YghadWeGVM3M4N9W?= =?us-ascii?Q?qKeTmfibthmGVg7ao4kpXcY92wMhcDZ7I3FQLd/A2g95VcBHyi4Xqet+0A9t?= =?us-ascii?Q?j5xHERdIwi+lBOMtuTKfy11EE1TXWugqONLV4qZ+zv8gP8ny2s24t4v8Guq6?= =?us-ascii?Q?2sLs75a6GayA7Tw/QgfJJb/ivLUNFvLVSyif+3QqCdAHGVYDnr0l8zrJ0v9c?= =?us-ascii?Q?O2zILaFmPhQjHGMvEt1BnVvKlxAweJEgcHGfCKbJuxm6pPIs6gqIJe1hTLvV?= =?us-ascii?Q?nQ5tlFDFFqmFsSupQji25f/oZIXTGKwpAFdFnMXAqW90b+BSYEbmGO1/Nd/j?= =?us-ascii?Q?0rqiz0lbDaEMlQCvR8r1v0jlBNhcQRf0NPemgv/lMCFRVehb1YiaKlzz+pok?= =?us-ascii?Q?/gzxnYdFlTKJ7zh/3rI5e2pZj6/mjAWCArDvwTxmpwyNi0msJtpDtmWUJ+7s?= =?us-ascii?Q?+o88jXPRC0SuVbqPS611FrtbIg0MUzugEB0CmYT5ymtIK/BohPhNh8dogRNx?= =?us-ascii?Q?S4hecuibrMnIEJnJCc0kDTWRV8SE5Lt9zt6nbp5L1F8oBq1HPi8jhh5IREXV?= =?us-ascii?Q?LYWTrtkLRCE0DnDEqntrAcqE/6KlWvH1+12EYXx5Ys6bYDdM/q1iUuWMCfWw?= =?us-ascii?Q?zM5LwalnFNiBXWVuRoBLZNtdul/Gc4J2QXxvF4W4+LVfd3eChE3Kawl9PFdb?= =?us-ascii?Q?NpGPhjjChDv060sIkrYQ1e2Iu5Q/fyieM1V9AkSyguJnw4ZIbVj6Vw80i6SP?= =?us-ascii?Q?/Wo1nm1EKaNvnOzEzgI+xq81a8wv6kW+CZATR0cGsWzs8NQC2Muz4sENqBCN?= =?us-ascii?Q?XXQtBDS8dc5Kngxn2+cZ+HKrM3yYQ//6GKFewl7pfNZMXluDHlIJQdiuTlwt?= =?us-ascii?Q?T2FepfjpUqwgymsalE0GIwIRPOG6ca1V7UG/8tZtEsAUUatxTQH3UC6ZT9eA?= =?us-ascii?Q?pNCXG2u1IRnN4Qi7JVmh2rgx/ZgdDPTOQdUCZMQrNHs0Vz4VJYvwVylOTDt7?= =?us-ascii?Q?Czf27a09YWoOtayR9Uv91eb3IVpgWOiEHi7Rlp6g027hpqf/0ovvJq9dA6qr?= =?us-ascii?Q?HM/3M951H2oM6SzbM52Npg3DnXMLhzEAzfbhl7QvwcZLrvv2l1B2qKufDGBv?= =?us-ascii?Q?0FszLIv8ufGdDdfcjzxMyPkTmIkIB4L5J63ejaMLX7k24T1cwgVN27hiJSnW?= =?us-ascii?Q?8vOWLmh3+K9sGMvQ7RXGxCYUZ4V9lCf1Nx9F5IjZg/A3rnlssUqKlOtoK9CA?= =?us-ascii?Q?ABZTzDthIH4cTtOlo+hABXka9clcNl6MJntlE9ud?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 11:40:31.1483 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59917347-9fa7-4d9a-49b5-08de1c60200b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4225 Content-Type: text/plain; charset="utf-8" Add sysfs interface to read/write the Performance Limited register. The Performance Limited register indicates to the OS that an unpredictable event (like thermal throttling) has limited processor performance. This register is sticky and remains set until reset or OS clears it by writing 0. The interface is exposed as: /sys/devices/system/cpu/cpuX/cpufreq/perf_limited Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 26 ++++++++++++++++++++++++++ drivers/cpufreq/cppc_cpufreq.c | 12 ++++++++++++ include/acpi/cppc_acpi.h | 10 ++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index ef53eb8a1feb..9b8da3ef06db 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1810,6 +1810,32 @@ int cppc_set_max_perf(int cpu, u64 max_perf) } EXPORT_SYMBOL_GPL(cppc_set_max_perf); =20 +/** + * cppc_get_perf_limited - Get the Performance Limited register value. + * @cpu: CPU from which to get Performance Limited register. + * @perf_limited: Pointer to store the Performance Limited value. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if = not supported. + */ +int cppc_get_perf_limited(int cpu, u64 *perf_limited) +{ + return cppc_get_reg_val(cpu, PERF_LIMITED, perf_limited); +} +EXPORT_SYMBOL_GPL(cppc_get_perf_limited); + +/** + * cppc_set_perf_limited() - Write the Performance Limited register. + * @cpu: CPU on which to write register. + * @perf_limited: Value to write to the perf_limited register. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if = not supported. + */ +int cppc_set_perf_limited(int cpu, u64 perf_limited) +{ + return cppc_set_reg_val(cpu, PERF_LIMITED, perf_limited); +} +EXPORT_SYMBOL_GPL(cppc_set_perf_limited); + /** * cppc_get_perf - Get a CPU's performance controls. * @cpu: CPU for which to get performance controls. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index cde6202e9c51..a425ad575aa6 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -1043,12 +1043,23 @@ static ssize_t store_max_perf(struct cpufreq_policy= *policy, const char *buf, si return count; } =20 +static ssize_t show_perf_limited(struct cpufreq_policy *policy, char *buf) +{ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_perf_limited, bu= f); +} + +static ssize_t store_perf_limited(struct cpufreq_policy *policy, const cha= r *buf, size_t count) +{ + return cppc_cpufreq_sysfs_store_u64(policy->cpu, cppc_set_perf_limited, b= uf, count); +} + cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); cpufreq_freq_attr_rw(auto_act_window); cpufreq_freq_attr_rw(energy_performance_preference_val); cpufreq_freq_attr_rw(min_perf); cpufreq_freq_attr_rw(max_perf); +cpufreq_freq_attr_rw(perf_limited); =20 static struct freq_attr *cppc_cpufreq_attr[] =3D { &freqdomain_cpus, @@ -1057,6 +1068,7 @@ static struct freq_attr *cppc_cpufreq_attr[] =3D { &energy_performance_preference_val, &min_perf, &max_perf, + &perf_limited, NULL, }; =20 diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index be7de1222eee..8baff46f2ac7 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -177,6 +177,8 @@ extern int cppc_get_min_perf(int cpu, u64 *min_perf); extern int cppc_set_min_perf(int cpu, u64 min_perf); extern int cppc_get_max_perf(int cpu, u64 *max_perf); extern int cppc_set_max_perf(int cpu, u64 max_perf); +extern int cppc_get_perf_limited(int cpu, u64 *perf_limited); +extern int cppc_set_perf_limited(int cpu, u64 perf_limited); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); extern int amd_detect_prefcore(bool *detected); @@ -285,6 +287,14 @@ static inline int cppc_set_max_perf(int cpu, u64 max_p= erf) { return -EOPNOTSUPP; } +static inline int cppc_get_perf_limited(int cpu, u64 *perf_limited) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_perf_limited(int cpu, u64 perf_limited) +{ + return -EOPNOTSUPP; +} static inline int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf) { return -ENODEV; --=20 2.34.1 From nobody Fri Dec 19 12:48:14 2025 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010051.outbound.protection.outlook.com [40.93.198.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B10A30FC3A; Wed, 5 Nov 2025 11:40:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342845; cv=fail; b=ugn5Yvw48tTw8SK7wm+XDX9YN1n1UnyiCLFZQqNuMhvDm4p2FspIfTZtnjZCoMxcvu1X7Qvs+uYrJhgachEc9kLvls/2KAn0ieOAkpbnxeUeBQZmEjHgEAyw/8kVPtpY9IylXlTc5u+wCAyQQhgKCliGobKEPHI0zlsc/9ALAw4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342845; c=relaxed/simple; bh=PniQjyXAvgNxwXm4TCcafnkKbSns9iqRDYXZ4Y4xdcc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=N8t2FbWkWGm5jKVKyT29vtmEgrxhNMP4niNm5f7YjwrjB3B19JI4nVPXclGaszRliaRK3Yteje4NpxZOL7+YEfNTAnYXQjeZIFN1RG6r1hg0HYynhd5mvnITwGYA2V+yYb9ZLzNcc51w9Wnl72Y3stq2xzF5+EZo4smL7hliLi0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=sXb6iUNt; arc=fail smtp.client-ip=40.93.198.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="sXb6iUNt" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Q0RKGaFduot+R55AusK4jLM+8BhMadKx9PFigGVjXoEIQ8KUSbwWQbDUI4Xu99o95ck1O+m2FvFnYru4DNeEksQ6p9/d1s7y5Os/6dQ5OIfACs0VIzzY2a+byjVHLXQbRoDy3dgGx1sYbNEkTNBGZJzLMuz7crn2XzNLT/7FKb9auIyqdAEHYfyMPG8fXYt1zhpvKURyOW+tf24nT7KIUA+KyR926Dp+BL2XGsGmFnSFS0yCJLkoSkVtIJ+zPAd33kHFZMogZngPpEAQY2252wunwaTG7PVPDuTJko/f8FO6gYgRJq/yRJzaG0sBJwU/v9p6RMlI/RXKXFZtxxQBwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oXgK7YNZyzbaGZoAMKsMSgnEOmVF9pqLUDnInBMDG4I=; b=byNfLUaEXUkJT22TV+QS3BCIwtGalVnGL3vLYHmtSstj3XD7veehuNk7RiSkXQiOXnt8GsmHsM5csS3YZ4jfRg7UhShJHY+auzMbuADtTRjUATqOJlNMjcitP9262YtGpPWTQHUSNYekx3eIZaONaT0q+WACTs1AbP0JRN4i/S2YWkKiW2QUTMu4rUva89b0FwzZlYLrin4fIKYv/oEkSqNM3FSSlkndAxIKnYhMAwPrJfwmSvMAio9TTC3enuck0PdEQ7f2WCI2FFCB+0hFMiL11xE7Zhn1qbrV90yEBifFXR/iJ8wy8nff2h635DotXCJc4XB+Xt40A4OIbQfdCA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oXgK7YNZyzbaGZoAMKsMSgnEOmVF9pqLUDnInBMDG4I=; b=sXb6iUNtWZYbfqK8d2umVNc65e9bBne4zy6b4CeKvyfWMCE/lIeBIVfZvoaQwBORGitC5y2rVh4a2cKMKMjmDw/ct3dq0eWo59HrdIJ2zqW7/NJm3NjI9NP9j7bPVH6V4p8MDZ/HwN+osGKLTl5ZjKS89rCKFkafUgBBIe34hSwHphxXHPt/XYpTWS46OvoRb+tnYIp9k5VzdA3wEp+ycNj8/N0ejU8bGB4MIp2hxxtevdfm4MKyXkJ6+Li0mrRtABzOzTF9OsgffskMTyknRf4t9M5+Epnrngm1+MDHXLWsK5+1C7gC0V0IRPiLHosMYjtxX4RiQxXYwV3a0OSozA== Received: from BL1P221CA0012.NAMP221.PROD.OUTLOOK.COM (2603:10b6:208:2c5::6) by DS0PR12MB7970.namprd12.prod.outlook.com (2603:10b6:8:149::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.7; Wed, 5 Nov 2025 11:40:40 +0000 Received: from BL6PEPF00020E65.namprd04.prod.outlook.com (2603:10b6:208:2c5:cafe::91) by BL1P221CA0012.outlook.office365.com (2603:10b6:208:2c5::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.7 via Frontend Transport; Wed, 5 Nov 2025 11:40:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF00020E65.mail.protection.outlook.com (10.167.249.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Wed, 5 Nov 2025 11:40:39 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:21 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:20 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 5 Nov 2025 03:40:13 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 6/8] cpufreq: CPPC: Add sysfs for min/max_perf and perf_limited Date: Wed, 5 Nov 2025 17:08:42 +0530 Message-ID: <20251105113844.4086250-7-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251105113844.4086250-1-sumitg@nvidia.com> References: <20251105113844.4086250-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E65:EE_|DS0PR12MB7970:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cf9180f-b3a8-426f-57ed-08de1c602540 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2K6i6wUFP6YGeSjycQRCEOtmIXZp5TVVEcxZtAbHAXG2sk+5gw7zq6c+kw02?= =?us-ascii?Q?J6atJSZh4znnY3QNPco003kvsm1iO9GWygcTQzSojZFXC1ybqXjtzy0mykCA?= =?us-ascii?Q?VzLqW3yUk5TUyVgUGl6n8ERV8jsOXoe0lQx00oIKs076ZNMjjhk1uDyn2vy+?= =?us-ascii?Q?CpEGEhtHYFzN+DkzD21irYJW82XWFkGH+ThaZQICgEN+LDrvz0ANwrH+nWl1?= =?us-ascii?Q?3Bwqbw78azHQNxEedkaJEaS8Gxzz185DXTnkoFe2NNwwsWGrtAISbqT+ogHy?= =?us-ascii?Q?iN896o+AWGd2d4WariVt6rXKY4xPT64XSOyUk0do3W8AhV+BLG+uWO7wSS+t?= =?us-ascii?Q?BD+zaZafsRRO0rSb40ijVw2KtNDXH+cmsFHZk56vP2st/+0eb9TlGERO1OJv?= =?us-ascii?Q?m8k6fsRA3Wx590oYDMcrIfoHvK6nI6x5HVTjABjjKUJFKLjhzJGM3sqnen44?= =?us-ascii?Q?BUd/ZNUhVTGH/XTgYehqH7OLT5kyXQA8X0YRTzy/sM12OLXXafXNfeMYzYCJ?= =?us-ascii?Q?u0u1KysApFbCoWup48zT5ambBVRxGYTgmkAK79312HkLE7Ph1/zBGPWV0KbG?= =?us-ascii?Q?U6gBzR/Wc6wJoZiv1TqojqBibqeJESoWXCmBBqegVh+oyrLo9oZmp/BdU2hb?= =?us-ascii?Q?UB4wnlknH4vErr37kUHjiPDPN/23W2JPGkkeE+C6mGT33hwjh8TnixGwrdC4?= =?us-ascii?Q?D3nMJ36yDAnDFPwbQHNL8AhsJfurCohlktLNgfTq9iDoT/kv8xQl1TsNcTCo?= =?us-ascii?Q?poZ26Wwwn4iHGeF9UB32dXv0jlzbGoLeB1LKDVS8aZxmJl1hZ4czxixWr6Xb?= =?us-ascii?Q?TNzQ1NyA+fX3pXOsFFEjz3RHsdlVV+fHlHNzqbQx9sKEoaIH14fopCPOsI31?= =?us-ascii?Q?dCoatOXfx1OWek+pL0CpQ8tfeKY4GUfj3nRbu3lRGeLRCWK+JsynVCoSRcKM?= =?us-ascii?Q?7Evz9etrWbjsxM8ZH1ZeY6uDovRQZrTusNfLoedKMuvfoiyU7SigMqCQ1Z9C?= =?us-ascii?Q?93Q6K0f8/bNR2lt0u4kSVW/i9vzVPRUllhRmpYWLcFfmefqzjM49bMIFQvFy?= =?us-ascii?Q?mR8H0a9V2n0FAYRTi0tWn4pUAfOwMtlmgMxmWkG7kuinOEU2LZhVNpBDxTcC?= =?us-ascii?Q?P8q191hSyHqsGxdMe78u+W5txBk0UUopfSr4a4wXVBbgMvxS5482mq65raue?= =?us-ascii?Q?7jb+QFwMa1EwVueShKLq778rcUccEiIbM7s2KaYxjTaQoV5F/TvbrEkAjWUl?= =?us-ascii?Q?nIQMYedBG552c503zDRz9WUpX0B0HeyqBD1dUU69PsxIejQafR+jSBjWr/IL?= =?us-ascii?Q?6TeslxGuxBIyfjjlhc4rJekm/F5l9KDhq2DeKYqr5q5tYTctmi4k6jimjRTG?= =?us-ascii?Q?b5EBJ15Cfx5TWmaj6hWif1BxtetZ9jq2VuPyKC0+DqbquNvXblBxco8NVa20?= =?us-ascii?Q?aWceZ0dtRSYuKhDGfGxeYrln68QtDlmN31fNXLXPiNWbl6nA7B7TPj00FDxv?= =?us-ascii?Q?lJbHh03Misit/rY7Dwoz/dKM4HxGQbGSbP7IVflhtKm9EHU/vWmuAubkfJvG?= =?us-ascii?Q?MkXUlaWLQVy5RdIEBedsaEhYWlRqpSxmb2wHq6WP?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 11:40:39.8654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cf9180f-b3a8-426f-57ed-08de1c602540 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E65.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7970 Content-Type: text/plain; charset="utf-8" Add sysfs interfaces for Minimum Performance, Maximum Performance and Performance Limited Register in the cppc_cpufreq driver. Reviewed-by: Randy Dunlap Signed-off-by: Sumit Gupta --- .../ABI/testing/sysfs-devices-system-cpu | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documenta= tion/ABI/testing/sysfs-devices-system-cpu index 8aed6d94c4cd..6f1f70696000 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -327,6 +327,52 @@ Description: Energy performance preference =20 This file is only present if the cppc-cpufreq driver is in use. =20 +What: /sys/devices/system/cpu/cpuX/cpufreq/min_perf +Date: December 2025 +Contact: linux-pm@vger.kernel.org +Description: Minimum Performance Frequency + + Read/write a frequency value in kHz from/to this file. This + file conveys the minimum performance level (as frequency) at + which the platform may run. The frequency value is internally + converted to a performance value and must correspond to a + performance level in the range [Lowest Performance, Highest + Performance], inclusive. The minimum must be less than or equal + to the maximum performance. The performance range can be checked + from nodes: + /sys/devices/system/cpu/cpuX/acpi_cppc/highest_perf + /sys/devices/system/cpu/cpuX/acpi_cppc/lowest_perf + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/max_perf +Date: December 2025 +Contact: linux-pm@vger.kernel.org +Description: Maximum Performance Frequency + + Read/write a frequency value in kHz from/to this file. This + file conveys the maximum performance level (as frequency) at + which the platform may run. The frequency value is internally + converted to a performance value and must correspond to a + performance level in the range [Lowest Performance, Highest + Performance], inclusive. The performance range can be checked + from nodes: + /sys/devices/system/cpu/cpuX/acpi_cppc/highest_perf + /sys/devices/system/cpu/cpuX/acpi_cppc/lowest_perf + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/perf_limited +Date: December 2025 +Contact: linux-pm@vger.kernel.org +Description: Performance Limited + + Read/write a 32 bits value from/to this file. This file indicates + to OSPM that an unpredictable event has limited processor + performance, and the delivered performance may be less than + desired/minimum performance. + + This file is only present if the cppc-cpufreq driver is in use. =20 What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} Date: August 2008 --=20 2.34.1 From nobody Fri Dec 19 12:48:14 2025 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012036.outbound.protection.outlook.com [40.107.209.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D6B2310625; Wed, 5 Nov 2025 11:40:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342858; cv=fail; b=GHWM+Si4qjx6vX7pQVO9r4VMsy8Im9oli5pWGW+XptGxiw2l2lO1IHCpSm8wFQsagXAzZOQi/IqdZbpJs6j/Oah0oCcyHENKT+rhr5GTy18tKpIRo0rHTuwszNoilo/r3JenZb9roSrrrHZe7uBe+ZmGpjpfRZfCO66OrH/NXaE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342858; c=relaxed/simple; bh=Ah2cIBXZ7TSkG7xVrswcbkITbG1KYr+13nhQsKunUQs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NXAbqkyfnSqx/zvD1zkh4GPcwYknptvN/xojZTthfSpxJNUHwe6jJKHxfNaTkXJ/dqCTUB+3IDlJ+1kJOfZCuKFoeb0puzheKQ2TOLAuI+bjy0MBSyEpV82KvpAm1dbZWMHx0U+1LDMuCV4Ab4Hdp0fiia6n/MGbEhyK5WI2dhI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=azNAkXSF; arc=fail smtp.client-ip=40.107.209.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="azNAkXSF" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZvevqPRnltmPoTgjX4wDzFjFvKx4z84RoG0kpWf1UgnhgG01fcWNIpw1AhxW7u88UY4qe6OuFrvVkkLQhqAswY/CyH2RvpUFlxVqt54DwcFN/rWHux7XhFmVzfxrdhW2ZUGw8R5NAkiXQdebdwYJXdUeVoNWSZ9r1wa7p8moS8bjdrBgZfcTYuX6IkEIn5dJDCfRs4mvhw4BuVk64PeZD09wgWJCvOTqhhmSeJeK07/W34VRnSRJfpD2NuAJ8rIYropUzDh0E33RZRU7Na9vVhuaGHQ/ZK7S1g5pk6asxstGinvSXia1WLOwXsywvaQxQWo95W82+kxuo5j08Isjtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2WKIVaSiOm18cjbn0+5HggKGhjCVSgpSTWGQCfV7l/Q=; b=fotyOAK9PKH1c6svjs3DCLBV1IouG26/lpUXZprl2m/SM0NmS5wg3ZqcE16Yxnt/gpi9btR18fHnS2xuxJhVTKrqf3OnPSFv0i4gY15mobeLrpaQppbVjxjQQai6wi4LcPCVSr5iJUolylyVrOAhXHR1IsfjZIslGDQilmmbCKw8+r79aP0mZOpEntxqbuJ5zorPa3x/1mbdd3H7Gn0AKo4DvyRlvFqdmTJA7KQ3F5q87IwujOmfkPTlW+twUIGQDLC9VYMqxRbabYREBV/EsqFs4t1ub6AaB7PwqMjWLS0VURverHOVS+yKETwXKcgiRNWaHzR+eQpyR7vKQIjsfw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2WKIVaSiOm18cjbn0+5HggKGhjCVSgpSTWGQCfV7l/Q=; b=azNAkXSFJWTPqxes0ypBcxjuJRaSEipR60uVbmPzqMdFjHtzRD99vOIqKWZL3xWQLaXuu4K3xkM/eTWcOKMdrSh+x0gdxygWAPCjPtUiTGtv0mIrWhIYV8R8ClM4mTXbmLgiOGDUlqe7ewi9Oxp84MIT6n98efTlv/Vg+HAnxx4PoxAyvEm4PB2GZeF0fL0lYiY8CSHAdSOY3NzZ8FJIQFsCjJHW/cf0rFPzaAdShp2GS0NO1PT9Q82+ezuuZqy2S1ZfMtEdbd30NW7pyMoTGLF0Vcf32Sd21/LHu5pchEbiTQ0QVKaxJnryLtRbbHw/bDyoDSWNsf9H3tujRldSpw== Received: from IA4P220CA0010.NAMP220.PROD.OUTLOOK.COM (2603:10b6:208:558::15) by MN2PR12MB4454.namprd12.prod.outlook.com (2603:10b6:208:26c::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.10; Wed, 5 Nov 2025 11:40:52 +0000 Received: from BL6PEPF00022575.namprd02.prod.outlook.com (2603:10b6:208:558:cafe::44) by IA4P220CA0010.outlook.office365.com (2603:10b6:208:558::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.10 via Frontend Transport; Wed, 5 Nov 2025 11:40:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL6PEPF00022575.mail.protection.outlook.com (10.167.249.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Wed, 5 Nov 2025 11:40:52 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:30 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:29 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 5 Nov 2025 03:40:22 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 7/8] cpufreq: CPPC: update policy min/max when toggling auto_select Date: Wed, 5 Nov 2025 17:08:43 +0530 Message-ID: <20251105113844.4086250-8-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251105113844.4086250-1-sumitg@nvidia.com> References: <20251105113844.4086250-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022575:EE_|MN2PR12MB4454:EE_ X-MS-Office365-Filtering-Correlation-Id: 86904117-0aff-4744-8b66-08de1c602cbe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4c3uZXSVBxvc3cYl0YCvYHVRZq4YFMNBuhNGJVCRZ0n1mEpBgslz5QRCaTUD?= =?us-ascii?Q?vd7Tapp8eBbRK8f0ndGEbhMWaxnXVnqKsWxEhoo0xSM0cM+tcLdqAVLhAZ1X?= =?us-ascii?Q?bL3JA2JJdBfrtUgWyLBVydvMIIFQRbY78h/J2Ms7r9N+oh7Oq2eHnMq8ePfc?= =?us-ascii?Q?tf7UQ5cI7ahyC/44NCsfG2C/9Fvs5s6geHP7Jnb6QGJkrCgOhm10HNzF1QcN?= =?us-ascii?Q?G/nVCVAVPUHoEHDGn0U6IeEiKe0xpg6dQaEBWZAjbeJyVKEYCfDNGVSyTbWP?= =?us-ascii?Q?KrkRJtxnStTz9fEi44vZ93cwBFRRAcv4Ki9XkPFOjRdroSj8lm6PQxkanil7?= =?us-ascii?Q?N2ILGXKLSweJWLGNcx0Zz33tOHisC+DIJMoHfFILb9ebcsvwmY3I++ceruJO?= =?us-ascii?Q?hZONZAtVsAfrHaXuQTwhRMRESYSauhVILadaKm9R508olEbDjSd++aiZNeOR?= =?us-ascii?Q?zjy2tst0A1MS1jA5x9Cq8MR73myWLYZdkKb7e3LNXWIb/08AXiGkaW3KfElm?= =?us-ascii?Q?K2noNO7/jk3FXSfH4jWp1/5j11SInNgaWJfEhoo30nA0e6bfqP4GKigfQIUe?= =?us-ascii?Q?7sR+2jig4VV1fXviVF9uorlfRQBCXKiyEyty3FGYdJG2j6tZUoHQNmSwBaRM?= =?us-ascii?Q?HHJrT6Z08Ogb7tE6HPUz1fh2V7hoIJGwFpTNSLtZGVeT+sz25XKEav4yT4AY?= =?us-ascii?Q?MQ/KlzsA0G+EI67Uv4Cs6kk21FR1fGFDfHUav+iZSGomqObuLIz5RLnskVE+?= =?us-ascii?Q?3G5d7tfEEmbtM/FmaxRjqsjzT4IdOekz7UQkwk5V69l07yRK9aAop85coyaB?= =?us-ascii?Q?R9MmfV5YRJfHzBsbpXQwVMy4lftWIScJZm4dZWKX1wl178YSO4TW68PYEFrN?= =?us-ascii?Q?IrVAUEGH4sdkpDX4LqHC9+qQ9PPJ0qX8LFLk3LBtzqtVuDPejlxWIwk0ZtNK?= =?us-ascii?Q?aNHG/LPEhKH9lpN8qn4jWDXomvTYEYS08sIJsEkoDo84zRi7Q+Yv+Z0IBijb?= =?us-ascii?Q?wjOeqOCK9nHsFWgPVVkD4grekzoY7ynJZ/TQwMi8004kEJW7zdMfStsevYjJ?= =?us-ascii?Q?tbJ6m1j92vAH/MrdpnJwG1o19s+H0Wct7MrHHoK0jfViRxC9uAmR/5eneDs1?= =?us-ascii?Q?BFiQCJY1kLbIvQuXuv6Wzmr/83RZ+srIDGYTi1c/MNub+nU8YCycK0j3vPkz?= =?us-ascii?Q?iNZbc47+sTCGZubc+tM4PrjXjWmugYR+dZIJcYY77qFECiImbxWH7yhKBYEe?= =?us-ascii?Q?axUxkxVUVlzVR7nOSjfY7yw2zPE94IL89Dolf+JrG1IbUEJvyAPzOSFToCW2?= =?us-ascii?Q?pLlabIJUoYmBHPqf0xx9zaZ1RmzrgyNs17PJXbG4hHV8s1qTDuwkFKupsIfg?= =?us-ascii?Q?FYDFN03HFptHUOZZYfLlw3EuC2Js3R85dFkXoQx4XGo3gdsjV3UcQedkQxlh?= =?us-ascii?Q?lcPfjk5uh+hEjvT8Qyi2R2nizLxyTv7YcoI10NJQdCudmKGVVrlzdmYO/X18?= =?us-ascii?Q?d31fSBOykZFBoJLRo0j9Fomv3XoMQtzCilYOxUcDJMBitzHaN8X7liPFGXwA?= =?us-ascii?Q?J1xQHuHCgVUmT+lDkBqUvQegoZ+IkqTgFANuBsbC?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 11:40:52.3911 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86904117-0aff-4744-8b66-08de1c602cbe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022575.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4454 Content-Type: text/plain; charset="utf-8" When CPPC autonomous selection (auto_select) is enabled or disabled, the policy min/max frequency limits should be updated appropriately to reflect the new operating mode. Currently, toggling auto_select only changes the hardware register but doesn't update the cpufreq policy constraints, which can lead to inconsistent behavior between the hardware state and the policy limits visible to userspace and other kernel components. When auto_select is enabled, preserve the current min/max performance values to maintain user-configured limits. When disabled, the hardware operates in a default mode where the OS directly controls performance, so update the policy limits accordingly. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 67 ++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index a425ad575aa6..d1b44beaddda 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -646,6 +646,26 @@ static int cppc_cpufreq_set_mperf_limit(struct cpufreq= _policy *policy, u64 val, #define cppc_cpufreq_set_max_perf(policy, val, update_reg, update_policy) \ cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, fals= e) =20 +static int cppc_cpufreq_update_autosel_val(struct cpufreq_policy *policy, = bool auto_sel) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int cpu =3D policy->cpu; + int ret; + + pr_debug("cpu%d, auto_sel curr:%u, new:%d\n", cpu, cpu_data->perf_caps.au= to_sel, auto_sel); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + ret =3D cppc_set_auto_sel(cpu, auto_sel); + if (ret) { + pr_warn("Failed to set auto_sel=3D%d for CPU%d (%d)\n", auto_sel, cpu, r= et); + return ret; + } + cpu_data->perf_caps.auto_sel =3D auto_sel; + + return 0; +} + static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) { unsigned int cpu =3D policy->cpu; @@ -879,8 +899,49 @@ static ssize_t show_auto_select(struct cpufreq_policy = *policy, char *buf) return sysfs_emit(buf, "%d\n", val); } =20 -static ssize_t store_auto_select(struct cpufreq_policy *policy, - const char *buf, size_t count) +/** + * cppc_cpufreq_update_auto_select - Update autonomous selection config fo= r policy->cpu + * @policy: cpufreq policy + * @enable: enable/disable autonomous selection + */ +static int cppc_cpufreq_update_auto_select(struct cpufreq_policy *policy, = bool enable) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + u64 min_perf =3D caps->lowest_nonlinear_perf; + u64 max_perf =3D caps->nominal_perf; + int ret; + + if (enable) { + if (cpu_data->perf_ctrls.min_perf) + min_perf =3D cpu_data->perf_ctrls.min_perf; + if (cpu_data->perf_ctrls.max_perf) + max_perf =3D cpu_data->perf_ctrls.max_perf; + } + + /* + * Set min/max performance registers and update policy constraints. + * When enabling: update both registers and policy. + * When disabling: update policy only. + * Continue even if min/max are not supported, as EPP and autosel + * might still be supported. + */ + ret =3D cppc_cpufreq_set_min_perf(policy, min_perf, enable, true); + if (ret && ret !=3D -EOPNOTSUPP) + return ret; + + ret =3D cppc_cpufreq_set_max_perf(policy, max_perf, enable, true); + if (ret && ret !=3D -EOPNOTSUPP) + return ret; + + ret =3D cppc_cpufreq_update_autosel_val(policy, enable); + if (ret) + return ret; + + return 0; +} + +static ssize_t store_auto_select(struct cpufreq_policy *policy, const char= *buf, size_t count) { bool val; int ret; @@ -889,7 +950,7 @@ static ssize_t store_auto_select(struct cpufreq_policy = *policy, if (ret) return ret; =20 - ret =3D cppc_set_auto_sel(policy->cpu, val); + ret =3D cppc_cpufreq_update_auto_select(policy, val); if (ret) return ret; =20 --=20 2.34.1 From nobody Fri Dec 19 12:48:14 2025 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011041.outbound.protection.outlook.com [52.101.52.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C0C43112DB; Wed, 5 Nov 2025 11:41:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.52.41 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342865; cv=fail; b=lZJlFyMaORsBdfTOV3v05h8fPNKTUI5WCLeiIhvWfXdq3Oid1jeyyx2HuRYRsGoMyJVxFtkH4YZ+fZkyzeN/CqKhOnBS4wJyxBW1bh5LoLsFd1loEMByF6UB8ArRIw+GK0gbAy75Deulv1JMMO5p8TPc+jj8EnWFeJ1rA+tuqok= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762342865; c=relaxed/simple; bh=MqTDxvy5gIPj1VgjE7XnnXvYvJwehOPLcG/2r+81ddk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XBKIendtetBMERC0qxazpudmlP5K764ix3eXi3EOUCne+m3MAvxmbHmvHYFvafS+72cz6Y8sNNsnUKtpoHHw0jSC6R+CBcC8VTH08xX76zdV7LZRIbuQmZdHMX/w2TeUxKz5RJfYVYvBiV26q9WydetuiNNYUs3Wyr5ocCIpk58= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=XYvAJnQk; arc=fail smtp.client-ip=52.101.52.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="XYvAJnQk" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ENigtsa6OjA0nYFiw00Ae/DerPinpbUkld47SW5izt7tEv/OwfoWDMPf1edICQ2+MTIANICVO/ZuVbF/OInxzCeEn8L0vMi27AsvUzqH1RQCohPtcXqWxkvNCdzmt3xLwZ82+WswxN4R8RbFRG5Pc4TdFBk328e3ksxseVWlpemFPSVPwQ7hESubFWMbKQqKOMrMBBEZxhF5JtRqo4FiF0az7ARmOHllpgfrHXYM5lxMQVn3eURXTYzr/FI7K9oawBKXzSBih0qX09pmNngH0w3bxi3L1zzqYAlun91VviNBBBvLahw8ZJNWmPBMkhE0Lyr+neTgD2cvG/tSVyCcfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ChX2jcGFuU6Q8gjuGEc6Ey+Q0m1kUv4XNgPPsjEw8L4=; b=N0bwAQsMlSnnxm1f+CVX+jgB+r85qyNZfsOTiuOeAPqAD4ZMotwxqypW/LOH1f6dMIYOJgbH1Kk1zbmubc7+ctNg6RBp2c1H/e8M/nONFPZj9tTHCzUulBIbK9o0FcZa3E+FbMocSGYZBNJj2gg0J2sEw8weURJlFEGxGyEWC+o4J2U2lnuJJ5HIyyWxHBQry7YqZfmgth6skNN39uhDjjVc3FbhMZwdoiHvy3NW5qIHKqszSK9WdAhXUZqdfFZhMnq4mJ9pTobyqDKZfZII9KbkAik9VeeIZfd8n21uEDWbtVtE+QGWHHlsO9W0iXzGGRJyJ/lsnULOeIRmHCO1Fg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ChX2jcGFuU6Q8gjuGEc6Ey+Q0m1kUv4XNgPPsjEw8L4=; b=XYvAJnQkn6a1YInOujcj/08fDWG0qZZOUcvGDbm7KZEWZFxj4Qje8l6eDyepZez+QcPhTir41T0BuZtFGkiZJHhRa8Qcepii8DOohQ0dVpBiZu1htD9fgskSxTxbAywhZxwDqIE2+fPknw2qUhoH/anRJI3gnfjJLZOZsBsoo28OG0VgPBTtriKH2xpbeJCbInRYXd071ywzx3+S6LRU3pQVxlulWXW+9pY4rMIVzYAYLLrClj5MKoylHAoyDXlW/vozKeAjNSG8fthPOlhKWwKZAswtnNxex4zMjJIkdSeWJT88as/flmHGrmikNSBn1oJJGnCPqp+i7wcVYUTMew== Received: from BL1PR13CA0187.namprd13.prod.outlook.com (2603:10b6:208:2be::12) by DS7PR12MB5933.namprd12.prod.outlook.com (2603:10b6:8:7c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.8; Wed, 5 Nov 2025 11:40:57 +0000 Received: from BL6PEPF00020E5F.namprd04.prod.outlook.com (2603:10b6:208:2be:cafe::2) by BL1PR13CA0187.outlook.office365.com (2603:10b6:208:2be::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9298.8 via Frontend Transport; Wed, 5 Nov 2025 11:40:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF00020E5F.mail.protection.outlook.com (10.167.249.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Wed, 5 Nov 2025 11:40:56 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:40 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 5 Nov 2025 03:40:40 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 5 Nov 2025 03:40:33 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 8/8] cpufreq: CPPC: add autonomous mode boot parameter support Date: Wed, 5 Nov 2025 17:08:44 +0530 Message-ID: <20251105113844.4086250-9-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251105113844.4086250-1-sumitg@nvidia.com> References: <20251105113844.4086250-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E5F:EE_|DS7PR12MB5933:EE_ X-MS-Office365-Filtering-Correlation-Id: b95c9eff-769a-4395-ab34-08de1c602f5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?vtkv2xOCfYhGYmJmubox53nCmZCKf7xxRiS7AafXfqwT8vM0fodPx5kDXeoW?= =?us-ascii?Q?mn24TovtsO8h6EideeA6XxpBYR8ElY6jBxs6kbiCifq4dv//0jt1hQ4cbIzU?= =?us-ascii?Q?up6jNcBeXYZ9exIanvM/NGLoKcUs4kYJrGnv5Vqc9VIIo82LdRs34l0PwNEX?= =?us-ascii?Q?yuAqB1SgslKWOGafc1FzOGERrnGKUxz/oerdspg4dt9p6WPxgNYeqQYTiheF?= =?us-ascii?Q?3LBf0g49l9qaptzDhecdqja+9M9J31TZXnE5BzQI3RHc1mFtyaQc+O0/xvCP?= =?us-ascii?Q?9xws2lujQSlf9bMuNKYbTWubGRQDV5LTQVCNwHUlLPNXfMhKQmdRCOwcNgfF?= =?us-ascii?Q?6KWA4ops/RD9iosK1MGUielRAQ6F/HiTrCDlbECXtHBzuHoNaHBSTrayBW4D?= =?us-ascii?Q?SAZ2RADAzPZ31VpUWMekzHpABUNQEmUlY2uJUB1VAWqa+mi/zaqsW3Dl6cqf?= =?us-ascii?Q?+oIh89p0XxEmbGG59PJDPMqokdnxoKKEaFZUq/40/fNi6Mn8hvmtrik2tImP?= =?us-ascii?Q?gZyGSYl5R8cVfX/PS1W4Vmo6X9QpYVTkwS49c1RoaIQD5b91G/EUiKz2dh57?= =?us-ascii?Q?Jqvbusiy1yXChUmnn0nvu1m1oRnAWsf6k/VJzerkT274hwWOBzmasgUXNXHs?= =?us-ascii?Q?1Ah5+E9j1eOn/6H7k11S4IagiHJRRYUYfvsYeBTJ5sHxcjXheqCMQeVS1waH?= =?us-ascii?Q?KCsWD6vWGoqIiuHK+17S1gv7Fqq0TyMGiAE2G310Nep+Iflbz8qYetCxvjtj?= =?us-ascii?Q?7/tyoZRVRFRkN142StB9s3vhcjFTPWtk1DXfN/hv1RVOWPX9SMGBfXAnAO+B?= =?us-ascii?Q?WNezzp/5DKqdgHhOUmuDlocbZZtuYkobMbVGsUD9vNKpU/z3AMlJg35n2HAU?= =?us-ascii?Q?umRVVfd/WTDTPhNkZUr+ZKbXANhXlg68ewMoV8HVgNjxKZgtw3qo7O4QooVQ?= =?us-ascii?Q?tzZaZoCL9+ZS0ocpuXKU+Hb2hhf9GDB3Qc+JNK0nx+yx4SYDnqY6xYsf4lkq?= =?us-ascii?Q?J/SoyfT7/3t64lTPQ8W/z6GFyGTAAarT6XrEB/Q7uTQDgcavXplL/Jo3aJsu?= =?us-ascii?Q?yzTqlyYrW+AWZ0idqyG7dZOfSmAp6cIoKfU9+Qf0N341QMvZEh9uA/12GcqP?= =?us-ascii?Q?YYhn9d/aT2sr9f3CP7rf9DmW2Qsu8/aycwjPKuNPtu/p2bGCom2k1CZtNO4t?= =?us-ascii?Q?4RbKv5PNB+5oNT/XNYmeIDPuz2h4bPQQ8wUl71g2SoUWFjhd1WeAg6VjqLEe?= =?us-ascii?Q?ErYZkkTP3YapC/870dKDy1emq5FJJNa7gHrEBZkaCXTVZzOeL4uQcq2ZBXH6?= =?us-ascii?Q?c5EfKaaIN4Ra75iN0mjgTRSC96TB6/jTodNBfWscGEJVoFc8UAvBfZemlJSb?= =?us-ascii?Q?DKfmFV4td18r+tPsUnMFpa3MS5OXFMImAdlPXlXSG/IaqQJ5v9VEhdVTpRnm?= =?us-ascii?Q?69TM0stQucbjbQLXb4u74kJqIoDf1fxEA/srn8IYS8N7p6+zAWips4m1U42V?= =?us-ascii?Q?g/hh4YrkxcWQZRDQfROcqikPq5e/sYpiEAsdZaw9FbTGEjRI1nLu4KlE0TMc?= =?us-ascii?Q?+t+rj0hglEuH6CIDfvMX1xsiudF3Ql9m2wMLoWod?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 11:40:56.7974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b95c9eff-769a-4395-ab34-08de1c602f5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E5F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5933 Content-Type: text/plain; charset="utf-8" Add kernel boot parameter 'cppc_cpufreq.auto_sel_mode' to enable CPPC autonomous performance selection at system startup. When autonomous mode is enabled, the hardware automatically adjusts CPU performance based on workload demands using Energy Performance Preference (EPP) hints. This parameter allows to configure the autonomous mode on all CPUs without requiring runtime sysfs manipulation if the 'auto_sel' register is present. When auto_sel_mode=3D1: - All CPUs are configured for autonomous operation during module init - EPP is set to performance preference (0x0) by default - Min/max performance bounds use defaults - CPU frequency scaling is handled by hardware instead of OS governor For Documentation/: Reviewed-by: Randy Dunlap Signed-off-by: Sumit Gupta --- .../admin-guide/kernel-parameters.txt | 12 ++ drivers/cpufreq/cppc_cpufreq.c | 197 +++++++++++++++--- 2 files changed, 182 insertions(+), 27 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index b8f8f5d74093..048f84008a7e 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -929,6 +929,18 @@ Format: ,,,[,] =20 + cppc_cpufreq.auto_sel_mode=3D + [CPU_FREQ] Enable ACPI CPPC autonomous performance selection. + When enabled, hardware automatically adjusts CPU frequency + on all CPUs based on workload demands. In Autonomous mode, + Energy Performance Preference(EPP) hints guide hardware + toward performance(0x0) or energy efficiency (0xff). + Requires ACPI CPPC autonomous selection register support. + Format: + Default: 0 (disabled) + 0: use cpufreq governors + 1: enable if supoorted by hardware + cpuidle.off=3D1 [CPU_IDLE] disable the cpuidle sub-system =20 diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index d1b44beaddda..0a55ab011317 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -28,8 +28,12 @@ #include =20 static struct cpufreq_driver cppc_cpufreq_driver; + static DEFINE_MUTEX(cppc_cpufreq_update_autosel_config_lock); =20 +/* Autonomous Selection */ +static bool auto_sel_mode; + #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { FIE_UNSET =3D -1, @@ -272,8 +276,13 @@ static int cppc_cpufreq_set_target(struct cpufreq_poli= cy *policy, freqs.old =3D policy->cur; freqs.new =3D target_freq; =20 + /* + * In autonomous selection mode, hardware handles frequency scaling direc= tly + * based on workload and EPP hints. So, skip the OS frequency set request= s. + */ cpufreq_freq_transition_begin(policy, &freqs); - ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); + if (!cpu_data->perf_caps.auto_sel) + ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); cpufreq_freq_transition_end(policy, &freqs, ret !=3D 0); =20 if (ret) @@ -565,6 +574,12 @@ static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(= unsigned int cpu) goto free_mask; } =20 + ret =3D cppc_get_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err reading CPU%d perf ctrls: ret:%d\n", cpu, ret); + goto free_mask; + } + return cpu_data; =20 free_mask: @@ -666,11 +681,81 @@ static int cppc_cpufreq_update_autosel_val(struct cpu= freq_policy *policy, bool a return 0; } =20 +static int cppc_cpufreq_update_epp_val(struct cpufreq_policy *policy, u32 = epp) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int cpu =3D policy->cpu; + int ret; + + pr_debug("cpu%d, epp curr:%u, new:%u\n", cpu, cpu_data->perf_ctrls.energy= _perf, epp); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + ret =3D cppc_set_epp(cpu, epp); + if (ret) { + pr_warn("failed to set energy_perf for cpu:%d (%d)\n", cpu, ret); + return ret; + } + cpu_data->perf_ctrls.energy_perf =3D epp; + + return 0; +} + +/** + * cppc_cpufreq_update_autosel_config - Update Autonomous selection config= uration + * @policy: cpufreq policy for the CPU + * @min_perf: minimum performance value to set + * @max_perf: maximum performance value to set + * @auto_sel: autonomous selection mode enable/disable (also controls min/= max perf reg updates) + * @epp_val: energy performance preference value + * @update_epp: whether to update EPP register + * @update_policy: whether to update policy constraints + * + * Return: 0 on success, negative error code on failure + */ +static int cppc_cpufreq_update_autosel_config(struct cpufreq_policy *polic= y, + u64 min_perf, u64 max_perf, bool auto_sel, + u32 epp_val, bool update_epp, bool update_policy) +{ + const unsigned int cpu =3D policy->cpu; + int ret; + + /* + * Set min/max performance registers and update policy constraints. + * When enabling: update both registers and policy. + * When disabling: update policy only. + * Continue even if min/max are not supported, as EPP and autosel + * might still be supported. + */ + ret =3D cppc_cpufreq_set_min_perf(policy, min_perf, auto_sel, update_poli= cy); + if (ret && ret !=3D -EOPNOTSUPP) + return ret; + + ret =3D cppc_cpufreq_set_max_perf(policy, max_perf, auto_sel, update_poli= cy); + if (ret && ret !=3D -EOPNOTSUPP) + return ret; + + if (update_epp) { + ret =3D cppc_cpufreq_update_epp_val(policy, epp_val); + if (ret) + return ret; + } + + ret =3D cppc_cpufreq_update_autosel_val(policy, auto_sel); + if (ret) + return ret; + + pr_debug("Updated autonomous config [%llu-%llu] for CPU%d\n", min_perf, m= ax_perf, cpu); + + return 0; +} + static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) { unsigned int cpu =3D policy->cpu; struct cppc_cpudata *cpu_data; struct cppc_perf_caps *caps; + u64 min_perf, max_perf; int ret; =20 cpu_data =3D cppc_cpufreq_get_cpu_data(cpu); @@ -734,11 +819,31 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_polic= y *policy) policy->cur =3D cppc_perf_to_khz(caps, caps->highest_perf); cpu_data->perf_ctrls.desired_perf =3D caps->highest_perf; =20 - ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); - if (ret) { - pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", - caps->highest_perf, cpu, ret); - goto out; + if (cpu_data->perf_caps.auto_sel) { + ret =3D cppc_set_enable(cpu, true); + if (ret) { + pr_err("Failed to enable CPPC on cpu%d (%d)\n", cpu, ret); + goto out; + } + + min_perf =3D cpu_data->perf_ctrls.min_perf ? + cpu_data->perf_ctrls.min_perf : caps->lowest_nonlinear_perf; + max_perf =3D cpu_data->perf_ctrls.max_perf ? + cpu_data->perf_ctrls.max_perf : caps->nominal_perf; + + ret =3D cppc_cpufreq_update_autosel_config(policy, min_perf, max_perf, t= rue, + CPPC_EPP_PERFORMANCE_PREF, true, false); + if (ret) { + cppc_set_enable(cpu, false); + goto out; + } + } else { + ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", + caps->highest_perf, cpu, ret); + goto out; + } } =20 cppc_cpufreq_cpu_fie_init(policy); @@ -910,7 +1015,6 @@ static int cppc_cpufreq_update_auto_select(struct cpuf= req_policy *policy, bool e struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; u64 min_perf =3D caps->lowest_nonlinear_perf; u64 max_perf =3D caps->nominal_perf; - int ret; =20 if (enable) { if (cpu_data->perf_ctrls.min_perf) @@ -919,26 +1023,8 @@ static int cppc_cpufreq_update_auto_select(struct cpu= freq_policy *policy, bool e max_perf =3D cpu_data->perf_ctrls.max_perf; } =20 - /* - * Set min/max performance registers and update policy constraints. - * When enabling: update both registers and policy. - * When disabling: update policy only. - * Continue even if min/max are not supported, as EPP and autosel - * might still be supported. - */ - ret =3D cppc_cpufreq_set_min_perf(policy, min_perf, enable, true); - if (ret && ret !=3D -EOPNOTSUPP) - return ret; - - ret =3D cppc_cpufreq_set_max_perf(policy, max_perf, enable, true); - if (ret && ret !=3D -EOPNOTSUPP) - return ret; - - ret =3D cppc_cpufreq_update_autosel_val(policy, enable); - if (ret) - return ret; - - return 0; + return cppc_cpufreq_update_autosel_config(policy, min_perf, max_perf, ena= ble, + 0, false, true); } =20 static ssize_t store_auto_select(struct cpufreq_policy *policy, const char= *buf, size_t count) @@ -1146,13 +1232,61 @@ static struct cpufreq_driver cppc_cpufreq_driver = =3D { .name =3D "cppc_cpufreq", }; =20 +static int cppc_cpufreq_set_epp_autosel_allcpus(bool auto_sel, u64 epp) +{ + int cpu, ret; + + for_each_present_cpu(cpu) { + ret =3D cppc_set_epp(cpu, epp); + if (ret) { + pr_warn("Failed to set EPP on CPU%d (%d)\n", cpu, ret); + goto disable_all; + } + + ret =3D cppc_set_auto_sel(cpu, auto_sel); + if (ret) { + pr_warn("Failed to set auto_sel on CPU%d (%d)\n", cpu, ret); + goto disable_all; + } + } + + return 0; + +disable_all: + pr_warn("Disabling auto_sel for all CPUs\n"); + for_each_present_cpu(cpu) + cppc_set_auto_sel(cpu, false); + + return -EIO; +} + static int __init cppc_cpufreq_init(void) { + bool auto_sel; int ret; =20 if (!acpi_cpc_valid()) return -ENODEV; =20 + if (auto_sel_mode) { + /* + * Check if autonomous selection is supported by testing CPU 0. + * If supported, enable autonomous mode on all CPUs. + */ + ret =3D cppc_get_auto_sel(0, &auto_sel); + if (!ret) { + pr_info("Enabling auto_sel_mode (autonomous selection mode)\n"); + ret =3D cppc_cpufreq_set_epp_autosel_allcpus(true, CPPC_EPP_PERFORMANCE= _PREF); + if (ret) { + pr_warn("Disabling auto_sel_mode, fallback to standard\n"); + auto_sel_mode =3D false; + } + } else { + pr_warn("Disabling auto_sel_mode as not supported by hardware\n"); + auto_sel_mode =3D false; + } + } + cppc_freq_invariance_init(); populate_efficiency_class(); =20 @@ -1165,10 +1299,19 @@ static int __init cppc_cpufreq_init(void) =20 static void __exit cppc_cpufreq_exit(void) { + int cpu; + + for_each_present_cpu(cpu) + cppc_set_auto_sel(cpu, false); + auto_sel_mode =3D false; + cpufreq_unregister_driver(&cppc_cpufreq_driver); cppc_freq_invariance_exit(); } =20 +module_param(auto_sel_mode, bool, 0000); +MODULE_PARM_DESC(auto_sel_mode, "Enable Autonomous Performance Level Selec= tion"); + module_exit(cppc_cpufreq_exit); MODULE_AUTHOR("Ashwin Chaugule"); MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec"); --=20 2.34.1