From nobody Fri Dec 19 12:49:50 2025 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7467D2FE07E; Wed, 5 Nov 2025 10:47:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762339658; cv=none; b=FnPmR0Xzznw7+uf+5/M5MHG56OoDK5IN12rgoNe/MDtriGOU7NhP7Lk9pb71nh+vF//PFnaAE2wn4AjdaGsxxSK1lgKgm53qxZ0ScJg+IKuBe8NS+by3t4LdhsmTEDMeUJnOFbszEzDhJYb2b6iREqAkVPPItIQaYiyO1s4Ryac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762339658; c=relaxed/simple; bh=XmoQEQ1GMUWXe7hZ/qA/Xg7/tQOkkXFD5SrI+kAAYig=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kSBXhwyEPHpCU3YAXSJZkJtEvt2G2aSPlNOGmd6UcuCh2k+A/agU2t01wO/E6HlkDJhmMCeMFujzYqBiKDGnCY+LMCtQ1usbMuE7n1VkhivONIJB3TIcXET2haUyWs8hoBjSpd+B7C53DjGgyB+SXPWI3o97pKwF7BGuop7b+WU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=QiIejDhH; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="QiIejDhH" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 5A5AiryvF984688, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1762339493; bh=GnvBMbFkvZYykLflO+/i2R2OdGZTHjqgnwGqTxuE31g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=QiIejDhH4goNqRddsNEcgqHuYekG9eVTl6H1smb9+AsZU86SiWu7kmFLyWAqziHEh 7WPGHTSJ8v3TdLuKjrA0n08vUEiJyuEQL+P6umPokqmw8ij4AwsrMcJlcn2DM8RtRS DYO3Yzhhg3/51xHpJ5I9ph6eVqTcYSj98rPtNEKpdCECImmnNeWBIaVg3D8q0Iluac 94cOMf0t73rc6jR2wLz8I0CK42nhCZdvWlERFY8kwMBWg7VW8krZ9VbzGfDj1zP/+r ozuOPgFXoyDNRhxuOa0H+RBJNygiSlOC0LScrAuNCcZGrM15fSQa96e8wAx2bQUdQA Pn+0Byren1kIA== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.13/5.93) with ESMTPS id 5A5AiryvF984688 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 5 Nov 2025 18:44:53 +0800 Received: from RTKEXHMBS01.realtek.com.tw (172.21.6.40) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.27; Wed, 5 Nov 2025 18:44:53 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS01.realtek.com.tw (172.21.6.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.27; Wed, 5 Nov 2025 18:44:52 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1544.27 via Frontend Transport; Wed, 5 Nov 2025 18:44:52 +0800 From: Yu-Chun Lin To: , , , , , CC: , , , , , , Subject: [PATCH 1/3] dt-bindings: arm: realtek: Add Kent Soc family compatibles Date: Wed, 5 Nov 2025 18:44:50 +0800 Message-ID: <20251105104452.6336-2-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251105104452.6336-1-eleanor.lin@realtek.com> References: <20251105104452.6336-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define compatible strings for Realtek RTD1501s, RTD1861b and RTD1920s. Additionally, convert legacy DTS-style comments to YAML description properties, following the pattern from the ARM bindings conversion series [1]. [1] https://lore.kernel.org/lkml/20200622125527.24207-2-afaerber@suse.de/ Signed-off-by: Yu-Chun Lin --- .../devicetree/bindings/arm/realtek.yaml | 43 +++++++++++++------ 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documenta= tion/devicetree/bindings/arm/realtek.yaml index ddd9a85099e9..9eed94ea4c8d 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -14,21 +14,21 @@ properties: const: '/' compatible: oneOf: - # RTD1195 SoC based boards - - items: + - description: RTD1195 SoC based boards + items: - enum: - mele,x1000 # MeLE X1000 - realtek,horseradish # Realtek Horseradish EVB - const: realtek,rtd1195 =20 - # RTD1293 SoC based boards - - items: + - description: RTD1293 SoC based boards + items: - enum: - synology,ds418j # Synology DiskStation DS418j - const: realtek,rtd1293 =20 - # RTD1295 SoC based boards - - items: + - description: RTD1295 SoC based boards + items: - enum: - mele,v9 # MeLE V9 - probox2,ava # ProBox2 AVA @@ -36,25 +36,44 @@ properties: - zidoo,x9s # Zidoo X9S - const: realtek,rtd1295 =20 - # RTD1296 SoC based boards - - items: + - description: RTD1296 SoC based boards + items: - enum: - synology,ds418 # Synology DiskStation DS418 - const: realtek,rtd1296 =20 - # RTD1395 SoC based boards - - items: + - description: RTD1395 SoC based boards + items: - enum: - bananapi,bpi-m4 # Banana Pi BPI-M4 - realtek,lion-skin # Realtek Lion Skin EVB - const: realtek,rtd1395 =20 - # RTD1619 SoC based boards - - items: + - description: RTD1501s SoC based boards + items: + - enum: + - realtek,phantom # Realtek Phantom EVB (8GB) + - const: realtek,rtd1501s + + - description: RTD1619 SoC based boards + items: - enum: - realtek,mjolnir # Realtek Mjolnir EVB - const: realtek,rtd1619 =20 + - description: RTD1861b SoC based boards + items: + - enum: + - realtek,krypton # Realtek Krypton EVB (8GB) + - const: realtek,rtd1861b + + - description: RTD1920s SoC based boards + items: + - enum: + - realtek,smallville # Realtek Smallville EVB (4GB) + - const: realtek,rtd1920s + + additionalProperties: true =20 ... --=20 2.34.1 From nobody Fri Dec 19 12:49:50 2025 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAEA8305957; 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Wed, 5 Nov 2025 18:44:53 +0800 Received: from RTKEXHMBS01.realtek.com.tw (172.21.6.40) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.27; Wed, 5 Nov 2025 18:44:53 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS01.realtek.com.tw (172.21.6.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.27; Wed, 5 Nov 2025 18:44:53 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1544.27 via Frontend Transport; Wed, 5 Nov 2025 18:44:52 +0800 From: Yu-Chun Lin To: , , , , , CC: , , , , , , Subject: [PATCH 2/3] dt-bindings: mfd: Add Realtek ISO system controller Date: Wed, 5 Nov 2025 18:44:51 +0800 Message-ID: <20251105104452.6336-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251105104452.6336-1-eleanor.lin@realtek.com> References: <20251105104452.6336-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT binding schema for Realtek system controller. Signed-off-by: Yu-Chun Lin --- .../bindings/mfd/realtek,iso-system.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/realtek,iso-syste= m.yaml diff --git a/Documentation/devicetree/bindings/mfd/realtek,iso-system.yaml = b/Documentation/devicetree/bindings/mfd/realtek,iso-system.yaml new file mode 100644 index 000000000000..6fbdedd3ee5b --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/realtek,iso-system.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/realtek,iso-system.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek ISO System Controller + +description: | + The Realtek ISO System Controller is a register area that contains + miscellaneous system registers for the SoC and serves as a parent node + for other functions. + +maintainers: + - James Tai + - Yu-Chun Lin + +properties: + compatible: + items: + - enum: + - realtek,iso-system + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + ranges: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + reg-io-width: + const: 4 + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + description: Catch-all for other sub-devices in the ISO area. + +required: + - compatible + - reg + - ranges + - '#address-cells' + - '#size-cells' + - reg-io-width + +additionalProperties: false + +examples: + - | + iso: syscon@7000 { + compatible =3D "realtek,iso-system", "syscon", "simple-mfd"; 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Wed, 5 Nov 2025 18:44:53 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1544.27 via Frontend Transport; Wed, 5 Nov 2025 18:44:53 +0800 From: Yu-Chun Lin To: , , , , , CC: , , , , , , Subject: [PATCH 3/3] arm64: dts: realtek: Add Kent SoC and EVB device trees Date: Wed, 5 Nov 2025 18:44:52 +0800 Message-ID: <20251105104452.6336-4-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251105104452.6336-1-eleanor.lin@realtek.com> References: <20251105104452.6336-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Device Tree hierarchy for Realtek Kent SoC family: - kent.dtsi: base SoC layer - rtd.dtsi: SoC variant layer - rtd-.dtsi: board layer - rtd--.dts: board configuration layer Include RTD1501S Phantom EVB (8GB), RTD1861B Krypton EVB (8GB), and RTD1920S Smallville EVB (4GB). Signed-off-by: Yu-Chun Lin --- arch/arm64/boot/dts/realtek/Makefile | 5 + arch/arm64/boot/dts/realtek/kent.dtsi | 179 ++++++++++++++++++ arch/arm64/boot/dts/realtek/rtd1501.dtsi | 13 ++ .../boot/dts/realtek/rtd1501s-phantom-8gb.dts | 26 +++ .../boot/dts/realtek/rtd1501s-phantom.dtsi | 135 +++++++++++++ arch/arm64/boot/dts/realtek/rtd1861.dtsi | 13 ++ .../boot/dts/realtek/rtd1861b-krypton-8gb.dts | 26 +++ .../boot/dts/realtek/rtd1861b-krypton.dtsi | 79 ++++++++ arch/arm64/boot/dts/realtek/rtd1920.dtsi | 13 ++ .../dts/realtek/rtd1920s-smallville-4gb.dts | 24 +++ .../boot/dts/realtek/rtd1920s-smallville.dtsi | 145 ++++++++++++++ 11 files changed, 658 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/kent.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1501.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1861.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1920.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/rea= ltek/Makefile index ef8d8fcbaa05..0ef0596681ad 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -13,3 +13,8 @@ dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1395-bpi-m4.dtb dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1395-lionskin.dtb =20 dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1619-mjolnir.dtb + +dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1501s-phantom-8gb.dtb +dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1861b-krypton-8gb.dtb +dtb-$(CONFIG_ARCH_REALTEK) +=3D rtd1920s-smallville-4gb.dtb + diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/re= altek/kent.dtsi new file mode 100644 index 000000000000..6af3efa0bda4 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek Kent SoC family + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + }; + + arch_timer: arch-timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + dynamic-power-coefficient =3D <454>; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + dynamic-power-coefficient =3D <454>; + #cooling-cells =3D <2>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + dynamic-power-coefficient =3D <454>; + #cooling-cells =3D <2>; + + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_3>; + dynamic-power-coefficient =3D <454>; + #cooling-cells =3D <2>; + + l2_3: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3>; + }; + }; + + l3: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <0x00200000>; + cache-unified; + }; + }; + + psci: psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00000000 0x00000000 0x00000000 0x00040000>, /* boot code */ + <0x98000000 0x00000000 0x98000000 0x00ef0000>, /* reg-bus */ + <0xa0000000 0x00000000 0xa0000000 0x10000000>, /* PCIE */ + <0xff000000 0x00000000 0xff000000 0x00200000>; /* GIC */ + + rbus: reg-bus@98000000 { + compatible =3D "simple-bus"; + reg =3D <0x98000000 0x00ef0000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00000000 0x98000000 0x00ef0000>, + <0xa0000000 0xa0000000 0x10000000>; /* PCIE */ + + iso: syscon@7000 { + compatible =3D "realtek,iso-system", "syscon", "simple-mfd"; + reg =3D <0x7000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x7000 0x1000>; + reg-io-width =3D <4>; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible =3D "arm,gic-v3"; + reg =3D <0xff100000 0x10000>, + <0xff140000 0x80000>; + interrupt-controller; + interrupts =3D ; + #address-cells =3D <1>; + #interrupt-cells =3D <3>; + #size-cells =3D <1>; + }; + }; +}; + +&iso { + uart0: serial@800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x800 0x100>; + clock-frequency =3D <432000000>; + interrupts =3D ; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1501.dtsi b/arch/arm64/boot/dts= /realtek/rtd1501.dtsi new file mode 100644 index 000000000000..1df5d9843505 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1501 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status =3D "okay"; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts b/arch/ar= m64/boot/dts/realtek/rtd1501s-phantom-8gb.dts new file mode 100644 index 000000000000..b0e03f3731e2 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1501S Phantom EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1501s-phantom.dtsi" + +/ { + compatible =3D "realtek,phantom", "realtek,rtd1501s"; + model =3D "Realtek Phantom EVB Chromium (8GB)"; + + memory: memory@40000 { + device_type =3D "memory"; + reg =3D <0x00000000 0x00050000 0x00000000 0x7ffb0000>, + <0x00000000 0x8a100000 0x00000000 0x0def0000>, + <0x00000000 0x98700000 0x00000000 0x07900000>, + <0x00000000 0xa0600000 0x00000000 0x5ea00000>, + <0x00000001 0x00000000 0x00000000 0xa0000000>, + <0x00000001 0xa0600000 0x00000000 0x5fa00000>; + }; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi b/arch/arm64= /boot/dts/realtek/rtd1501s-phantom.dtsi new file mode 100644 index 000000000000..bf1e499addf9 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1501S Phantom EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include +#include "rtd1501.dtsi" + +/ { + chosen { + bootargs =3D "earlycon=3Duart8250,mmio32,0x98007800 + console=3DttyS0,460800 8250.nr_uarts=3D2 init=3D/init + loglevel=3D8 max_loop=3D64 loop.max_part=3D7 + firmware_class.path=3D/vendor/firmware/,/vendor/av_fw"; + stdout-path =3D "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + alignment =3D <0x0 0x00400000>; + alloc-ranges =3D <0x0 0x00000000 0x0 0x20000000>; + size =3D <0x0 0x02000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp800: opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <830000 830000 1100000>; + status =3D "okay"; + }; + + opp900: opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <850000 850000 1100000>; + status =3D "okay"; + }; + + opp1000: opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <870000 870000 1100000>; + status =3D "okay"; + }; + + opp1100: opp-1100000000 { + opp-hz =3D /bits/ 64 <1100000000>; + opp-microvolt =3D <890000 890000 1100000>; + status =3D "okay"; + }; + + opp1200: opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <910000 910000 1100000>; + status =3D "okay"; + }; + + opp1300: opp-1300000000 { + opp-hz =3D /bits/ 64 <1300000000>; + opp-microvolt =3D <930000 930000 1100000>; + status =3D "okay"; + }; + + opp1400: opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-microvolt =3D <950000 950000 1100000>; + status =3D "okay"; + }; + + opp1500: opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <970000 970000 1100000>; + status =3D "okay"; + }; + + opp1600: opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <990000 990000 1100000>; + opp-suspend; + status =3D "okay"; + }; + + opp1700: opp-1700000000 { + opp-hz =3D /bits/ 64 <1700000000>; + opp-microvolt =3D <1010000 1010000 1100000>; + status =3D "okay"; + }; + + opp1800: opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1030000 1030000 1100000>; + status =3D "okay"; + }; + + opp1900: opp-1900000000 { + opp-hz =3D /bits/ 64 <1900000000>; + opp-microvolt =3D <1050000 1050000 1100000>; + status =3D "okay"; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu1 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu2 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu3 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1861.dtsi b/arch/arm64/boot/dts= /realtek/rtd1861.dtsi new file mode 100644 index 000000000000..e9b1b85c7a63 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1861 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status =3D "okay"; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts b/arch/ar= m64/boot/dts/realtek/rtd1861b-krypton-8gb.dts new file mode 100644 index 000000000000..c36b485e8c5f --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1861B Krypton EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1861b-krypton.dtsi" + +/ { + compatible =3D "realtek,krypton", "realtek,rtd1861b"; + model =3D "Realtek Krypton EVB (8GB)"; + + memory: memory@40000 { + device_type =3D "memory"; + reg =3D <0x00000000 0x00050000 0x00000000 0x7ffb0000>, + <0x00000000 0x8a100000 0x00000000 0x0def0000>, + <0x00000000 0x98700000 0x00000000 0x07900000>, + <0x00000000 0xa0600000 0x00000000 0x5ea00000>, + <0x00000001 0x00000000 0x00000000 0xa0000000>, + <0x00000001 0xa0600000 0x00000000 0x5fa00000>; + }; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi b/arch/arm64= /boot/dts/realtek/rtd1861b-krypton.dtsi new file mode 100644 index 000000000000..acf9066a7d98 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1861B Krypton EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1861.dtsi" + +/ { + chosen { + bootargs =3D "earlycon=3Duart8250,mmio32,0x98007800 console=3DttyS0,4608= 00 8250.nr_uarts=3D1 + 8250.share_irqs=3D1 init=3D/init loglevel=3D8 max_loop=3D64 loop.ma= x_part=3D7 + firmware_class.path=3D/vendor/firmware/,/vendor/av_fw"; + stdout-path =3D "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + alignment =3D <0x0 0x00400000>; + alloc-ranges =3D <0x0 0x00000000 0x0 0x20000000>; + size =3D <0x0 0x02000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp1200: opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <900000>; + status =3D "okay"; + }; + + opp1600: opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <1000000>; + opp-suspend; + status =3D "okay"; + }; + + opp1800: opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1050000>; + status =3D "okay"; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu1 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu2 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu3 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1920.dtsi b/arch/arm64/boot/dts= /realtek/rtd1920.dtsi new file mode 100644 index 000000000000..ffefde9749a1 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1920 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status =3D "okay"; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts b/arch= /arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts new file mode 100644 index 000000000000..2c8296018e68 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1920S Smallville EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1920s-smallville.dtsi" + +/ { + compatible =3D "realtek,smallville", "realtek,rtd1920s"; + model =3D "Realtek Smallville EVB (4GB)"; + + memory: memory@40000 { + device_type =3D "memory"; + reg =3D <0x00000000 0x00050000 0x00000000 0x7ffb0000>, + <0x00000000 0x8a100000 0x00000000 0x0def0000>, + <0x00000000 0x98700000 0x00000000 0x07900000>, + <0x00000000 0xa1000000 0x00000000 0x5e000000>; + }; +}; + diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi b/arch/ar= m64/boot/dts/realtek/rtd1920s-smallville.dtsi new file mode 100644 index 000000000000..75d29591b9fa --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1920S Smallville EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include +#include "rtd1920.dtsi" + +/ { + chosen { + bootargs =3D "earlycon=3Duart8250,mmio32,0x98007800 + console=3DttyS0,460800 8250.nr_uarts=3D11 8250.share_irqs=3D1 + init=3D/init loglevel=3D8 max_loop=3D64 loop.max_part=3D7 + firmware_class.path=3D/vendor/firmware/,/vendor/av_fw"; + stdout-path =3D "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + protected_mem: protected-mem@50000 { + reg =3D <0x0 0x00050000 0x0 0x00bf0000>; + no-map; + }; + + metadata: metadata@c40000 { + reg =3D <0x0 0x00c40000 0x0 0x003c4000>; + no-map; + }; + + linux,cma { + compatible =3D "shared-dma-pool"; + alignment =3D <0x0 0x00400000>; + alloc-ranges =3D <0x0 0x00000000 0x0 0x20000000>; + size =3D <0x0 0x02000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp800: opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <830000 830000 1100000>; + status =3D "okay"; + }; + + opp900: opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <850000 850000 1100000>; + status =3D "okay"; + }; + + opp1000: opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <870000 870000 1100000>; + status =3D "okay"; + }; + + opp1100: opp-1100000000 { + opp-hz =3D /bits/ 64 <1100000000>; + opp-microvolt =3D <890000 890000 1100000>; + status =3D "okay"; + }; + + opp1200: opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <910000 910000 1100000>; + status =3D "okay"; + }; + + opp1300: opp-1300000000 { + opp-hz =3D /bits/ 64 <1300000000>; + opp-microvolt =3D <930000 930000 1100000>; + status =3D "okay"; + }; + + opp1400: opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-microvolt =3D <950000 950000 1100000>; + status =3D "okay"; + }; + + opp1500: opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <970000 970000 1100000>; + status =3D "okay"; + }; + + opp1600: opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <990000 990000 1100000>; + opp-suspend; + status =3D "okay"; + }; + + opp1700: opp-1700000000 { + opp-hz =3D /bits/ 64 <1700000000>; + opp-microvolt =3D <1010000 1010000 1100000>; + status =3D "okay"; + }; + + opp1800: opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1030000 1030000 1100000>; + status =3D "okay"; + }; + + opp1900: opp-1900000000 { + opp-hz =3D /bits/ 64 <1900000000>; + opp-microvolt =3D <1050000 1050000 1100000>; + status =3D "okay"; + }; + }; +}; + +&cpu0 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu1 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu2 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + +&cpu3 { + operating-points-v2 =3D <&cpu_opps>; + #cooling-cells =3D <2>; +}; + --=20 2.34.1