From nobody Fri Dec 19 14:37:43 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 78B01307AE3; Wed, 5 Nov 2025 10:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762339415; cv=none; b=Zk66h7KRLVXPG2uNmVkuMiTrr/DofbK1MU+KHj+tsczek9t77JgyLX9cGihM7az8hX7p7vpbOYKgn+RBAp22bxL/ySictUYwB72OUZejBg3terJrG/hODDfCMRk1SKB5eaWwoLPlyqfAlWPTbMYZZssoKyQo4MEP1/8CQ5Pe8uU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762339415; c=relaxed/simple; bh=tGxHwADi5ufjYK4AqVUI1K6k1hsgUmIJgmE9xlatDSY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bC1z6sAg6WfydKznMZHGfmfVS9cZEgZ0qmoWKjLw1EDMOBOW+KBhk803FWY6iMEhQv/mO6flASGmRdhqUBoW+fvS3YV1fgnckzkpF55grnATqjrt3++jHe9SPSucI4X4qrBEamJL9w3qcqXv7frJkvkXn2CLfyZiAK+m/Lt+4uI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: XeCu1/GCRPqy5abtrZwxlQ== X-CSE-MsgGUID: 7PMRG9SSTseuKuAGAwuNkw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 05 Nov 2025 19:43:32 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.82]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id EBDF64001DCB; Wed, 5 Nov 2025 19:43:27 +0900 (JST) From: Cosmin Tanislav To: Fabrizio Castro , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: linux-spi@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v3 07/14] spi: rzv2h-rspi: make transfer clock rate finding chip-specific Date: Wed, 5 Nov 2025 12:41:44 +0200 Message-ID: <20251105104151.1489281-8-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251105104151.1489281-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251105104151.1489281-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a more complicated clocking setup for the SPI transfer clock than RZ/V2H, as the clock from which it is generated supports multiple dividers. To prepare for adding support for these SoCs, split out the logic for finding the SPR and BRDV for a fixed clock into rzv2h_rspi_find_rate_fixed(), and add and use a .find_tclk_rate() callback into the chip-specific structure. Signed-off-by: Cosmin Tanislav --- drivers/spi/spi-rzv2h-rspi.c | 62 ++++++++++++++++++++++++++++++------ 1 file changed, 53 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c index d7719f3c7b13..f59bcadf5e38 100644 --- a/drivers/spi/spi-rzv2h-rspi.c +++ b/drivers/spi/spi-rzv2h-rspi.c @@ -67,7 +67,18 @@ =20 #define RSPI_RESET_NUM 2 =20 +struct rzv2h_rspi_best_clock { + struct clk *clk; + unsigned long clk_rate; + unsigned long error; + u32 actual_hz; + u8 brdv; + u8 spr; +}; + struct rzv2h_rspi_info { + void (*find_tclk_rate)(struct clk *clk, u32 hz, u8 spr_min, u8 spr_max, + struct rzv2h_rspi_best_clock *best_clk); const char *tclk_name; unsigned int fifo_size; unsigned int num_clks; @@ -240,9 +251,13 @@ static inline u32 rzv2h_rspi_calc_bitrate(unsigned lon= g tclk_rate, u8 spr, return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv))); } =20 -static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz) +static void rzv2h_rspi_find_rate_fixed(struct clk *clk, u32 hz, + u8 spr_min, u8 spr_max, + struct rzv2h_rspi_best_clock *best) { - unsigned long tclk_rate; + unsigned long clk_rate; + unsigned long error; + u32 actual_hz; int spr; u8 brdv; =20 @@ -255,21 +270,49 @@ static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_p= riv *rspi, u32 hz) * * n =3D SPR - is RSPI_SPBR.SPR (from 0 to 255) * * N =3D BRDV - is RSPI_SPCMD.BRDV (from 0 to 3) */ - tclk_rate =3D clk_get_rate(rspi->tclk); + clk_rate =3D clk_get_rate(clk); for (brdv =3D RSPI_SPCMD_BRDV_MIN; brdv <=3D RSPI_SPCMD_BRDV_MAX; brdv++)= { - spr =3D DIV_ROUND_UP(tclk_rate, hz * (1 << (brdv + 1))); + spr =3D DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1))); spr--; - if (spr >=3D RSPI_SPBR_SPR_MIN && spr <=3D RSPI_SPBR_SPR_MAX) + if (spr >=3D spr_min && spr <=3D spr_max) goto clock_found; } =20 - return 0; + return; =20 clock_found: - rspi->spr =3D spr; - rspi->brdv =3D brdv; + actual_hz =3D rzv2h_rspi_calc_bitrate(clk_rate, spr, brdv); + error =3D abs((long)hz - (long)actual_hz); =20 - return rzv2h_rspi_calc_bitrate(tclk_rate, spr, brdv); + if (error >=3D best->error) + return; + + *best =3D (struct rzv2h_rspi_best_clock) { + .clk =3D clk, + .clk_rate =3D clk_rate, + .error =3D error, + .actual_hz =3D actual_hz, + .brdv =3D brdv, + .spr =3D spr, + }; +} + +static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz) +{ + struct rzv2h_rspi_best_clock best_clock =3D { + .error =3D ULONG_MAX, + }; + + rspi->info->find_tclk_rate(rspi->tclk, hz, RSPI_SPBR_SPR_MIN, + RSPI_SPBR_SPR_MAX, &best_clock); + + if (!best_clock.clk_rate) + return -EINVAL; + + rspi->spr =3D best_clock.spr; + rspi->brdv =3D best_clock.brdv; + + return best_clock.actual_hz; } =20 static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr, @@ -463,6 +506,7 @@ static void rzv2h_rspi_remove(struct platform_device *p= dev) } =20 static const struct rzv2h_rspi_info rzv2h_info =3D { + .find_tclk_rate =3D rzv2h_rspi_find_rate_fixed, .tclk_name =3D "tclk", .fifo_size =3D 16, .num_clks =3D 3, --=20 2.51.2