From nobody Fri Dec 19 14:37:44 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 597BA306497; Wed, 5 Nov 2025 10:43:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762339393; cv=none; b=iXd26UfARfLPppTHnkM4VKWfozq8D2Nb7Ou1jRxmXruKrBIzsTCv7MWNB3WGXuGO2gTBXvTVKVvLh611A+JnfupBg/QolyfiLflvw9n+n8JHuToaQGzdLvI+Ebm5PmzJtsTmmsTHX8peFJBP9++n0DQ0juHF7qdvVB6IlG7KO0Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762339393; c=relaxed/simple; bh=1u4fEjtbPiVf/1eUodFOVHHRdMyGMiZUk1LvcM7ZKL8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MCFTTzZIfRz9OHMVBeuobTVouD6Kr0acOimTtTq0rIZ2yd+HnKxTyhjoX28lD+x6TKnfHqFuMEG53xQ5yJmqn85A5u6A23Q+9t68hkIHTAwyMLR0XnCwaNQ33YEq82c+0rc0zUfrXjNs6ozA/11BB6+gZoo//M/DoEcyO6gaUlc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: 8flgLxuGRJeN9/zw57vsCA== X-CSE-MsgGUID: MdL4wZ+DSK6md+ajUPZi8Q== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 05 Nov 2025 19:43:09 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.82]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3D8814001DCB; Wed, 5 Nov 2025 19:43:03 +0900 (JST) From: Cosmin Tanislav To: Fabrizio Castro , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: linux-spi@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v3 03/14] spi: rzv2h-rspi: make FIFO size chip-specific Date: Wed, 5 Nov 2025 12:41:40 +0200 Message-ID: <20251105104151.1489281-4-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251105104151.1489281-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251105104151.1489281-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a different FIFO size compared to RZ/V2H. Add a chip-specific structure, and set the FIFO size inside it, to prepare for adding support for them. Signed-off-by: Cosmin Tanislav --- drivers/spi/spi-rzv2h-rspi.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c index 09b9362e9b1f..7a7a576c17dd 100644 --- a/drivers/spi/spi-rzv2h-rspi.c +++ b/drivers/spi/spi-rzv2h-rspi.c @@ -58,7 +58,6 @@ /* Register SPDCR2 */ #define RSPI_SPDCR2_TTRG GENMASK(11, 8) #define RSPI_SPDCR2_RTRG GENMASK(3, 0) -#define RSPI_FIFO_SIZE 16 =20 /* Register SPSR */ #define RSPI_SPSR_SPRF BIT(15) @@ -69,9 +68,14 @@ #define RSPI_RESET_NUM 2 #define RSPI_CLK_NUM 3 =20 +struct rzv2h_rspi_info { + unsigned int fifo_size; +}; + struct rzv2h_rspi_priv { struct reset_control_bulk_data resets[RSPI_RESET_NUM]; struct spi_controller *controller; + const struct rzv2h_rspi_info *info; void __iomem *base; struct clk *tclk; wait_queue_head_t wait; @@ -305,7 +309,7 @@ static int rzv2h_rspi_prepare_message(struct spi_contro= ller *ctlr, writeb(0, rspi->base + RSPI_SSLP); =20 /* Setup FIFO thresholds */ - conf16 =3D FIELD_PREP(RSPI_SPDCR2_TTRG, RSPI_FIFO_SIZE - 1); + conf16 =3D FIELD_PREP(RSPI_SPDCR2_TTRG, rspi->info->fifo_size - 1); conf16 |=3D FIELD_PREP(RSPI_SPDCR2_RTRG, 0); writew(conf16, rspi->base + RSPI_SPDCR2); =20 @@ -362,6 +366,8 @@ static int rzv2h_rspi_probe(struct platform_device *pde= v) =20 rspi->controller =3D controller; =20 + rspi->info =3D device_get_match_data(dev); + rspi->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rspi->base)) return PTR_ERR(rspi->base); @@ -445,8 +451,12 @@ static void rzv2h_rspi_remove(struct platform_device *= pdev) reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets); } =20 +static const struct rzv2h_rspi_info rzv2h_info =3D { + .fifo_size =3D 16, +}; + static const struct of_device_id rzv2h_rspi_match[] =3D { - { .compatible =3D "renesas,r9a09g057-rspi" }, + { .compatible =3D "renesas,r9a09g057-rspi", &rzv2h_info }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzv2h_rspi_match); --=20 2.51.2