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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF0000231A.mail.protection.outlook.com (10.167.242.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Tue, 4 Nov 2025 17:07:38 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 4 Nov 2025 09:07:37 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 24/25] CXL/PCI: Enable CXL protocol errors during CXL Port probe Date: Tue, 4 Nov 2025 11:03:04 -0600 Message-ID: <20251104170305.4163840-25-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|SA5PPFE494AA682:EE_ X-MS-Office365-Filtering-Correlation-Id: 995a63d4-ce9d-4966-8ad2-08de1bc4a87a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:07:38.5986 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 995a63d4-ce9d-4966-8ad2-08de1bc4a87a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFE494AA682 Content-Type: text/plain; charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. These must be enabled inorder to process CXL protocol errors. Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_err= ors(). pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized. But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable A= ER correctable internal errors and uncorrectable internal errors for all CXL devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham --- Changes in v12->v13: - Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Te= rry) - Add Dave Jiang's and Ben's review-by Changes in v11->v12: - None Changes in v10->v11: - Added check for valid PCI devices in is_cxl_error() (Terry) - Removed check for RCiEP in cxl_handle_proto_err() and cxl_report_error_detected() (Terry) --- drivers/cxl/core/core.h | 4 ++++ drivers/cxl/core/port.c | 4 ++++ drivers/cxl/core/ras.c | 26 +++++++++++++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 046ec65ed147..a7a0838c8f23 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -159,6 +159,8 @@ pci_ers_result_t pci_error_detected(struct pci_dev *pde= v, void pci_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_port_error_detected(struct device *dev); void cxl_port_cor_error_detected(struct device *dev); +void cxl_mask_proto_interrupts(struct device *dev); +void cxl_unmask_proto_interrupts(struct device *dev); #else static inline int cxl_ras_init(void) { @@ -183,6 +185,8 @@ static inline pci_ers_result_t cxl_port_error_detected(= struct device *dev) { return PCI_ERS_RESULT_NONE; } +static inline void cxl_unmask_proto_interrupts(struct device *dev) { } +static inline void cxl_mask_proto_interrupts(struct device *dev) { } #endif /* CONFIG_CXL_RAS */ =20 /* Restricted CXL Host specific RAS functions */ diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index d060f864cf2e..a23c742eb670 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1747,6 +1747,8 @@ static int add_port_attach_ep(struct cxl_memdev *cxlm= d, rc =3D -ENXIO; } =20 + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); + return rc; } =20 @@ -1833,6 +1835,8 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) =20 rc =3D cxl_add_ep(dport, &cxlmd->dev); =20 + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); + /* * If the endpoint already exists in the port's list, * that's ok, it was added on a previous pass. diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 52c6f19564b6..101e55723785 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -122,6 +122,23 @@ static bool is_pcie_endpoint(struct pci_dev *pdev) return pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT; } =20 +void cxl_unmask_proto_interrupts(struct device *dev) +{ + if (!dev || !dev_is_pci(dev)) + return; + + struct pci_dev *pdev __free(pci_dev_put) =3D pci_dev_get(to_pci_dev(dev)); + + if (!pdev->aer_cap) { + pdev->aer_cap =3D pci_find_ext_capability(pdev, + PCI_EXT_CAP_ID_ERR); + if (!pdev->aer_cap) + return; + } + + pci_aer_unmask_internal_errors(pdev); +} + static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -230,7 +247,10 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) =20 cxl_dport_map_rch_aer(dport); cxl_disable_rch_root_ints(dport); + return; } + + cxl_unmask_proto_interrupts(dport->dport_dev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 @@ -241,8 +261,12 @@ void cxl_uport_init_ras_reporting(struct cxl_port *por= t, =20 map->host =3D host; if (cxl_map_component_regs(map, &port->uport_regs, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(&port->dev, "Failed to map RAS capability\n"); + return; + } + + cxl_unmask_proto_interrupts(port->uport_dev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); =20 --=20 2.34.1