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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB73.mail.protection.outlook.com (10.167.242.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Tue, 4 Nov 2025 17:06:21 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 4 Nov 2025 09:06:20 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 17/25] cxl: Introduce cxl_pci_drv_bound() to check for bound driver Date: Tue, 4 Nov 2025 11:02:57 -0600 Message-ID: <20251104170305.4163840-18-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|CH3PR12MB9730:EE_ X-MS-Office365-Filtering-Correlation-Id: 18aada6c-8811-4b1d-85c9-08de1bc47a41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:06:21.1411 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18aada6c-8811-4b1d-85c9-08de1bc47a41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9730 Content-Type: text/plain; charset="utf-8" CXL devices handle protocol errors via driver-specific callbacks rather than the generic pci_driver::err_handlers by default. The callbacks are implemented in the cxl_pci driver and are not part of struct pci_driver, so cxl_core must verify that a device is actually bound to the cxl_pci module's driver before invoking the callbacks (the device could be bound to another driver, e.g. VFIO). However, cxl_core can not reference symbols in the cxl_pci module because it creates a circular dependency. This prevents cxl_core from checking the EP's bound driver and calling the callbacks. To fix this, move drivers/cxl/pci.c into drivers/cxl/core/pci_drv.c and build it as part of the cxl_core module. Compile into cxl_core using CXL_PCI and CXL_CORE Kconfig dependencies. This removes the standalone cxl_pci module, consolidates the cxl_pci driver code into cxl_core, and eliminates the circular dependency so cxl_core can safely perform bound-driver checks and invoke the CXL PCI callbacks. Introduce cxl_pci_drv_bound() to return boolean depending on if the PCI EP parameter is bound to a CXL driver instance. This will be used in future patch when dequeuing work from the kfifo. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham Reviewed-by: Jonathan Cameron --- Changes in v12->v13; - Add Dave Jiang's review-by. Changes in v11->v12: - Add device_lock_assert() in cxl_pci_drv_bound() (Dave Jiang) - Add Jonathan's review-by Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/cxl/Kconfig | 6 +++--- drivers/cxl/Makefile | 2 -- drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 9 +++++++++ drivers/cxl/{pci.c =3D> core/pci_drv.c} | 21 +++++++++++++-------- drivers/cxl/core/port.c | 3 +++ tools/testing/cxl/Kbuild | 1 + 7 files changed, 30 insertions(+), 13 deletions(-) rename drivers/cxl/{pci.c =3D> core/pci_drv.c} (99%) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index ffe6ad981434..360c78fa7e97 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -20,7 +20,7 @@ menuconfig CXL_BUS if CXL_BUS =20 config CXL_PCI - tristate "PCI manageability" + bool "PCI manageability" default CXL_BUS help The CXL specification defines a "CXL memory device" sub-class in the @@ -29,12 +29,12 @@ config CXL_PCI memory to be mapped into the system address map (Host-managed Device Memory (HDM)). =20 - Say 'y/m' to enable a driver that will attach to CXL memory expander + Say 'y' to enable a driver that will attach to CXL memory expander devices enumerated by the memory device class code for configuration and management primarily via the mailbox interface. See Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more details. =20 - If unsure say 'm'. + If unsure say 'y'. =20 config CXL_MEM_RAW_COMMANDS bool "RAW Command Interface for Memory Devices" diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index 2caa90fa4bf2..ff6add88b6ae 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -12,10 +12,8 @@ obj-$(CONFIG_CXL_PORT) +=3D cxl_port.o obj-$(CONFIG_CXL_ACPI) +=3D cxl_acpi.o obj-$(CONFIG_CXL_PMEM) +=3D cxl_pmem.o obj-$(CONFIG_CXL_MEM) +=3D cxl_mem.o -obj-$(CONFIG_CXL_PCI) +=3D cxl_pci.o =20 cxl_port-y :=3D port.o cxl_acpi-y :=3D acpi.o cxl_pmem-y :=3D pmem.o security.o cxl_mem-y :=3D mem.o -cxl_pci-y :=3D pci.o diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index fa1d4aed28b9..2937d0ddcce2 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -21,3 +21,4 @@ cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o cxl_core-$(CONFIG_CXL_RAS) +=3D ras.o cxl_core-$(CONFIG_CXL_RCH_RAS) +=3D ras_rch.o +cxl_core-$(CONFIG_CXL_PCI) +=3D pci_drv.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index e47ae7365ce0..61c6726744d7 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -195,4 +195,13 @@ int cxl_set_feature(struct cxl_mailbox *cxl_mbox, cons= t uuid_t *feat_uuid, u16 *return_code); #endif =20 +#ifdef CONFIG_CXL_PCI +bool cxl_pci_drv_bound(struct pci_dev *pdev); +int cxl_pci_driver_init(void); +void cxl_pci_driver_exit(void); +#else +static inline bool cxl_pci_drv_bound(struct pci_dev *pdev) { return false;= }; +static inline int cxl_pci_driver_init(void) { return 0; } +static inline void cxl_pci_driver_exit(void) { } +#endif #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/core/pci_drv.c similarity index 99% rename from drivers/cxl/pci.c rename to drivers/cxl/core/pci_drv.c index bd95be1f3d5c..06f2fd993cb0 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/core/pci_drv.c @@ -1131,6 +1131,17 @@ static struct pci_driver cxl_pci_driver =3D { }, }; =20 +bool cxl_pci_drv_bound(struct pci_dev *pdev) +{ + device_lock_assert(&pdev->dev); + + if (pdev->driver !=3D &cxl_pci_driver) + pr_err_ratelimited("%s device not bound to CXL PCI driver\n", + pci_name(pdev)); + + return (pdev->driver =3D=3D &cxl_pci_driver); +} + #define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0) static void cxl_handle_cper_event(enum cxl_event_type ev_type, struct cxl_cper_event_rec *rec) @@ -1177,7 +1188,7 @@ static void cxl_cper_work_fn(struct work_struct *work) } static DECLARE_WORK(cxl_cper_work, cxl_cper_work_fn); =20 -static int __init cxl_pci_driver_init(void) +int __init cxl_pci_driver_init(void) { int rc; =20 @@ -1192,15 +1203,9 @@ static int __init cxl_pci_driver_init(void) return rc; } =20 -static void __exit cxl_pci_driver_exit(void) +void cxl_pci_driver_exit(void) { cxl_cper_unregister_work(&cxl_cper_work); cancel_work_sync(&cxl_cper_work); pci_unregister_driver(&cxl_pci_driver); } - -module_init(cxl_pci_driver_init); -module_exit(cxl_pci_driver_exit); -MODULE_DESCRIPTION("CXL: PCI manageability"); -MODULE_LICENSE("GPL v2"); -MODULE_IMPORT_NS("CXL"); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 48f6a1492544..b70e1b505b5c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2507,6 +2507,8 @@ static __init int cxl_core_init(void) if (rc) goto err_ras; =20 + cxl_pci_driver_init(); + return 0; =20 err_ras: @@ -2522,6 +2524,7 @@ static __init int cxl_core_init(void) =20 static void cxl_core_exit(void) { + cxl_pci_driver_exit(); cxl_ras_exit(); cxl_region_exit(); bus_unregister(&cxl_bus_type); diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 6905f8e710ab..d8b8272ef87b 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -65,6 +65,7 @@ cxl_core-$(CONFIG_CXL_FEATURES) +=3D $(CXL_CORE_SRC)/feat= ures.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D $(CXL_CORE_SRC)/edac.o cxl_core-$(CONFIG_CXL_RAS) +=3D $(CXL_CORE_SRC)/ras.o cxl_core-$(CONFIG_CXL_RCH_RAS) +=3D $(CXL_CORE_SRC)/ras_rch.o +cxl_core-$(CONFIG_CXL_PCI) +=3D $(CXL_CORE_SRC)/pci_drv.o cxl_core-y +=3D config_check.o cxl_core-y +=3D cxl_core_test.o cxl_core-y +=3D cxl_core_exports.o --=20 2.34.1