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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB72.mail.protection.outlook.com (10.167.242.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Tue, 4 Nov 2025 17:03:23 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 4 Nov 2025 09:03:22 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 01/25] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Date: Tue, 4 Nov 2025 11:02:41 -0600 Message-ID: <20251104170305.4163840-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB72:EE_|PH7PR12MB5712:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a25f57c-c500-4410-ec65-08de1bc4101f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:03:23.0746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a25f57c-c500-4410-ec65-08de1bc4101f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5712 Content-Type: text/plain; charset="utf-8" The CXL DVSECs are currently defined in cxl/core/cxlpci.h. These are not accessible to other subsystems. Move these to uapi/linux/pci_regs.h. Change DVSEC name formatting to follow the existing PCI format in pci_regs.h. The current format uses CXL_DVSEC_XYZ and the CXL defines must be changed to be PCI_DVSEC_CXL_XYZ to match existing pci_regs.h. Leave PCI_DVSEC_CXL_PORT* defines as-is because they are already defined and may be in use by userspace application(s). Update existing usage to match the name change. Update the inline documentation to refer to latest CXL spec version. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Dan Williams Reviewed-by: Jonathan Cameron ---- Changes in v12->v13: - Add Dave Jiang's reviewed-by - Remove changes to existing PCI_DVSEC_CXL_PORT* defines. Update commit message. (Jonathan) Changes in v11 -> v12: - Change formatting to be same as existing definitions - Change GENMASK() -> __GENMASK() and BIT() to _BITUL() Changes in v10 -> v11: - New commit --- drivers/cxl/core/pci.c | 62 +++++++++++++++++----------------- drivers/cxl/core/regs.c | 12 +++---- drivers/cxl/cxlpci.h | 53 ----------------------------- drivers/cxl/pci.c | 2 +- drivers/pci/pci.c | 4 ++- include/uapi/linux/pci_regs.h | 63 ++++++++++++++++++++++++++++++++--- 6 files changed, 100 insertions(+), 96 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 18825e1505d6..cbc8defa6848 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -158,19 +158,19 @@ static int cxl_dvsec_mem_range_valid(struct cxl_dev_s= tate *cxlds, int id) int rc, i; u32 temp; =20 - if (id > CXL_DVSEC_RANGE_MAX) + if (id > PCI_DVSEC_CXL_RANGE_MAX) return -EINVAL; =20 /* Check MEM INFO VALID bit first, give up after 1s */ i =3D 1; do { rc =3D pci_read_config_dword(pdev, - d + CXL_DVSEC_RANGE_SIZE_LOW(id), + d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp); if (rc) return rc; =20 - valid =3D FIELD_GET(CXL_DVSEC_MEM_INFO_VALID, temp); + valid =3D FIELD_GET(PCI_DVSEC_CXL_MEM_INFO_VALID, temp); if (valid) break; msleep(1000); @@ -194,17 +194,17 @@ static int cxl_dvsec_mem_range_active(struct cxl_dev_= state *cxlds, int id) int rc, i; u32 temp; =20 - if (id > CXL_DVSEC_RANGE_MAX) + if (id > PCI_DVSEC_CXL_RANGE_MAX) return -EINVAL; =20 /* Check MEM ACTIVE bit, up to 60s timeout by default */ for (i =3D media_ready_timeout; i; i--) { rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(id), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp); if (rc) return rc; =20 - active =3D FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp); + active =3D FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE, temp); if (active) break; msleep(1000); @@ -233,11 +233,11 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds) u16 cap; =20 rc =3D pci_read_config_word(pdev, - d + CXL_DVSEC_CAP_OFFSET, &cap); + d + PCI_DVSEC_CXL_CAP_OFFSET, &cap); if (rc) return rc; =20 - hdm_count =3D FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + hdm_count =3D FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT_MASK, cap); for (i =3D 0; i < hdm_count; i++) { rc =3D cxl_dvsec_mem_range_valid(cxlds, i); if (rc) @@ -265,16 +265,16 @@ static int cxl_set_mem_enable(struct cxl_dev_state *c= xlds, u16 val) u16 ctrl; int rc; =20 - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, &ctrl); if (rc < 0) return rc; =20 - if ((ctrl & CXL_DVSEC_MEM_ENABLE) =3D=3D val) + if ((ctrl & PCI_DVSEC_CXL_MEM_ENABLE) =3D=3D val) return 1; - ctrl &=3D ~CXL_DVSEC_MEM_ENABLE; + ctrl &=3D ~PCI_DVSEC_CXL_MEM_ENABLE; ctrl |=3D val; =20 - rc =3D pci_write_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, ctrl); + rc =3D pci_write_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, ctrl); if (rc < 0) return rc; =20 @@ -290,7 +290,7 @@ static int devm_cxl_enable_mem(struct device *host, str= uct cxl_dev_state *cxlds) { int rc; =20 - rc =3D cxl_set_mem_enable(cxlds, CXL_DVSEC_MEM_ENABLE); + rc =3D cxl_set_mem_enable(cxlds, PCI_DVSEC_CXL_MEM_ENABLE); if (rc < 0) return rc; if (rc > 0) @@ -352,11 +352,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, return -ENXIO; } =20 - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CAP_OFFSET, &cap); if (rc) return rc; =20 - if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { + if (!(cap & PCI_DVSEC_CXL_MEM_CAPABLE)) { dev_dbg(dev, "Not MEM Capable\n"); return -ENXIO; } @@ -367,7 +367,7 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, * driver is for a spec defined class code which must be CXL.mem * capable, there is no point in continuing to enable CXL.mem. */ - hdm_count =3D FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + hdm_count =3D FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT_MASK, cap); if (!hdm_count || hdm_count > 2) return -EINVAL; =20 @@ -376,11 +376,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, * disabled, and they will remain moot after the HDM Decoder * capability is enabled. */ - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, &ctrl); if (rc) return rc; =20 - info->mem_enabled =3D FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); + info->mem_enabled =3D FIELD_GET(PCI_DVSEC_CXL_MEM_ENABLE, ctrl); if (!info->mem_enabled) return 0; =20 @@ -393,35 +393,35 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, return rc; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i), &temp); if (rc) return rc; =20 size =3D (u64)temp << 32; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(i), &temp); if (rc) return rc; =20 - size |=3D temp & CXL_DVSEC_MEM_SIZE_LOW_MASK; + size |=3D temp & PCI_DVSEC_CXL_MEM_SIZE_LOW_MASK; if (!size) { continue; } =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_BASE_HIGH(i), &temp); if (rc) return rc; =20 base =3D (u64)temp << 32; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_BASE_LOW(i), &temp); if (rc) return rc; =20 - base |=3D temp & CXL_DVSEC_MEM_BASE_LOW_MASK; + base |=3D temp & PCI_DVSEC_CXL_MEM_BASE_LOW_MASK; =20 info->dvsec_range[ranges++] =3D (struct range) { .start =3D base, @@ -1147,7 +1147,7 @@ u16 cxl_gpf_get_dvsec(struct device *dev) is_port =3D false; =20 dvsec =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, - is_port ? CXL_DVSEC_PORT_GPF : CXL_DVSEC_DEVICE_GPF); + is_port ? PCI_DVSEC_CXL_PORT_GPF : PCI_DVSEC_CXL_DEVICE_GPF); if (!dvsec) dev_warn(dev, "%s GPF DVSEC not present\n", is_port ? "Port" : "Device"); @@ -1163,14 +1163,14 @@ static int update_gpf_port_dvsec(struct pci_dev *pd= ev, int dvsec, int phase) =20 switch (phase) { case 1: - offset =3D CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET; - base =3D CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK; - scale =3D CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK; + offset =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL_OFFSET; + base =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE_MASK; + scale =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE_MASK; break; case 2: - offset =3D CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET; - base =3D CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK; - scale =3D CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK; + offset =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL_OFFSET; + base =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE_MASK; + scale =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE_MASK; break; default: return -EINVAL; diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 5ca7b0eed568..fb70ffbba72d 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -271,10 +271,10 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, "CXL"); static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_= hi, struct cxl_register_map *map) { - u8 reg_type =3D FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo); - int bar =3D FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo); + u8 reg_type =3D FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID_MASK, reg_lo= ); + int bar =3D FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BIR_MASK, reg_lo); u64 offset =3D ((u64)reg_hi << 32) | - (reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK); + (reg_lo & PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW_MASK); =20 if (offset > pci_resource_len(pdev, bar)) { dev_warn(&pdev->dev, @@ -311,15 +311,15 @@ static int __cxl_find_regblock_instance(struct pci_de= v *pdev, enum cxl_regloc_ty }; =20 regloc =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, - CXL_DVSEC_REG_LOCATOR); + PCI_DVSEC_CXL_REG_LOCATOR); if (!regloc) return -ENXIO; =20 pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); regloc_size =3D FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); =20 - regloc +=3D CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET; - regblocks =3D (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8; + regloc +=3D PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET; + regblocks =3D (regloc_size - PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET) / 8; =20 for (i =3D 0; i < regblocks; i++, regloc +=3D 8) { u32 reg_lo, reg_hi; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 7ae621e618e7..4985dbd90069 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -7,59 +7,6 @@ =20 #define CXL_MEMORY_PROGIF 0x10 =20 -/* - * See section 8.1 Configuration Space Registers in the CXL 2.0 - * Specification. Names are taken straight from the specification with "CX= L" and - * "DVSEC" redundancies removed. When obvious, abbreviations may be used. - */ -#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) - -/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ -#define CXL_DVSEC_PCIE_DEVICE 0 -#define CXL_DVSEC_CAP_OFFSET 0xA -#define CXL_DVSEC_MEM_CAPABLE BIT(2) -#define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4) -#define CXL_DVSEC_CTRL_OFFSET 0xC -#define CXL_DVSEC_MEM_ENABLE BIT(2) -#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) -#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) -#define CXL_DVSEC_MEM_INFO_VALID BIT(0) -#define CXL_DVSEC_MEM_ACTIVE BIT(1) -#define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28) -#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) -#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) -#define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28) - -#define CXL_DVSEC_RANGE_MAX 2 - -/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ -#define CXL_DVSEC_FUNCTION_MAP 2 - -/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ -#define CXL_DVSEC_PORT_EXTENSIONS 3 - -/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ -#define CXL_DVSEC_PORT_GPF 4 -#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK GENMASK(11, 8) -#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK GENMASK(11, 8) - -/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ -#define CXL_DVSEC_DEVICE_GPF 5 - -/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ -#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 - -/* CXL 2.0 8.1.9: Register Locator DVSEC */ -#define CXL_DVSEC_REG_LOCATOR 8 -#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC -#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16) - /* * NOTE: Currently all the functions which are enabled for CXL require the= ir * vectors to be in the first 16. Use this as the default max. diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bd100ac31672..bd95be1f3d5c 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -933,7 +933,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) cxlds->rcd =3D is_cxl_restricted(pdev); cxlds->serial =3D pci_get_dsn(pdev); cxlds->cxl_dvsec =3D pci_find_dvsec_capability( - pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + pdev, PCI_VENDOR_ID_CXL, PCI_DVSEC_CXL_DEVICE); if (!cxlds->cxl_dvsec) dev_warn(&pdev->dev, "Device DVSEC not present, skip CXL.mem init\n"); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b14dd064006c..53a49bb32514 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5002,7 +5002,9 @@ static bool cxl_sbr_masked(struct pci_dev *dev) if (!dvsec) return false; =20 - rc =3D pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®); + rc =3D pci_read_config_word(dev, + dvsec + PCI_DVSEC_CXL_PORT_CTL, + ®); if (rc || PCI_POSSIBLE_ERROR(reg)) return false; =20 diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 07e06aafec50..279b92f01d08 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1244,9 +1244,64 @@ /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE = */ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_= RSP_3_TYPE =20 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ -#define PCI_DVSEC_CXL_PORT 3 -#define PCI_DVSEC_CXL_PORT_CTL 0x0c -#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 +/* Compute Express Link (CXL r3.2, sec 8.1) + * + * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state + * is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these + * registers on downstream link-up events. + */ + +#define PCI_DVSEC_HEADER1_LENGTH_MASK __GENMASK(31, 20) + +/* CXL 3.2 8.1.3: PCIe DVSEC for CXL Device */ +#define PCI_DVSEC_CXL_DEVICE 0 +#define PCI_DVSEC_CXL_CAP_OFFSET 0xA +#define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2) +#define PCI_DVSEC_CXL_HDM_COUNT_MASK __GENMASK(5, 4) +#define PCI_DVSEC_CXL_CTRL_OFFSET 0xC +#define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2) +#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) +#define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) +#define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0) +#define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1) +#define PCI_DVSEC_CXL_MEM_SIZE_LOW_MASK __GENMASK(31, 28) +#define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) +#define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) +#define PCI_DVSEC_CXL_MEM_BASE_LOW_MASK __GENMASK(31, 28) + +#define PCI_DVSEC_CXL_RANGE_MAX 2 + +/* CXL 3.2 8.1.4: Non-CXL Function Map DVSEC */ +#define PCI_DVSEC_CXL_FUNCTION_MAP 2 + +/* CXL 3.2 8.1.5: Extensions DVSEC for Ports */ +#define PCI_DVSEC_CXL_PORT 3 +#define PCI_DVSEC_CXL_PORT_CTL 0x0c +#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 + +/* CXL 3.2 8.1.6: GPF DVSEC for CXL Port */ +#define PCI_DVSEC_CXL_PORT_GPF 4 +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE_MASK __GENMASK(3, 0) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE_MASK __GENMASK(11, 8) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE_MASK __GENMASK(3, 0) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE_MASK __GENMASK(11, 8) + +/* CXL 3.2 8.1.7: GPF DVSEC for CXL Device */ +#define PCI_DVSEC_CXL_DEVICE_GPF 5 + +/* CXL 3.2 8.1.8: PCIe DVSEC for Flex Bus Port */ +#define PCI_DVSEC_CXL_FLEXBUS_PORT 7 +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET 0xE +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK _BITUL(0) +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK _BITUL(2) + +/* CXL 3.2 8.1.9: Register Locator DVSEC */ +#define PCI_DVSEC_CXL_REG_LOCATOR 8 +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET 0xC +#define PCI_DVSEC_CXL_REG_LOCATOR_BIR_MASK __GENMASK(2, 0) +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID_MASK __GENMASK(15, 8) +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW_MASK __GENMASK(31, 16) =20 #endif /* LINUX_PCI_REGS_H */ --=20 2.34.1 From nobody Wed Dec 17 08:59:20 2025 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010016.outbound.protection.outlook.com [52.101.85.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D78B033A03C; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:03:34.1950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 156d7740-001b-42dd-a532-08de1bc416bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6566 Content-Type: text/plain; charset="utf-8" CXL and AER drivers need the ability to identify CXL devices. Introduce set_pcie_cxl() with logic checking for CXL.mem or CXL.cache status in the CXL Flexbus DVSEC status register. The CXL Flexbus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL CXL.cache and CXl.mem status. In the case the device is an EP or USP, call set_pcie_cxl() on behalf of the parent downstream device. Once a device is created there is possibilty the parent training or CXL state was updated as well. This will make certain the correct parent CXL state is cached. Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman Reviewed-by: Ira Weiny Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Alejandro Lucero Reviewed-by: Ben Cheatham --- Changes in v12->v13: - Add Ben's "reviewed-by" Changes in v11->v12: - Add review-by for Alejandro - Add comment in set_pcie_cxl() explaining why updating parent status. Changes in v10->v11: - Amend set_pcie_cxl() to check for Upstream Port's and EP's parent downstream port by calling set_pcie_cxl(). (Dan) - Retitle patch: 'Add' -> 'Introduce' - Add check for CXL.mem and CXL.cache (Alejandro, Dan) --- drivers/pci/probe.c | 29 +++++++++++++++++++++++++++++ include/linux/pci.h | 6 ++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 0ce98e18b5a8..63124651f865 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1709,6 +1709,33 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt =3D 1; } =20 +static void set_pcie_cxl(struct pci_dev *dev) +{ + struct pci_dev *parent; + u16 dvsec =3D pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS_PORT); + if (dvsec) { + u16 cap; + + pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET, &= cap); + + dev->is_cxl =3D FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK, cap) = || + FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK, cap); + } + + if (!pci_is_pcie(dev) || + !(pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ENDPOINT || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_UPSTREAM)) + return; + + /* + * Update parent's CXL state because alternate protocol training + * may have changed + */ + parent =3D pci_upstream_bridge(dev); + set_pcie_cxl(parent); +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent =3D pci_upstream_bridge(dev); @@ -2039,6 +2066,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); =20 + set_pcie_cxl(dev); + set_pcie_untrusted(dev); =20 if (pci_is_pcie(dev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index d1fdf81fbe1e..5c4759078d2f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -460,6 +460,7 @@ struct pci_dev { unsigned int is_pciehp:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* Compute Express Link (CXL) */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. 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Tue, 4 Nov 2025 17:03:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB77.mail.protection.outlook.com (10.167.242.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Tue, 4 Nov 2025 17:03:45 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 4 Nov 2025 09:03:44 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 03/25] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Date: Tue, 4 Nov 2025 11:02:43 -0600 Message-ID: <20251104170305.4163840-4-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB77:EE_|SJ0PR12MB8115:EE_ X-MS-Office365-Filtering-Correlation-Id: a5495e3d-c7ae-4077-573a-08de1bc41d67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:03:45.3592 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5495e3d-c7ae-4077-573a-08de1bc41d67 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8115 Content-Type: text/plain; charset="utf-8" The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras() are unnecessary helper functions used only for Endpoints. Remove these functions as they are not common for all CXL devices and do not provide value for EP handling. Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras() to cxl_handle_cor_ras(). Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Changes in v12->v13: - None Changes in v11->v12: - Added Dave Jiang's review by - Moved to front of series Changes in v10->v11: - None Reviewed-by: Dan Williams --- drivers/cxl/core/pci.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index cbc8defa6848..3ac90ff6e3d3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -711,8 +711,8 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -728,11 +728,6 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state = *cxlds, } } =20 -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); -} - /* CXL spec rev3.0 8.2.4.16.1 */ static void header_log_copy(void __iomem *ras_base, u32 *log) { @@ -754,8 +749,8 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static bool cxl_handle_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -788,11 +783,6 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxl= ds, return true; } =20 -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_ras(cxlds, cxlds->regs.ras); -} - #ifdef CONFIG_PCIEAER_CXL =20 static void cxl_dport_map_rch_aer(struct cxl_dport *dport) @@ -871,13 +861,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "C= XL"); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); + return cxl_handle_cor_ras(cxlds, dport->regs.ras); } =20 static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_ras(cxlds, dport->regs.ras); + return cxl_handle_ras(cxlds, dport->regs.ras); } =20 /* @@ -974,7 +964,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_endpoint_cor_ras(cxlds); + cxl_handle_cor_ras(cxlds, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -1003,7 +993,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pd= ev, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_endpoint_ras(cxlds); + ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); } =20 =20 --=20 2.34.1 From nobody Wed Dec 17 08:59:20 2025 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012049.outbound.protection.outlook.com [52.101.53.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49F343396FD; Tue, 4 Nov 2025 17:04:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 4 Nov 2025 09:03:55 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 04/25] cxl/pci: Remove unnecessary CXL RCH handling helper functions Date: Tue, 4 Nov 2025 11:02:44 -0600 Message-ID: <20251104170305.4163840-5-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB74:EE_|MN0PR12MB5763:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ccc4f89-bdbe-4735-64f2-08de1bc42445 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:03:56.8822 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ccc4f89-bdbe-4735-64f2-08de1bc42445 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5763 Content-Type: text/plain; charset="utf-8" cxl_handle_rdport_cor_ras() and cxl_handle_rdport_ras() are specific to Restricted CXL Host (RCH) handling. Improve readability and maintainability by replacing these and instead using the common cxl_handle_cor_ras() and cxl_handle_ras() functions. Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams --- Changes in v12->v13: - None Changes in v11->v12: - Add reviewed-by for Alejandro & Dave Jiang - Moved to front of series Changes in v10->v11: - New patch --- drivers/cxl/core/pci.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 3ac90ff6e3d3..a0f53a20fa61 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -858,18 +858,6 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 -static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return cxl_handle_cor_ras(cxlds, dport->regs.ras); -} - -static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return cxl_handle_ras(cxlds, dport->regs.ras); -} - /* * Copy the AER capability registers using 32 bit read accesses. * This is necessary because RCRB AER capability is MMIO mapped. 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Tue, 4 Nov 2025 17:04:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB71.mail.protection.outlook.com (10.167.242.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.6 via Frontend Transport; Tue, 4 Nov 2025 17:04:07 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 4 Nov 2025 09:04:06 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 05/25] cxl: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c Date: Tue, 4 Nov 2025 11:02:45 -0600 Message-ID: <20251104170305.4163840-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB71:EE_|CH3PR12MB9080:EE_ X-MS-Office365-Filtering-Correlation-Id: a71acd43-474e-4aed-5c11-08de1bc42aae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:04:07.6353 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a71acd43-474e-4aed-5c11-08de1bc42aae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB71.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9080 Content-Type: text/plain; charset="utf-8" From: Dave Jiang Create new config CONFIG_CXL_RAS and put all CXL RAS items behind the config. The config will depend on CPER and PCIE AER to build. Move the related VH RAS code from core/pci.c to core/ras.c. Restricted CXL host (RCH) RAS functions will be moved in a future patch. Cc: Robert Richter Cc: Terry Bowman Reviewed-by: Joshua Hahn Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Reviewed-by: Dan Williams Reviewed-by: Alison Schofield Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman --- Changes in v11->v12: - None Changes in v10->v11: - New patch - Updated by Terry Bowman to use (ACPI_APEI_GHES && PCIEAER_CXL) dependency in Kconfig. Otherwise checks will be reauired for CONFIG_PCIEAER because AER driver functions are called. --- drivers/cxl/Kconfig | 4 + drivers/cxl/core/Makefile | 2 +- drivers/cxl/core/core.h | 31 +++++++ drivers/cxl/core/pci.c | 189 +------------------------------------- drivers/cxl/core/ras.c | 176 +++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 8 -- drivers/cxl/cxlpci.h | 16 ++++ tools/testing/cxl/Kbuild | 2 +- 8 files changed, 233 insertions(+), 195 deletions(-) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 48b7314afdb8..217888992c88 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -233,4 +233,8 @@ config CXL_MCE def_bool y depends on X86_MCE && MEMORY_FAILURE =20 +config CXL_RAS + def_bool y + depends on ACPI_APEI_GHES && PCIEAER && CXL_PCI + endif diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 5ad8fef210b5..b2930cc54f8b 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -14,9 +14,9 @@ cxl_core-y +=3D pci.o cxl_core-y +=3D hdm.o cxl_core-y +=3D pmu.o cxl_core-y +=3D cdat.o -cxl_core-y +=3D ras.o cxl_core-$(CONFIG_TRACING) +=3D trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D region.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o +cxl_core-$(CONFIG_CXL_RAS) +=3D ras.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 1fb66132b777..bc818de87ccc 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -144,8 +144,39 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct= access_coordinate *c); int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, struct access_coordinate *c); =20 +#ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); +bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base); +void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e); +#else +static inline int cxl_ras_init(void) +{ + return 0; +} + +static inline void cxl_ras_exit(void) +{ +} + +static inline bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iome= m *ras_base) +{ + return false; +} +static inline void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __= iomem *ras_base) { } +#endif /* CONFIG_CXL_RAS */ + +/* Restricted CXL Host specific RAS functions */ +#ifdef CONFIG_CXL_RAS +void cxl_dport_map_rch_aer(struct cxl_dport *dport); +void cxl_disable_rch_root_ints(struct cxl_dport *dport); +void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); +#else +static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } +static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } +static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } +#endif /* CONFIG_CXL_RAS */ + int cxl_gpf_port_setup(struct cxl_dport *dport); =20 struct cxl_hdm; diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a0f53a20fa61..cd73cea93282 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -711,81 +711,8 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) -{ - void __iomem *addr; - u32 status; - - if (!ras_base) - return; - - addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; - status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); - } -} - -/* CXL spec rev3.0 8.2.4.16.1 */ -static void header_log_copy(void __iomem *ras_base, u32 *log) -{ - void __iomem *addr; - u32 *log_addr; - int i, log_u32_size =3D CXL_HEADERLOG_SIZE / sizeof(u32); - - addr =3D ras_base + CXL_RAS_HEADER_LOG_OFFSET; - log_addr =3D log; - - for (i =3D 0; i < log_u32_size; i++) { - *log_addr =3D readl(addr); - log_addr++; - addr +=3D sizeof(u32); - } -} - -/* - * Log the state of the RAS status registers and prepare them to log the - * next error status. Return 1 if reset needed. - */ -static bool cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) -{ - u32 hl[CXL_HEADERLOG_SIZE_U32]; - void __iomem *addr; - u32 status; - u32 fe; - - if (!ras_base) - return false; - - addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; - status =3D readl(addr); - if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; - - /* If multiple errors, log header points to first error from ctrl reg */ - if (hweight32(status) > 1) { - void __iomem *rcc_addr =3D - ras_base + CXL_RAS_CAP_CONTROL_OFFSET; - - fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, - readl(rcc_addr))); - } else { - fe =3D status; - } - - header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); - writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); - - return true; -} - -#ifdef CONFIG_PCIEAER_CXL - -static void cxl_dport_map_rch_aer(struct cxl_dport *dport) +#ifdef CONFIG_CXL_RAS +void cxl_dport_map_rch_aer(struct cxl_dport *dport) { resource_size_t aer_phys; struct device *host; @@ -800,19 +727,7 @@ static void cxl_dport_map_rch_aer(struct cxl_dport *dp= ort) } } =20 -static void cxl_dport_map_ras(struct cxl_dport *dport) -{ - struct cxl_register_map *map =3D &dport->reg_map; - struct device *dev =3D dport->dport_dev; - - if (!map->component_map.ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) - dev_dbg(dev, "Failed to map RAS capability.\n"); -} - -static void cxl_disable_rch_root_ints(struct cxl_dport *dport) +void cxl_disable_rch_root_ints(struct cxl_dport *dport) { void __iomem *aer_base =3D dport->regs.dport_aer; u32 aer_cmd_mask, aer_cmd; @@ -836,28 +751,6 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } =20 -/** - * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport - * @dport: the cxl_dport that needs to be initialized - * @host: host device for devm operations - */ -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) -{ - dport->reg_map.host =3D host; - cxl_dport_map_ras(dport); - - if (dport->rch) { - struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); - - if (!host_bridge->native_aer) - return; - - cxl_dport_map_rch_aer(dport); - cxl_disable_rch_root_ints(dport); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); - /* * Copy the AER capability registers using 32 bit read accesses. * This is necessary because RCRB AER capability is MMIO mapped. Clear the @@ -906,7 +799,7 @@ static bool cxl_rch_get_aer_severity(struct aer_capabil= ity_regs *aer_regs, return false; } =20 -static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) +void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); struct aer_capability_regs aer_regs; @@ -931,82 +824,8 @@ static void cxl_handle_rdport_errors(struct cxl_dev_st= ate *cxlds) else cxl_handle_ras(cxlds, dport->regs.ras); } - -#else -static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { } #endif =20 -void cxl_cor_error_detected(struct pci_dev *pdev) -{ - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct device *dev =3D &cxlds->cxlmd->dev; - - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } - - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - - cxl_handle_cor_ras(cxlds, cxlds->regs.ras); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); - -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) -{ - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; - - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } - - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); - } - - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; -} -EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); - static int cxl_flit_size(struct pci_dev *pdev) { if (cxl_pci_flit_256(pdev)) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 2731ba3a0799..b933030b8e1e 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "trace.h" =20 static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev, @@ -124,3 +125,178 @@ void cxl_ras_exit(void) cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); cancel_work_sync(&cxl_cper_prot_err_work); } + +static void cxl_dport_map_ras(struct cxl_dport *dport) +{ + struct cxl_register_map *map =3D &dport->reg_map; + struct device *dev =3D dport->dport_dev; + + if (!map->component_map.ras.valid) + dev_dbg(dev, "RAS registers not found\n"); + else if (cxl_map_component_regs(map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(dev, "Failed to map RAS capability.\n"); +} + +/** + * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport + * @dport: the cxl_dport that needs to be initialized + * @host: host device for devm operations + */ +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) +{ + dport->reg_map.host =3D host; + cxl_dport_map_ras(dport); + + if (dport->rch) { + struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); + + if (!host_bridge->native_aer) + return; + + cxl_dport_map_rch_aer(dport); + cxl_disable_rch_root_ints(dport); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); + +void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e) +{ + void __iomem *addr; + u32 status; + + if (!ras_base) + return; + + addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; + status =3D readl(addr); + if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + } +} + +/* CXL spec rev3.0 8.2.4.16.1 */ +static void header_log_copy(void __iomem *ras_base, u32 *log) +{ + void __iomem *addr; + u32 *log_addr; + int i, log_u32_size =3D CXL_HEADERLOG_SIZE / sizeof(u32); + + addr =3D ras_base + CXL_RAS_HEADER_LOG_OFFSET; + log_addr =3D log; + + for (i =3D 0; i < log_u32_size; i++) { + *log_addr =3D readl(addr); + log_addr++; + addr +=3D sizeof(u32); + } +} + +/* + * Log the state of the RAS status registers and prepare them to log the + * next error status. Return 1 if reset needed. + */ +bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base) +{ + u32 hl[CXL_HEADERLOG_SIZE_U32]; + void __iomem *addr; + u32 status; + u32 fe; + + if (!ras_base) + return false; + + addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; + status =3D readl(addr); + if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) + return false; + + /* If multiple errors, log header points to first error from ctrl reg */ + if (hweight32(status) > 1) { + void __iomem *rcc_addr =3D + ras_base + CXL_RAS_CAP_CONTROL_OFFSET; + + fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, + readl(rcc_addr))); + } else { + fe =3D status; + } + + header_log_copy(ras_base, hl); + trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); + + return true; +} + +void cxl_cor_error_detected(struct pci_dev *pdev) +{ + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct device *dev =3D &cxlds->cxlmd->dev; + + scoped_guard(device, dev) { + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); + +pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; + struct device *dev =3D &cxlmd->dev; + bool ue; + + scoped_guard(device, dev) { + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return PCI_ERS_RESULT_DISCONNECT; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + /* + * A frozen channel indicates an impending reset which is fatal to + * CXL.mem operation, and will likely crash the system. On the off + * chance the situation is recoverable dump the status of the RAS + * capability registers and bounce the active state of the memdev. + */ + ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); + } + + + switch (state) { + case pci_channel_io_normal: + if (ue) { + device_release_driver(dev); + return PCI_ERS_RESULT_NEED_RESET; + } + return PCI_ERS_RESULT_CAN_RECOVER; + case pci_channel_io_frozen: + dev_warn(&pdev->dev, + "%s: frozen state error detected, disable CXL.mem\n", + dev_name(dev)); + device_release_driver(dev); + return PCI_ERS_RESULT_NEED_RESET; + case pci_channel_io_perm_failure: + dev_warn(&pdev->dev, + "failure state error detected, request disconnect\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + return PCI_ERS_RESULT_NEED_RESET; +} +EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 231ddccf8977..259ed4b676e1 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -776,14 +776,6 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, struct device *dport_dev, int port_id, resource_size_t rcrb); =20 -#ifdef CONFIG_PCIEAER_CXL -void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); -#else -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, - struct device *host) { } -#endif - struct cxl_decoder *to_cxl_decoder(struct device *dev); struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 4985dbd90069..0c8b6ee7b6de 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -77,7 +77,23 @@ static inline bool cxl_pci_flit_256(struct pci_dev *pdev) int devm_cxl_port_enumerate_dports(struct cxl_port *port); struct cxl_dev_state; void read_cdat_data(struct cxl_port *port); + +#ifdef CONFIG_CXL_RAS void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); +#else +static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } + +static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + return PCI_ERS_RESULT_NONE; +} + +static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, + struct device *host) { } +#endif + #endif /* __CXL_PCI_H__ */ diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 0d5ce4b74b9f..927fbb6c061f 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -58,12 +58,12 @@ cxl_core-y +=3D $(CXL_CORE_SRC)/pci.o cxl_core-y +=3D $(CXL_CORE_SRC)/hdm.o cxl_core-y +=3D $(CXL_CORE_SRC)/pmu.o cxl_core-y +=3D $(CXL_CORE_SRC)/cdat.o -cxl_core-y +=3D $(CXL_CORE_SRC)/ras.o cxl_core-$(CONFIG_TRACING) +=3D $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D $(CXL_CORE_SRC)/region.o cxl_core-$(CONFIG_CXL_MCE) +=3D $(CXL_CORE_SRC)/mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D $(CXL_CORE_SRC)/features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D $(CXL_CORE_SRC)/edac.o +cxl_core-$(CONFIG_CXL_RAS) +=3D $(CXL_CORE_SRC)/ras.o cxl_core-y +=3D config_check.o cxl_core-y +=3D cxl_core_test.o cxl_core-y +=3D cxl_core_exports.o --=20 2.34.1 From nobody Wed Dec 17 08:59:20 2025 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010015.outbound.protection.outlook.com [52.101.56.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B45DE33A02B; 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Tue, 4 Nov 2025 09:04:17 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 06/25] cxl: Move CXL driver's RCH error handling into core/ras_rch.c Date: Tue, 4 Nov 2025 11:02:46 -0600 Message-ID: <20251104170305.4163840-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|DM4PR12MB6376:EE_ X-MS-Office365-Filtering-Correlation-Id: 792e2405-55b2-45ed-01fd-08de1bc43152 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:04:18.7599 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 792e2405-55b2-45ed-01fd-08de1bc43152 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6376 Content-Type: text/plain; charset="utf-8" Restricted CXL Host (RCH) protocol error handling uses a procedure distinct from the CXL Virtual Hierarchy (VH) handling. This is because of the differences in the RCH and VH topologies. Improve the maintainability and add ability to enable/disable RCH handling. Move and combine the RCH handling code into a single block conditionally compiled with the CONFIG_CXL_RCH_RAS kernel config. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- Changes in v12->v13: - None Changes v11->v12: - Moved CXL_RCH_RAS Kconfig definition here from following commit. Changes v10->v11: - New patch --- drivers/cxl/Kconfig | 7 +++ drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 5 +- drivers/cxl/core/pci.c | 115 ----------------------------------- drivers/cxl/core/ras_rch.c | 120 +++++++++++++++++++++++++++++++++++++ tools/testing/cxl/Kbuild | 1 + 6 files changed, 132 insertions(+), 117 deletions(-) create mode 100644 drivers/cxl/core/ras_rch.c diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 217888992c88..ffe6ad981434 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -237,4 +237,11 @@ config CXL_RAS def_bool y depends on ACPI_APEI_GHES && PCIEAER && CXL_PCI =20 +config CXL_RCH_RAS + bool "CXL: Restricted CXL Host (RCH) protocol error handling" + def_bool n + depends on CXL_RAS + help + RAS support for Restricted CXL Host (RCH) defined in CXL1.1. + endif diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index b2930cc54f8b..fa1d4aed28b9 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -20,3 +20,4 @@ cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o cxl_core-$(CONFIG_CXL_RAS) +=3D ras.o +cxl_core-$(CONFIG_CXL_RCH_RAS) +=3D ras_rch.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index bc818de87ccc..c30ab7c25a92 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -4,6 +4,7 @@ #ifndef __CXL_CORE_H__ #define __CXL_CORE_H__ =20 +#include #include #include =20 @@ -167,7 +168,7 @@ static inline void cxl_handle_cor_ras(struct cxl_dev_st= ate *cxlds, void __iomem #endif /* CONFIG_CXL_RAS */ =20 /* Restricted CXL Host specific RAS functions */ -#ifdef CONFIG_CXL_RAS +#ifdef CONFIG_CXL_RCH_RAS void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); @@ -175,7 +176,7 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxl= ds); static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } -#endif /* CONFIG_CXL_RAS */ +#endif /* CONFIG_CXL_RCH_RAS */ =20 int cxl_gpf_port_setup(struct cxl_dport *dport); =20 diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index cd73cea93282..a66f7a84b5c8 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -711,121 +711,6 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -#ifdef CONFIG_CXL_RAS -void cxl_dport_map_rch_aer(struct cxl_dport *dport) -{ - resource_size_t aer_phys; - struct device *host; - u16 aer_cap; - - aer_cap =3D cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); - if (aer_cap) { - host =3D dport->reg_map.host; - aer_phys =3D aer_cap + dport->rcrb.base; - dport->regs.dport_aer =3D devm_cxl_iomap_block(host, aer_phys, - sizeof(struct aer_capability_regs)); - } -} - -void cxl_disable_rch_root_ints(struct cxl_dport *dport) -{ - void __iomem *aer_base =3D dport->regs.dport_aer; - u32 aer_cmd_mask, aer_cmd; - - if (!aer_base) - return; - - /* - * Disable RCH root port command interrupts. - * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors - * - * This sequence may not be necessary. CXL spec states disabling - * the root cmd register's interrupts is required. But, PCI spec - * shows these are disabled by default on reset. - */ - aer_cmd_mask =3D (PCI_ERR_ROOT_CMD_COR_EN | - PCI_ERR_ROOT_CMD_NONFATAL_EN | - PCI_ERR_ROOT_CMD_FATAL_EN); - aer_cmd =3D readl(aer_base + PCI_ERR_ROOT_COMMAND); - aer_cmd &=3D ~aer_cmd_mask; - writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); -} - -/* - * Copy the AER capability registers using 32 bit read accesses. - * This is necessary because RCRB AER capability is MMIO mapped. Clear the - * status after copying. - * - * @aer_base: base address of AER capability block in RCRB - * @aer_regs: destination for copying AER capability - */ -static bool cxl_rch_get_aer_info(void __iomem *aer_base, - struct aer_capability_regs *aer_regs) -{ - int read_cnt =3D sizeof(struct aer_capability_regs) / sizeof(u32); - u32 *aer_regs_buf =3D (u32 *)aer_regs; - int n; - - if (!aer_base) - return false; - - /* Use readl() to guarantee 32-bit accesses */ - for (n =3D 0; n < read_cnt; n++) - aer_regs_buf[n] =3D readl(aer_base + n * sizeof(u32)); - - writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); - writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); - - return true; -} - -/* Get AER severity. Return false if there is no error. */ -static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, - int *severity) -{ - if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { - if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) - *severity =3D AER_FATAL; - else - *severity =3D AER_NONFATAL; - return true; - } - - if (aer_regs->cor_status & ~aer_regs->cor_mask) { - *severity =3D AER_CORRECTABLE; - return true; - } - - return false; -} - -void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) -{ - struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); - struct aer_capability_regs aer_regs; - struct cxl_dport *dport; - int severity; - - struct cxl_port *port __free(put_cxl_port) =3D - cxl_pci_find_port(pdev, &dport); - if (!port) - return; - - if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) - return; - - if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) - return; - - pci_print_aer(pdev, severity, &aer_regs); - - if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(cxlds, dport->regs.ras); - else - cxl_handle_ras(cxlds, dport->regs.ras); -} -#endif - static int cxl_flit_size(struct pci_dev *pdev) { if (cxl_pci_flit_256(pdev)) diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c new file mode 100644 index 000000000000..f6de5492a8b7 --- /dev/null +++ b/drivers/cxl/core/ras_rch.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include +#include "trace.h" + +void cxl_dport_map_rch_aer(struct cxl_dport *dport) +{ + resource_size_t aer_phys; + struct device *host; + u16 aer_cap; + + aer_cap =3D cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); + if (aer_cap) { + host =3D dport->reg_map.host; + aer_phys =3D aer_cap + dport->rcrb.base; + dport->regs.dport_aer =3D devm_cxl_iomap_block(host, aer_phys, + sizeof(struct aer_capability_regs)); + } +} + +void cxl_disable_rch_root_ints(struct cxl_dport *dport) +{ + void __iomem *aer_base =3D dport->regs.dport_aer; + u32 aer_cmd_mask, aer_cmd; + + if (!aer_base) + return; + + /* + * Disable RCH root port command interrupts. + * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors + * + * This sequence may not be necessary. CXL spec states disabling + * the root cmd register's interrupts is required. But, PCI spec + * shows these are disabled by default on reset. + */ + aer_cmd_mask =3D (PCI_ERR_ROOT_CMD_COR_EN | + PCI_ERR_ROOT_CMD_NONFATAL_EN | + PCI_ERR_ROOT_CMD_FATAL_EN); + aer_cmd =3D readl(aer_base + PCI_ERR_ROOT_COMMAND); + aer_cmd &=3D ~aer_cmd_mask; + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); +} + +/* + * Copy the AER capability registers using 32 bit read accesses. + * This is necessary because RCRB AER capability is MMIO mapped. Clear the + * status after copying. + * + * @aer_base: base address of AER capability block in RCRB + * @aer_regs: destination for copying AER capability + */ +static bool cxl_rch_get_aer_info(void __iomem *aer_base, + struct aer_capability_regs *aer_regs) +{ + int read_cnt =3D sizeof(struct aer_capability_regs) / sizeof(u32); + u32 *aer_regs_buf =3D (u32 *)aer_regs; + int n; + + if (!aer_base) + return false; + + /* Use readl() to guarantee 32-bit accesses */ + for (n =3D 0; n < read_cnt; n++) + aer_regs_buf[n] =3D readl(aer_base + n * sizeof(u32)); + + writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); + writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); + + return true; +} + +/* Get AER severity. Return false if there is no error. */ +static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, + int *severity) +{ + if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { + if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) + *severity =3D AER_FATAL; + else + *severity =3D AER_NONFATAL; + return true; + } + + if (aer_regs->cor_status & ~aer_regs->cor_mask) { + *severity =3D AER_CORRECTABLE; + return true; + } + + return false; +} + +void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) +{ + struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); + struct aer_capability_regs aer_regs; + struct cxl_dport *dport; + int severity; + + struct cxl_port *port __free(put_cxl_port) =3D + cxl_pci_find_port(pdev, &dport); + if (!port) + return; + + if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) + return; + + if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) + return; + + pci_print_aer(pdev, severity, &aer_regs); + if (severity =3D=3D AER_CORRECTABLE) + cxl_handle_cor_ras(cxlds, dport->regs.ras); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:04:30.5504 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcefeca3-8294-4003-c860-08de1bc43856 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB999107 Content-Type: text/plain; charset="utf-8" cxl_rch_handle_error_iter() includes a call to device_lock() using a goto for multiple return paths. Improve readability and maintainability by using the guard() lock variant. Signed-off-by: Terry Bowman Reviewed-by: Dan Williams Reviewed-by: Dave Jiang >=20 Reviewed-by: Jonathan Cameron --- Changes in v12->v13: - New patch --- drivers/pci/pcie/aer.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 0b5ed4722ac3..cbaed65577d9 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1187,12 +1187,11 @@ static int cxl_rch_handle_error_iter(struct pci_dev= *dev, void *data) if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) return 0; =20 - /* Protect dev->driver */ - device_lock(&dev->dev); + guard(device)(&dev->dev); =20 err_handler =3D dev->driver ? dev->driver->err_handler : NULL; if (!err_handler) - goto out; + return 0; =20 if (info->severity =3D=3D AER_CORRECTABLE) { if (err_handler->cor_error_detected) @@ -1203,8 +1202,6 @@ static int cxl_rch_handle_error_iter(struct pci_dev *= dev, void *data) else if (info->severity =3D=3D AER_FATAL) err_handler->error_detected(dev, pci_channel_io_frozen); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:04:40.9566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fdfa79f5-8f52-4637-c369-08de1bc43e8a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB76.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9231 Content-Type: text/plain; charset="utf-8" The restricted CXL Host (RCH) AER error handling logic currently resides in the AER driver file, drivers/pci/pcie/aer.c. CXL specific changes are conditionally compiled using #ifdefs. Improve the AER driver maintainability by separating the RCH specific logic from the AER driver's core functionality and removing the ifdefs. Introduce drivers/pci/pcie/aer_cxl_rch.c for moving the RCH AER logic into. Conditionally compile the file using the CONFIG_CXL_RCH_RAS Kconfig. Move the CXL logic into the new file but leave helper functions in aer.c for now as they will be moved in future patch for CXL virtual hierarchy handling. Export the handler functions as needed. Export pci_aer_unmask_internal_errors() allowing for all subsystems to use. Avoid multiple declaration moves and export cxl_error_is_native() now to allow access from cxl_core. Inorder to maintain compilation after the move other changes are required. Change cxl_rch_handle_error() & cxl_rch_enable_rcec() to be non-static inorder for accessing from the AER driver in aer.c. Update the new file with the SPDX and 2023 AMD copyright notations because the RCH bits were initally contributed in 2023 by AMD. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams --- Changes in v12->v13: - Add forward declararation of 'struct aer_err_info' in pci/pci.h (Terry) - Changed copyright date from 2025 to 2023 (Jonathan) - Add David Jiang's, Jonathan's, and Ben's review-by - Readd 'struct aer_err_info' (Bot) Changes in v11->v12: - Rename drivers/pci/pcie/cxl_rch.c to drivers/pci/pcie/aer_cxl_rch.c (Luka= s) - Removed forward declararation of 'struct aer_err_info' in pci/pci.h (Terr= y) Changes in v10->v11: - Remove changes in code-split and move to earlier, new patch - Add #include to cxl_ras.c - Move cxl_rch_handle_error() & cxl_rch_enable_rcec() declarations from pci= .h to aer.h, more localized. - Introduce CONFIG_CXL_RCH_RAS, includes Makefile changes, ras.c ifdef changes --- drivers/pci/pci.h | 16 +++++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 105 +++------------------------------ drivers/pci/pcie/aer_cxl_rch.c | 96 ++++++++++++++++++++++++++++++ include/linux/aer.h | 8 +++ 5 files changed, 128 insertions(+), 98 deletions(-) create mode 100644 drivers/pci/pcie/aer_cxl_rch.c diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4492b809094b..d23430e3eea0 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1295,4 +1295,20 @@ static inline int pci_msix_write_tph_tag(struct pci_= dev *pdev, unsigned int inde (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ PCI_CONF1_EXT_REG(reg)) =20 +struct aer_err_info; + +#ifdef CONFIG_CXL_RCH_RAS +void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); +void cxl_rch_enable_rcec(struct pci_dev *rcec); +#else +static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_er= r_info *info) { } +static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { } +#endif + +#ifdef CONFIG_CXL_RAS +bool is_internal_error(struct aer_err_info *info); +#else +static inline bool is_internal_error(struct aer_err_info *info) { return f= alse; } +#endif + #endif /* DRIVERS_PCI_H */ diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 173829aa02e6..970e7cbc5b34 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o =20 obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o +obj-$(CONFIG_CXL_RCH_RAS) +=3D aer_cxl_rch.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index cbaed65577d9..f5f22216bb41 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1130,7 +1130,7 @@ static bool find_source_device(struct pci_dev *parent, * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer =3D dev->aer_cap; u32 mask; @@ -1143,116 +1143,25 @@ static void pci_aer_unmask_internal_errors(struct = pci_dev *dev) mask &=3D ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_GPL(pci_aer_unmask_internal_errors); =20 -static bool is_cxl_mem_dev(struct pci_dev *dev) -{ - /* - * The capability, status, and control fields in Device 0, - * Function 0 DVSEC control the CXL functionality of the - * entire device (CXL 3.0, 8.1.3). - */ - if (dev->devfn !=3D PCI_DEVFN(0, 0)) - return false; - - /* - * CXL Memory Devices must have the 502h class code set (CXL - * 3.0, 8.1.12.1). - */ - if ((dev->class >> 8) !=3D PCI_CLASS_MEMORY_CXL) - return false; - - return true; -} - -static bool cxl_error_is_native(struct pci_dev *dev) +bool cxl_error_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); =20 return (pcie_ports_native || host->native_aer); } +EXPORT_SYMBOL_NS_GPL(cxl_error_is_native, "CXL"); =20 -static bool is_internal_error(struct aer_err_info *info) +bool is_internal_error(struct aer_err_info *info) { if (info->severity =3D=3D AER_CORRECTABLE) return info->status & PCI_ERR_COR_INTERNAL; =20 return info->status & PCI_ERR_UNC_INTN; } - -static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) -{ - struct aer_err_info *info =3D (struct aer_err_info *)data; - const struct pci_error_handlers *err_handler; - - if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) - return 0; - - guard(device)(&dev->dev); - - err_handler =3D dev->driver ? dev->driver->err_handler : NULL; - if (!err_handler) - return 0; - - if (info->severity =3D=3D AER_CORRECTABLE) { - if (err_handler->cor_error_detected) - err_handler->cor_error_detected(dev); - } else if (err_handler->error_detected) { - if (info->severity =3D=3D AER_NONFATAL) - err_handler->error_detected(dev, pci_channel_io_normal); - else if (info->severity =3D=3D AER_FATAL) - err_handler->error_detected(dev, pci_channel_io_frozen); - } - return 0; -} - -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info = *info) -{ - /* - * Internal errors of an RCEC indicate an AER error in an - * RCH's downstream port. Check and handle them in the CXL.mem - * device driver. - */ - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); -} - -static int handles_cxl_error_iter(struct pci_dev *dev, void *data) -{ - bool *handles_cxl =3D data; - - if (!*handles_cxl) - *handles_cxl =3D is_cxl_mem_dev(dev) && cxl_error_is_native(dev); - - /* Non-zero terminates iteration */ - return *handles_cxl; -} - -static bool handles_cxl_errors(struct pci_dev *rcec) -{ - bool handles_cxl =3D false; - - if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); - - return handles_cxl; -} - -static void cxl_rch_enable_rcec(struct pci_dev *rcec) -{ - if (!handles_cxl_errors(rcec)) - return; - - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); -} - -#else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } -#endif +EXPORT_SYMBOL_NS_GPL(is_internal_error, "CXL"); +#endif /* CONFIG_CXL_RAS */ =20 /** * pci_aer_handle_error - handle logging error into an event log diff --git a/drivers/pci/pcie/aer_cxl_rch.c b/drivers/pci/pcie/aer_cxl_rch.c new file mode 100644 index 000000000000..f4d160f18169 --- /dev/null +++ b/drivers/pci/pcie/aer_cxl_rch.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2023 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include "../pci.h" + +static bool is_cxl_mem_dev(struct pci_dev *dev) +{ + /* + * The capability, status, and control fields in Device 0, + * Function 0 DVSEC control the CXL functionality of the + * entire device (CXL 3.0, 8.1.3). + */ + if (dev->devfn !=3D PCI_DEVFN(0, 0)) + return false; + + /* + * CXL Memory Devices must have the 502h class code set (CXL + * 3.0, 8.1.12.1). + */ + if ((dev->class >> 8) !=3D PCI_CLASS_MEMORY_CXL) + return false; + + return true; +} + +static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) +{ + struct aer_err_info *info =3D (struct aer_err_info *)data; + const struct pci_error_handlers *err_handler; + + if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) + return 0; + + guard(device)(&dev->dev); + + err_handler =3D dev->driver ? dev->driver->err_handler : NULL; + if (!err_handler) + return 0; + + if (info->severity =3D=3D AER_CORRECTABLE) { + if (err_handler->cor_error_detected) + err_handler->cor_error_detected(dev); + } else if (err_handler->error_detected) { + if (info->severity =3D=3D AER_NONFATAL) + err_handler->error_detected(dev, pci_channel_io_normal); + else if (info->severity =3D=3D AER_FATAL) + err_handler->error_detected(dev, pci_channel_io_frozen); + } + return 0; +} + +void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +{ + /* + * Internal errors of an RCEC indicate an AER error in an + * RCH's downstream port. Check and handle them in the CXL.mem + * device driver. + */ + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && + is_internal_error(info)) + pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); +} + +static int handles_cxl_error_iter(struct pci_dev *dev, void *data) +{ + bool *handles_cxl =3D data; + + if (!*handles_cxl) + *handles_cxl =3D is_cxl_mem_dev(dev) && cxl_error_is_native(dev); + + /* Non-zero terminates iteration */ + return *handles_cxl; +} + +static bool handles_cxl_errors(struct pci_dev *rcec) +{ + bool handles_cxl =3D false; + + if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(rcec)) + pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + + return handles_cxl; +} + +void cxl_rch_enable_rcec(struct pci_dev *rcec) +{ + if (!handles_cxl_errors(rcec)) + return; + + pci_aer_unmask_internal_errors(rcec); + pci_info(rcec, "CXL: Internal errors unmasked"); +} diff --git a/include/linux/aer.h b/include/linux/aer.h index 02940be66324..2ef820563996 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -56,12 +56,20 @@ struct aer_capability_regs { #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:04:53.3201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a30a7882-a478-43b9-5e1c-08de1bc445e9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8651 Content-Type: text/plain; charset="utf-8" The AER service driver and aer_event tracing currently log 'PCIe Bus Type' for all errors. Update the driver and aer_event tracing to log 'CXL Bus Type' for CXL device errors. This requires the AER can identify and distinguish between PCIe errors and CXL errors. Introduce boolean 'is_cxl' to 'struct aer_err_info'. Add assignment in aer_get_device_error_info() and pci_print_aer(). Update the aer_event trace routine to accept a bus type string parameter. Signed-off-by: Terry Bowman Reviewed-by: Ira Weiny Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams Reviewed-by: Dave Jiang Acked-by: Bjorn Helgaas --- Changes in v12->v13: - Remove duplicated aer_err_info inline comments. Is already in the kernel-doc header (Ben) Changes in v11->v12: - Change aer_err_info::is_cxl to be bool a bitfield. Update structure padding. (Lukas) - Add kernel-doc for 'struct aer_err_info' (Lukas) Changes in v10->v11: - Remove duplicate call to trace_aer_event() (Shiju) - Added Dan William's and Dave Jiang's reviewed-by --- drivers/pci/pci.h | 37 ++++++++++++++++++++++++++++++------- drivers/pci/pcie/aer.c | 18 ++++++++++++------ include/ras/ras_event.h | 9 ++++++--- 3 files changed, 48 insertions(+), 16 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index d23430e3eea0..446251892bb7 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -701,31 +701,54 @@ static inline bool pci_dev_binding_disallowed(struct = pci_dev *dev) =20 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ =20 +/** + * struct aer_err_info - AER Error Information + * @dev: Devices reporting error + * @ratelimit_print: Flag to log or not log the devices' error. 0=3DNotLog= /1=3DLog + * @error_devnum: Number of devices reporting an error + * @level: printk level to use in logging + * @id: Value from register PCI_ERR_ROOT_ERR_SRC + * @severity: AER severity, 0-UNCOR Non-fatal, 1-UNCOR fatal, 2-COR + * @root_ratelimit_print: Flag to log or not log the root's error. 0=3DNot= Log/1=3DLog + * @multi_error_valid: If multiple errors are reported + * @first_error: First reported error + * @is_cxl: Bus type error: 0-PCI Bus error, 1-CXL Bus error + * @tlp_header_valid: Indicates if TLP field contains error information + * @status: COR/UNCOR error status + * @mask: COR/UNCOR mask + * @tlp: Transaction packet information + */ struct aer_err_info { struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; int error_dev_num; - const char *level; /* printk level */ + const char *level; =20 unsigned int id:16; =20 - unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ - unsigned int root_ratelimit_print:1; /* 0=3Dskip, 1=3Dprint */ + unsigned int severity:2; + unsigned int root_ratelimit_print:1; unsigned int __pad1:4; unsigned int multi_error_valid:1; =20 unsigned int first_error:5; - unsigned int __pad2:2; + unsigned int __pad2:1; + bool is_cxl:1; unsigned int tlp_header_valid:1; =20 - unsigned int status; /* COR/UNCOR Error Status */ - unsigned int mask; /* COR/UNCOR Error Mask */ - struct pcie_tlp_log tlp; /* TLP Header */ + unsigned int status; + unsigned int mask; + struct pcie_tlp_log tlp; }; =20 int aer_get_device_error_info(struct aer_err_info *info, int i); void aer_print_error(struct aer_err_info *info, int i); =20 +static inline const char *aer_err_bus(struct aer_err_info *info) +{ + return info->is_cxl ? "CXL" : "PCIe"; +} + int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, unsigned int tlp_len, bool flit, struct pcie_tlp_log *log); diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index f5f22216bb41..39e99f438563 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -868,6 +868,7 @@ void aer_print_error(struct aer_err_info *info, int i) struct pci_dev *dev; int layer, agent, id; const char *level =3D info->level; + const char *bus_type =3D aer_err_bus(info); =20 if (WARN_ON_ONCE(i >=3D AER_MAX_MULTI_ERR_DEVICES)) return; @@ -876,23 +877,23 @@ void aer_print_error(struct aer_err_info *info, int i) id =3D pci_dev_id(dev); =20 pci_dev_aer_stats_incr(dev, info); - trace_aer_event(pci_name(dev), (info->status & ~info->mask), + trace_aer_event(pci_name(dev), bus_type, (info->status & ~info->mask), info->severity, info->tlp_header_valid, &info->tlp); =20 if (!info->ratelimit_print[i]) return; =20 if (!info->status) { - pci_err(dev, "PCIe Bus Error: severity=3D%s, type=3DInaccessible, (Unreg= istered Agent ID)\n", - aer_error_severity_string[info->severity]); + pci_err(dev, "%s Bus Error: severity=3D%s, type=3DInaccessible, (Unregis= tered Agent ID)\n", + bus_type, aer_error_severity_string[info->severity]); goto out; } =20 layer =3D AER_GET_LAYER_ERROR(info->severity, info->status); agent =3D AER_GET_AGENT(info->severity, info->status); =20 - aer_printk(level, dev, "PCIe Bus Error: severity=3D%s, type=3D%s, (%s)\n", - aer_error_severity_string[info->severity], + aer_printk(level, dev, "%s Bus Error: severity=3D%s, type=3D%s, (%s)\n", + bus_type, aer_error_severity_string[info->severity], aer_error_layer[layer], aer_agent_string[agent]); =20 aer_printk(level, dev, " device [%04x:%04x] error status/mask=3D%08x/%08= x\n", @@ -926,6 +927,7 @@ EXPORT_SYMBOL_GPL(cper_severity_to_aer); void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer) { + const char *bus_type; int layer, agent, tlp_header_valid =3D 0; u32 status, mask; struct aer_err_info info =3D { @@ -946,9 +948,12 @@ void pci_print_aer(struct pci_dev *dev, int aer_severi= ty, =20 info.status =3D status; info.mask =3D mask; + info.is_cxl =3D pcie_is_cxl(dev); + + bus_type =3D aer_err_bus(&info); =20 pci_dev_aer_stats_incr(dev, &info); - trace_aer_event(pci_name(dev), (status & ~mask), + trace_aer_event(pci_name(dev), bus_type, (status & ~mask), aer_severity, tlp_header_valid, &aer->header_log); =20 if (!aer_ratelimit(dev, info.severity)) @@ -1309,6 +1314,7 @@ int aer_get_device_error_info(struct aer_err_info *in= fo, int i) /* Must reset in this function */ info->status =3D 0; info->tlp_header_valid =3D 0; + info->is_cxl =3D pcie_is_cxl(dev); =20 /* The device might not support AER */ if (!aer) diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index c8cd0f00c845..85dbafec6ad1 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -298,15 +298,17 @@ TRACE_EVENT(non_standard_event, =20 TRACE_EVENT(aer_event, TP_PROTO(const char *dev_name, + const char *bus_type, const u32 status, const u8 severity, const u8 tlp_header_valid, struct pcie_tlp_log *tlp), =20 - TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp), + TP_ARGS(dev_name, bus_type, status, severity, tlp_header_valid, tlp), =20 TP_STRUCT__entry( __string( dev_name, dev_name ) + __string( bus_type, bus_type ) __field( u32, status ) __field( u8, severity ) __field( u8, tlp_header_valid) @@ -315,6 +317,7 @@ TRACE_EVENT(aer_event, =20 TP_fast_assign( __assign_str(dev_name); + __assign_str(bus_type); __entry->status =3D status; __entry->severity =3D severity; __entry->tlp_header_valid =3D tlp_header_valid; @@ -326,8 +329,8 @@ TRACE_EVENT(aer_event, } ), =20 - TP_printk("%s PCIe Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", - __get_str(dev_name), + TP_printk("%s %s Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", + __get_str(dev_name), __get_str(bus_type), __entry->severity =3D=3D AER_CORRECTABLE ? "Corrected" : __entry->severity =3D=3D AER_FATAL ? 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:05:09.2774 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c6a2ac2-beb8-4c05-135e-08de1bc44f6c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB71.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7620 Content-Type: text/plain; charset="utf-8" CXL PCIe Port Protocol Error handling support will be added to the CXL drivers in the future. In preparation, rename the existing interfaces to support handling all CXL PCIe Port Protocol Errors. The driver's RAS support functions currently rely on a 'struct cxl_dev_state' type parameter, which is not available for CXL Port devices. However, since the same CXL RAS capability structure is needed across most CXL components and devices, a common handling approach should be adopted. To accommodate this, update the __cxl_handle_cor_ras() and __cxl_handle_ras() functions to use a `struct device` instead of `struct cxl_dev_state`. No functional changes are introduced. [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams --- Changes in v12->v13: - Added Ben's review-by --- drivers/cxl/core/core.h | 15 ++++++--------- drivers/cxl/core/ras.c | 12 ++++++------ drivers/cxl/core/ras_rch.c | 4 ++-- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index c30ab7c25a92..1a419b35fa59 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -7,6 +7,7 @@ #include #include #include +#include =20 extern const struct device_type cxl_nvdimm_bridge_type; extern const struct device_type cxl_nvdimm_type; @@ -148,23 +149,19 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_po= rt *port, #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base); -void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e); +bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); +void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); #else static inline int cxl_ras_init(void) { return 0; } - -static inline void cxl_ras_exit(void) -{ -} - -static inline bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iome= m *ras_base) +static inline void cxl_ras_exit(void) { } +static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_ba= se) { return false; } -static inline void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __= iomem *ras_base) { } +static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } #endif /* CONFIG_CXL_RAS */ =20 /* Restricted CXL Host specific RAS functions */ diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index b933030b8e1e..72908f3ced77 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -160,7 +160,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 -void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e) +void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -172,7 +172,7 @@ void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, vo= id __iomem *ras_base) status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); } } =20 @@ -197,7 +197,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base) +bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -224,7 +224,7 @@ bool cxl_handle_ras(struct cxl_dev_state *cxlds, void _= _iomem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -246,7 +246,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -275,7 +275,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); 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Tue, 4 Nov 2025 09:05:13 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 11/25] cxl/pci: Log message if RAS registers are unmapped Date: Tue, 4 Nov 2025 11:02:51 -0600 Message-ID: <20251104170305.4163840-12-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB75:EE_|IA1PR12MB6435:EE_ X-MS-Office365-Filtering-Correlation-Id: f4e31572-6986-4bf4-bfce-08de1bc45432 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:05:17.2899 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4e31572-6986-4bf4-bfce-08de1bc45432 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB75.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6435 Content-Type: text/plain; charset="utf-8" The CXL RAS handlers do not currently log if the RAS registers are unmapped. This is needed in order to help debug CXL error handling. Update the CXL driver to log a warning message if the RAS register block is unmapped during RAS error handling. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams --- Chan ges in v12->v13: - Added Bens review-by --- drivers/cxl/core/ras.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 72908f3ced77..0320c391f201 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -165,8 +165,10 @@ void cxl_handle_cor_ras(struct device *dev, void __iom= em *ras_base) void __iomem *addr; u32 status; =20 - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return; + } =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); @@ -204,8 +206,10 @@ bool cxl_handle_ras(struct device *dev, void __iomem *= ras_base) u32 status; u32 fe; =20 - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return false; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:05:25.3008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e631d0d2-509c-4c09-231b-08de1bc458f9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7927 Content-Type: text/plain; charset="utf-8" CXL currently has separate trace routines for CXL Port errors and CXL Endpoint errors. This is inconvenient for the user because they must enable 2 sets of trace routines. Make updates to the trace logging such that a single trace routine logs both CXL Endpoint and CXL Port protocol errors. Keep the trace log fields 'memdev' and 'host'. While these are not accurate for non-Endpoints the fields will remain as-is to prevent breaking userspace RAS trace consumers. Add serial number parameter to the trace logging. This is used for EPs and 0 is provided for CXL port devices without a serial number. Leave the correctable and uncorrectable trace routines' TP_STRUCT__entry() unchanged with respect to member data types and order. Below is output of correctable and uncorrectable protocol error logging. CXL Root Port and CXL Endpoint examples are included below. Root Port: cxl_aer_correctable_error: memdev=3D0000:0c:00.0 host=3Dpci0000:0c serial: = 0 status=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: memdev=3D0000:0c:00.0 host=3Dpci0000:0c serial= : 0 status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enabl= e Parity Error' Endpoint: cxl_aer_correctable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial=3D0 sta= tus=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial: 0 st= atus: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Pari= ty Error' Signed-off-by: Terry Bowman Reviewed-by: Shiju Jose Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang --- Changes in v12->v13: - Added Dave Jiang's review-by Changes in v11 -> v12: - Correct parameters to call trace_cxl_aer_correctable_error() - Add reviewed-by for Jonathan and Shiju Changes in v10->v11: - Updated CE and UCE trace routines to maintain consistent TP_Struct ABI and unchanged TP_printk() logging. --- drivers/cxl/core/core.h | 4 +-- drivers/cxl/core/ras.c | 26 ++++++++------- drivers/cxl/core/ras_rch.c | 4 +-- drivers/cxl/core/trace.h | 68 ++++++-------------------------------- 4 files changed, 29 insertions(+), 73 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 1a419b35fa59..e47ae7365ce0 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -149,8 +149,8 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port= *port, #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base= ); +void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base); #else static inline int cxl_ras_init(void) { diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 0320c391f201..599c88f0b376 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -13,7 +13,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_= dev *pdev, { u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; =20 - trace_cxl_port_aer_correctable_error(&pdev->dev, status); + trace_cxl_aer_correctable_error(&pdev->dev, status, 0); } =20 static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev, @@ -28,8 +28,8 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pc= i_dev *pdev, else fe =3D status; =20 - trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe, + ras_cap.header_log, 0); } =20 static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd, @@ -37,7 +37,7 @@ static void cxl_cper_trace_corr_prot_err(struct cxl_memde= v *cxlmd, { u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; =20 - trace_cxl_aer_correctable_error(cxlmd, status); + trace_cxl_aer_correctable_error(&cxlmd->dev, status, cxlmd->cxlds->serial= ); } =20 static void @@ -45,6 +45,7 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, struct cxl_ras_capability_regs ras_cap) { u32 status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; u32 fe; =20 if (hweight32(status) > 1) @@ -53,8 +54,9 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, else fe =3D status; =20 - trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe, + ras_cap.header_log, + cxlds->serial); } =20 static int match_memdev_by_parent(struct device *dev, const void *uport) @@ -160,7 +162,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) +void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; u32 status; @@ -174,7 +176,7 @@ void cxl_handle_cor_ras(struct device *dev, void __iome= m *ras_base) status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + trace_cxl_aer_correctable_error(dev, status, serial); } } =20 @@ -199,7 +201,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -228,7 +230,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *r= as_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -250,7 +252,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -279,7 +281,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras= ); } =20 =20 diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index 4d2babe8d206..421dd1bcfc9c 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -114,7 +114,7 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxl= ds) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, 0, dport->regs.ras); else - cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_ras(&cxlds->cxlmd->dev, 0, dport->regs.ras); } diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index a972e4ef1936..69f8a0efd924 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -48,40 +48,13 @@ { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ ) =20 -TRACE_EVENT(cxl_port_aer_uncorrectable_error, - TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), - TP_ARGS(dev, status, fe, hl), - TP_STRUCT__entry( - __string(device, dev_name(dev)) - __string(host, dev_name(dev->parent)) - __field(u32, status) - __field(u32, first_error) - __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) - ), - TP_fast_assign( - __assign_str(device); - __assign_str(host); - __entry->status =3D status; - __entry->first_error =3D fe; - /* - * Embed the 512B headerlog data for user app retrieval and - * parsing, but no need to print this in the trace buffer. - */ - memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); - ), - TP_printk("device=3D%s host=3D%s status: '%s' first_error: '%s'", - __get_str(device), __get_str(host), - show_uc_errs(__entry->status), - show_uc_errs(__entry->first_error) - ) -); - TRACE_EVENT(cxl_aer_uncorrectable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), - TP_ARGS(cxlmd, status, fe, hl), + TP_PROTO(const struct device *cxlmd, u32 status, u32 fe, u32 *hl, + u64 serial), + TP_ARGS(cxlmd, status, fe, hl, serial), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(memdev, dev_name(cxlmd)) + __string(host, dev_name(cxlmd->parent)) __field(u64, serial) __field(u32, status) __field(u32, first_error) @@ -90,7 +63,7 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, TP_fast_assign( __assign_str(memdev); __assign_str(host); - __entry->serial =3D cxlmd->cxlds->serial; + __entry->serial =3D serial; __entry->status =3D status; __entry->first_error =3D fe; /* @@ -124,38 +97,19 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ ) =20 -TRACE_EVENT(cxl_port_aer_correctable_error, - TP_PROTO(struct device *dev, u32 status), - TP_ARGS(dev, status), - TP_STRUCT__entry( - __string(device, dev_name(dev)) - __string(host, dev_name(dev->parent)) - __field(u32, status) - ), - TP_fast_assign( - __assign_str(device); - __assign_str(host); - __entry->status =3D status; - ), - TP_printk("device=3D%s host=3D%s status=3D'%s'", - __get_str(device), __get_str(host), - show_ce_errs(__entry->status) - ) -); - TRACE_EVENT(cxl_aer_correctable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), - TP_ARGS(cxlmd, status), + TP_PROTO(const struct device *cxlmd, u32 status, u64 serial), + TP_ARGS(cxlmd, status, serial), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(memdev, dev_name(cxlmd)) + __string(host, dev_name(cxlmd->parent)) __field(u64, serial) __field(u32, status) ), TP_fast_assign( __assign_str(memdev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:05:36.2954 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45977830-92df-4a95-c103-08de1bc45f86 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7458 Content-Type: text/plain; charset="utf-8" Update cxl_handle_cor_ras() to exit early in the case there is no RAS errors detected after applying the status mask. This change will make the correctable handler's implementation consistent with the uncorrectable handler, cxl_handle_ras(). Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham Reviewed-by: Alejandro Lucero Reviewed-by: Dan Williams --- Changes v12->v13: - Added Ben's review-by Changes v11->v12: - None Changes v10->v11: - Added Dave Jiang and Jonathan Cameron's review-by - Changes moved to core/ras.c --- drivers/cxl/core/ras.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 599c88f0b376..246dfe56617a 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -174,10 +174,11 @@ void cxl_handle_cor_ras(struct device *dev, u64 seria= l, void __iomem *ras_base) =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(dev, status, serial); - } + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) + return; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:05:48.1783 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5db1c65e-0b8e-4c05-ea75-08de1bc4669b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8835 Content-Type: text/plain; charset="utf-8" CXL Endpoint (EP) Ports may include Root Ports (RP) or Downstream Switch Ports (DSP). CXL RPs and DSPs contain RAS registers that require memory mapping to enable RAS logging. This initialization is currently missing and must be added for CXL RPs and DSPs. Update cxl_dport_init_ras_reporting() to support RP and DSP RAS mapping. Add alongside the existing Restricted CXL Host Downstream Port RAS mapping. Update cxl_endpoint_port_probe() to invoke cxl_dport_init_ras_reporting(). This will initiate the RAS mapping for CXL RPs and DSPs when each CXL EP is created and added to the EP port. Make a call to cxl_port_setup_regs() in cxl_port_add(). This will probe the Upstream Port's CXL capabilities' physical location to be used in mapping the RAS registers. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang >=20 Reviewed-by: Jonathan Cameron --- Changes in v12->v13: - Change as result of dport delay fix. No longer need switchport and endport approach. (Terry) Changes in v11->v12: - Add check for dport_parent->rch before calling cxl_dport_init_ras_reporti= ng(). RCH dports are initialized from cxl_dport_init_ras_reporting cxl_mem_probe(= ). Changes in v10->v11: - Use local pointer for readability in cxl_switch_port_init_ras() (Jonathan= Cameron) - Rename port to be ep in cxl_endpoint_port_init_ras() (Dave Jiang) - Rename dport to be parent_dport in cxl_endpoint_port_init_ras() and cxl_switch_port_init_ras() (Dave Jiang) - Port helper changes were in cxl/port.c, now in core/ras.c (Dave Jiang) --- drivers/cxl/core/port.c | 4 ++++ drivers/cxl/core/ras.c | 12 ++++++++++++ drivers/cxl/cxl.h | 2 ++ drivers/cxl/cxlpci.h | 4 ++++ drivers/cxl/mem.c | 3 ++- 5 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 8128fd2b5b31..48f6a1492544 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1194,6 +1194,8 @@ __devm_cxl_add_dport(struct cxl_port *port, struct de= vice *dport_dev, return ERR_PTR(rc); } port->component_reg_phys =3D CXL_RESOURCE_NONE; + if (!is_cxl_endpoint(port) && dev_is_pci(port->uport_dev)) + cxl_uport_init_ras_reporting(port, &port->dev); } =20 get_device(dport_dev); @@ -1623,6 +1625,8 @@ static struct cxl_dport *cxl_port_add_dport(struct cx= l_port *port, =20 cxl_switch_parse_cdat(new_dport); =20 + cxl_dport_init_ras_reporting(new_dport, &port->dev); + if (ida_is_empty(&port->decoder_ida)) { rc =3D devm_cxl_switch_port_decoders_setup(port); if (rc) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 246dfe56617a..19d9ffe885bf 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -162,6 +162,18 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 +void cxl_uport_init_ras_reporting(struct cxl_port *port, + struct device *host) +{ + struct cxl_register_map *map =3D &port->reg_map; + + map->host =3D host; + if (cxl_map_component_regs(map, &port->uport_regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(&port->dev, "Failed to map RAS capability\n"); +} +EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); + void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 259ed4b676e1..b7654d40dc9e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -599,6 +599,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @uport_regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing @@ -620,6 +621,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs uport_regs; int nr_dports; int hdm_end; int commit_end; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 0c8b6ee7b6de..a0a491e7b5b9 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -83,6 +83,8 @@ void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); +void cxl_uport_init_ras_reporting(struct cxl_port *port, + struct device *host); #else static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } =20 @@ -94,6 +96,8 @@ static inline pci_ers_result_t cxl_error_detected(struct = pci_dev *pdev, =20 static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host) { } +static inline void cxl_uport_init_ras_reporting(struct cxl_port *port, + struct device *host) { } #endif =20 #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 6e6777b7bafb..d2155f45240d 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -166,7 +166,8 @@ static int cxl_mem_probe(struct device *dev) else endpoint_parent =3D &parent_port->dev; =20 - cxl_dport_init_ras_reporting(dport, dev); + if (dport->rch) + cxl_dport_init_ras_reporting(dport, dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:05:58.8169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7eab398f-8773-4b30-bf72-08de1bc46cf3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7711 Content-Type: text/plain; charset="utf-8" The CXL driver's error handling for uncorrectable errors (UCE) will be updated in the future. A required change is for the error handlers to to force a system panic when a UCE is detected. Introduce PCI_ERS_RESULT_PANIC as a 'enum pci_ers_result' type. This will be used by CXL UCE fatal and non-fatal recovery in future patches. Update PCIe recovery documentation with details of PCI_ERS_RESULT_PANIC. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams --- Changes in v12->v13: - Add Dave Jiang's, Jonathan's, Ben's review-by - Typo fix (Ben) Changes v11 -> v12: - Documentation requested (Lukas) --- Documentation/PCI/pci-error-recovery.rst | 6 ++++++ include/linux/pci.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/Documentation/PCI/pci-error-recovery.rst b/Documentation/PCI/p= ci-error-recovery.rst index 5df481ac6193..83505a585116 100644 --- a/Documentation/PCI/pci-error-recovery.rst +++ b/Documentation/PCI/pci-error-recovery.rst @@ -102,6 +102,8 @@ Possible return values are:: PCI_ERS_RESULT_NEED_RESET, /* Device driver wants slot to be reset. */ PCI_ERS_RESULT_DISCONNECT, /* Device has completely failed, is unrecove= rable */ PCI_ERS_RESULT_RECOVERED, /* Device driver is fully recovered and oper= ational */ + PCI_ERS_RESULT_NO_AER_DRIVER, /* No AER capabilities registered for the = driver */ + PCI_ERS_RESULT_PANIC, /* System is unstable, panic. Is CXL specifi= c */ }; =20 A driver does not have to implement all of these callbacks; however, @@ -116,6 +118,10 @@ The actual steps taken by a platform to recover from a= PCI error event will be platform-dependent, but will follow the general sequence described below. =20 +PCI_ERS_RESULT_PANIC is currently unique to CXL and handled in CXL +cxl_do_recovery(). The PCI pcie_do_recovery() routine does not report or +handle PCI_ERS_RESULT_PANIC. + STEP 0: Error Event ------------------- A PCI bus error is detected by the PCI hardware. On powerpc, the slot diff --git a/include/linux/pci.h b/include/linux/pci.h index 5c4759078d2f..cffa5535f28d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -890,6 +890,9 @@ enum pci_ers_result { =20 /* No AER capabilities registered for the driver */ PCI_ERS_RESULT_NO_AER_DRIVER =3D (__force pci_ers_result_t) 6, + + /* System is unstable, panic. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:06:10.9312 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb99f11d-44d8-4724-8d77-08de1bc4742b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9066 Content-Type: text/plain; charset="utf-8" CXL virtual hierarchy (VH) RAS handling for CXL Port devices will be added soon. This requires a notification mechanism for the AER driver to share the AER interrupt with the CXL driver. The notification will be used as an indication for the CXL drivers to handle and log the CXL RAS errors. Note, 'CXL protocol error' terminology will refer to CXL VH and not CXL RCH errors unless specifically noted going forward. Introduce a new file in the AER driver to handle the CXL protocol errors named pci/pcie/aer_cxl_vh.c. Add a kfifo work queue to be used by the AER and CXL drivers. The AER driver will be the sole kfifo producer adding work and the cxl_core will be the sole kfifo consumer removing work. Add the boilerplate kfifo support. Encapsulate the kfifo, RW semaphore, and work pointer in a single structure. Add CXL work queue handler registration functions in the AER driver. Export the functions allowing CXL driver to access. Implement registration functions for the CXL driver to assign or clear the work handler function. Synchronize accesses using the RW semaphore. Introduce 'struct cxl_proto_err_work_data' to serve as the kfifo work data. This will contain a reference to the erring PCI device and the error severity. This will be used when the work is dequeued by the cxl_core drive= r. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang --- Changes in v12->v13: - Added Dave Jiang's review-by - Update error message (Ben) Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/pci/pci.h | 4 ++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 25 ++------- drivers/pci/pcie/aer_cxl_vh.c | 95 +++++++++++++++++++++++++++++++++++ include/linux/aer.h | 17 +++++++ 5 files changed, 121 insertions(+), 21 deletions(-) create mode 100644 drivers/pci/pcie/aer_cxl_vh.c diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 446251892bb7..a398e489318c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1330,8 +1330,12 @@ static inline void cxl_rch_enable_rcec(struct pci_de= v *rcec) { } =20 #ifdef CONFIG_CXL_RAS bool is_internal_error(struct aer_err_info *info); +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info); +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info); #else static inline bool is_internal_error(struct aer_err_info *info) { return f= alse; } +static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info = *info) { return false; } +static inline void cxl_forward_error(struct pci_dev *pdev, struct aer_err_= info *info) { } #endif =20 #endif /* DRIVERS_PCI_H */ diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 970e7cbc5b34..72992b3ea417 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o obj-$(CONFIG_CXL_RCH_RAS) +=3D aer_cxl_rch.o +obj-$(CONFIG_CXL_RAS) +=3D aer_cxl_vh.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 39e99f438563..e806fa05280b 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1123,8 +1123,6 @@ static bool find_source_device(struct pci_dev *parent, return true; } =20 -#ifdef CONFIG_PCIEAER_CXL - /** * pci_aer_unmask_internal_errors - unmask internal errors * @dev: pointer to the pci_dev data structure @@ -1150,24 +1148,6 @@ void pci_aer_unmask_internal_errors(struct pci_dev *= dev) } EXPORT_SYMBOL_GPL(pci_aer_unmask_internal_errors); =20 -bool cxl_error_is_native(struct pci_dev *dev) -{ - struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); - - return (pcie_ports_native || host->native_aer); -} -EXPORT_SYMBOL_NS_GPL(cxl_error_is_native, "CXL"); - -bool is_internal_error(struct aer_err_info *info) -{ - if (info->severity =3D=3D AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} -EXPORT_SYMBOL_NS_GPL(is_internal_error, "CXL"); -#endif /* CONFIG_CXL_RAS */ - /** * pci_aer_handle_error - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device @@ -1204,7 +1184,10 @@ static void pci_aer_handle_error(struct pci_dev *dev= , struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { cxl_rch_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (is_cxl_error(dev, info)) + cxl_forward_error(dev, info); + else + pci_aer_handle_error(dev, info); pci_dev_put(dev); } =20 diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c new file mode 100644 index 000000000000..5dbc81341dc4 --- /dev/null +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include "../pci.h" + +#define CXL_ERROR_SOURCES_MAX 128 + +struct cxl_proto_err_kfifo { + struct work_struct *work; + struct rw_semaphore rw_sema; + DECLARE_KFIFO(fifo, struct cxl_proto_err_work_data, + CXL_ERROR_SOURCES_MAX); +}; + +static struct cxl_proto_err_kfifo cxl_proto_err_kfifo =3D { + .rw_sema =3D __RWSEM_INITIALIZER(cxl_proto_err_kfifo.rw_sema) +}; + +bool cxl_error_is_native(struct pci_dev *dev) +{ + struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); + + return (pcie_ports_native || host->native_aer); +} +EXPORT_SYMBOL_NS_GPL(cxl_error_is_native, "CXL"); + +bool is_internal_error(struct aer_err_info *info) +{ + if (info->severity =3D=3D AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; + + return info->status & PCI_ERR_UNC_INTN; +} +EXPORT_SYMBOL_NS_GPL(is_internal_error, "CXL"); + +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + if (!info || !info->is_cxl) + return false; + + if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + return false; + + return is_internal_error(info); +} +EXPORT_SYMBOL_NS_GPL(is_cxl_error, "CXL"); + +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + struct cxl_proto_err_work_data wd =3D (struct cxl_proto_err_work_data) { + .severity =3D info->severity, + .pdev =3D pdev + }; + + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + + if (!cxl_proto_err_kfifo.work) { + dev_warn_once(&pdev->dev, "CXL driver is unregistered. Unable to forward= error."); + return; + } + + if (!kfifo_put(&cxl_proto_err_kfifo.fifo, wd)) { + dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo overflow\n"); + return; + } + + schedule_work(cxl_proto_err_kfifo.work); +} +EXPORT_SYMBOL_NS_GPL(cxl_forward_error, "CXL"); + +void cxl_register_proto_err_work(struct work_struct *work) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + cxl_proto_err_kfifo.work =3D work; +} +EXPORT_SYMBOL_NS_GPL(cxl_register_proto_err_work, "CXL"); + +void cxl_unregister_proto_err_work(void) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + cxl_proto_err_kfifo.work =3D NULL; +} +EXPORT_SYMBOL_NS_GPL(cxl_unregister_proto_err_work, "CXL"); + +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd) +{ + guard(rwsem_read)(&cxl_proto_err_kfifo.rw_sema); + return kfifo_get(&cxl_proto_err_kfifo.fifo, wd); +} +EXPORT_SYMBOL_NS_GPL(cxl_proto_err_kfifo_get, "CXL"); diff --git a/include/linux/aer.h b/include/linux/aer.h index 2ef820563996..6b2c87d1b5b6 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -10,6 +10,7 @@ =20 #include #include +#include =20 #define AER_NONFATAL 0 #define AER_FATAL 1 @@ -53,6 +54,16 @@ struct aer_capability_regs { u16 uncor_err_source; }; =20 +/** + * struct cxl_proto_err_work_data - Error information used in CXL error ha= ndling + * @severity: AER severity + * @pdev: PCI device detecting the error + */ +struct cxl_proto_err_work_data { + int severity; + struct pci_dev *pdev; +}; + #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); @@ -68,8 +79,14 @@ static inline void pci_aer_unmask_internal_errors(struct= pci_dev *dev) { } =20 #ifdef CONFIG_CXL_RAS bool cxl_error_is_native(struct pci_dev *dev); +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd); +void cxl_register_proto_err_work(struct work_struct *work); +void cxl_unregister_proto_err_work(void); #else static inline bool cxl_error_is_native(struct pci_dev *dev) { return false= ; } +static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *= wd) { return 0; } +static inline void cxl_register_proto_err_work(struct work_struct *work) {= } +static inline void cxl_unregister_proto_err_work(void) { } #endif =20 void pci_print_aer(struct pci_dev *dev, int aer_severity, --=20 2.34.1 From nobody Wed Dec 17 08:59:20 2025 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010038.outbound.protection.outlook.com [52.101.46.38]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D2FA33B951; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:06:21.1411 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18aada6c-8811-4b1d-85c9-08de1bc47a41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9730 Content-Type: text/plain; charset="utf-8" CXL devices handle protocol errors via driver-specific callbacks rather than the generic pci_driver::err_handlers by default. The callbacks are implemented in the cxl_pci driver and are not part of struct pci_driver, so cxl_core must verify that a device is actually bound to the cxl_pci module's driver before invoking the callbacks (the device could be bound to another driver, e.g. VFIO). However, cxl_core can not reference symbols in the cxl_pci module because it creates a circular dependency. This prevents cxl_core from checking the EP's bound driver and calling the callbacks. To fix this, move drivers/cxl/pci.c into drivers/cxl/core/pci_drv.c and build it as part of the cxl_core module. Compile into cxl_core using CXL_PCI and CXL_CORE Kconfig dependencies. This removes the standalone cxl_pci module, consolidates the cxl_pci driver code into cxl_core, and eliminates the circular dependency so cxl_core can safely perform bound-driver checks and invoke the CXL PCI callbacks. Introduce cxl_pci_drv_bound() to return boolean depending on if the PCI EP parameter is bound to a CXL driver instance. This will be used in future patch when dequeuing work from the kfifo. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham Reviewed-by: Jonathan Cameron --- Changes in v12->v13; - Add Dave Jiang's review-by. Changes in v11->v12: - Add device_lock_assert() in cxl_pci_drv_bound() (Dave Jiang) - Add Jonathan's review-by Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/cxl/Kconfig | 6 +++--- drivers/cxl/Makefile | 2 -- drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 9 +++++++++ drivers/cxl/{pci.c =3D> core/pci_drv.c} | 21 +++++++++++++-------- drivers/cxl/core/port.c | 3 +++ tools/testing/cxl/Kbuild | 1 + 7 files changed, 30 insertions(+), 13 deletions(-) rename drivers/cxl/{pci.c =3D> core/pci_drv.c} (99%) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index ffe6ad981434..360c78fa7e97 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -20,7 +20,7 @@ menuconfig CXL_BUS if CXL_BUS =20 config CXL_PCI - tristate "PCI manageability" + bool "PCI manageability" default CXL_BUS help The CXL specification defines a "CXL memory device" sub-class in the @@ -29,12 +29,12 @@ config CXL_PCI memory to be mapped into the system address map (Host-managed Device Memory (HDM)). =20 - Say 'y/m' to enable a driver that will attach to CXL memory expander + Say 'y' to enable a driver that will attach to CXL memory expander devices enumerated by the memory device class code for configuration and management primarily via the mailbox interface. See Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more details. =20 - If unsure say 'm'. + If unsure say 'y'. =20 config CXL_MEM_RAW_COMMANDS bool "RAW Command Interface for Memory Devices" diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index 2caa90fa4bf2..ff6add88b6ae 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -12,10 +12,8 @@ obj-$(CONFIG_CXL_PORT) +=3D cxl_port.o obj-$(CONFIG_CXL_ACPI) +=3D cxl_acpi.o obj-$(CONFIG_CXL_PMEM) +=3D cxl_pmem.o obj-$(CONFIG_CXL_MEM) +=3D cxl_mem.o -obj-$(CONFIG_CXL_PCI) +=3D cxl_pci.o =20 cxl_port-y :=3D port.o cxl_acpi-y :=3D acpi.o cxl_pmem-y :=3D pmem.o security.o cxl_mem-y :=3D mem.o -cxl_pci-y :=3D pci.o diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index fa1d4aed28b9..2937d0ddcce2 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -21,3 +21,4 @@ cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o cxl_core-$(CONFIG_CXL_RAS) +=3D ras.o cxl_core-$(CONFIG_CXL_RCH_RAS) +=3D ras_rch.o +cxl_core-$(CONFIG_CXL_PCI) +=3D pci_drv.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index e47ae7365ce0..61c6726744d7 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -195,4 +195,13 @@ int cxl_set_feature(struct cxl_mailbox *cxl_mbox, cons= t uuid_t *feat_uuid, u16 *return_code); #endif =20 +#ifdef CONFIG_CXL_PCI +bool cxl_pci_drv_bound(struct pci_dev *pdev); +int cxl_pci_driver_init(void); +void cxl_pci_driver_exit(void); +#else +static inline bool cxl_pci_drv_bound(struct pci_dev *pdev) { return false;= }; +static inline int cxl_pci_driver_init(void) { return 0; } +static inline void cxl_pci_driver_exit(void) { } +#endif #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/core/pci_drv.c similarity index 99% rename from drivers/cxl/pci.c rename to drivers/cxl/core/pci_drv.c index bd95be1f3d5c..06f2fd993cb0 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/core/pci_drv.c @@ -1131,6 +1131,17 @@ static struct pci_driver cxl_pci_driver =3D { }, }; =20 +bool cxl_pci_drv_bound(struct pci_dev *pdev) +{ + device_lock_assert(&pdev->dev); + + if (pdev->driver !=3D &cxl_pci_driver) + pr_err_ratelimited("%s device not bound to CXL PCI driver\n", + pci_name(pdev)); + + return (pdev->driver =3D=3D &cxl_pci_driver); +} + #define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0) static void cxl_handle_cper_event(enum cxl_event_type ev_type, struct cxl_cper_event_rec *rec) @@ -1177,7 +1188,7 @@ static void cxl_cper_work_fn(struct work_struct *work) } static DECLARE_WORK(cxl_cper_work, cxl_cper_work_fn); =20 -static int __init cxl_pci_driver_init(void) +int __init cxl_pci_driver_init(void) { int rc; =20 @@ -1192,15 +1203,9 @@ static int __init cxl_pci_driver_init(void) return rc; } =20 -static void __exit cxl_pci_driver_exit(void) +void cxl_pci_driver_exit(void) { cxl_cper_unregister_work(&cxl_cper_work); cancel_work_sync(&cxl_cper_work); pci_unregister_driver(&cxl_pci_driver); } - -module_init(cxl_pci_driver_init); -module_exit(cxl_pci_driver_exit); -MODULE_DESCRIPTION("CXL: PCI manageability"); -MODULE_LICENSE("GPL v2"); -MODULE_IMPORT_NS("CXL"); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 48f6a1492544..b70e1b505b5c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2507,6 +2507,8 @@ static __init int cxl_core_init(void) if (rc) goto err_ras; =20 + cxl_pci_driver_init(); + return 0; =20 err_ras: @@ -2522,6 +2524,7 @@ static __init int cxl_core_init(void) =20 static void cxl_core_exit(void) { + cxl_pci_driver_exit(); cxl_ras_exit(); cxl_region_exit(); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:06:32.1356 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd0a7c81-de4a-4208-48b4-08de1bc480cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9515 Content-Type: text/plain; charset="utf-8" The CXL protocol error handlers use scoped_guard() to guarantee access to the underlying CXL memory device. Improve readability and reduce complexity by changing the current scoped_guard() to be guard(). Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang >=20 Reviewed-by: Jonathan Cameron --- Changes in v12->v13: - New patch --- drivers/cxl/core/ras.c | 53 +++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 19d9ffe885bf..cb712772de5c 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -254,19 +254,19 @@ void cxl_cor_error_detected(struct pci_dev *pdev) struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); struct device *dev =3D &cxlds->cxlmd->dev; =20 - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } - - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); + guard(device)(dev); =20 - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return; } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 @@ -278,25 +278,24 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *p= dev, struct device *dev =3D &cxlmd->dev; bool ue; =20 - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } + guard(device)(dev); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras= ); + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return PCI_ERS_RESULT_DISCONNECT; } =20 + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + /* + * A frozen channel indicates an impending reset which is fatal to + * CXL.mem operation, and will likely crash the system. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:06:43.5500 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03d45588-a71e-4bbf-f7be-08de1bc487aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4455 Content-Type: text/plain; charset="utf-8" CXL Endpoint protocol errors are currently handled by generic PCI error handlers. However, uncorrectable errors (UCEs) require CXL.mem protocol- specific handling logic that the PCI handlers cannot provide. Add dedicated CXL protocol error handlers for CXL Endpoints. Rename the existing cxl_error_handlers to pci_error_handlers to better reflect their purpose and maintain naming consistency. Update the PCI error handlers to invoke the new CXL protocol handlers when the endpoint is operating in CXL.mem mode. Implement cxl_handle_ras() to return PCI_ERS_RESULT_NONE or PCI_ERS_RESULT_PANIC. Remove unnecessary result checks from the previous endpoint UCE handler since CXL UCE recovery is not implemented in this patch. Add device lock assertions to protect against concurrent device or RAS register removal during error handling. Two devices require locking for CXL endpoints: 1. The PCI device (pdev->dev) - RAS registers are allocated and mapped using devm_* functions with this device as the host. Locking prevents the RAS registers from being unmapped until after error handling completes. 2. The CXL memory device (cxlmd->dev) - Holds a reference to the RAS registers accessed during error handling. Locking prevents the memory device and its RAS register references from being removed during error handling. The lock assertions added here will be satisfied by device locks introduced in a subsequent patch. A future patch will extend the CXL UCE handler to support full UCE recovery. Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan --- Changes in v12->v13: - Update commit messaqge (Terry) - Updated all the implemetnation and commit message. (Terry) - Refactored cxl_cor_error_detected()/cxl_error_detected() to remove pdev (Dave Jiang) Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/cxl/core/core.h | 22 +++++++-- drivers/cxl/core/pci_drv.c | 9 ++-- drivers/cxl/core/ras.c | 97 +++++++++++++++++++++++--------------- drivers/cxl/cxlpci.h | 11 ----- 4 files changed, 82 insertions(+), 57 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 61c6726744d7..b2c0ccd6803f 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -149,19 +149,33 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_po= rt *port, #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base= ); +pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, + void __iomem *ras_base); void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base); +pci_ers_result_t cxl_error_detected(struct device *dev); +void cxl_cor_error_detected(struct device *dev); +pci_ers_result_t pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error); +void pci_cor_error_detected(struct pci_dev *pdev); #else static inline int cxl_ras_init(void) { return 0; } static inline void cxl_ras_exit(void) { } -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_ba= se) +static inline pci_ers_result_t cxl_handle_ras(struct device *dev, u64 seri= al, + void __iomem *ras_base) { - return false; + return PCI_ERS_RESULT_NONE; } -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } +static inline void cxl_handle_cor_ras(struct device *dev, u64 serial, + void __iomem *ras_base) { } +static inline pci_ers_result_t pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error) +{ + return PCI_ERS_RESULT_NONE; +} +static inline void pci_cor_error_detected(struct pci_dev *pdev) { } #endif /* CONFIG_CXL_RAS */ =20 /* Restricted CXL Host specific RAS functions */ diff --git a/drivers/cxl/core/pci_drv.c b/drivers/cxl/core/pci_drv.c index 06f2fd993cb0..bc3c959f7eb6 100644 --- a/drivers/cxl/core/pci_drv.c +++ b/drivers/cxl/core/pci_drv.c @@ -16,6 +16,7 @@ #include "cxlpci.h" #include "cxl.h" #include "pmu.h" +#include "core/core.h" =20 /** * DOC: cxl pci @@ -1112,11 +1113,11 @@ static void cxl_reset_done(struct pci_dev *pdev) } } =20 -static const struct pci_error_handlers cxl_error_handlers =3D { - .error_detected =3D cxl_error_detected, +static const struct pci_error_handlers pci_error_handlers =3D { + .error_detected =3D pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, - .cor_error_detected =3D cxl_cor_error_detected, + .cor_error_detected =3D pci_cor_error_detected, .reset_done =3D cxl_reset_done, }; =20 @@ -1124,7 +1125,7 @@ static struct pci_driver cxl_pci_driver =3D { .name =3D KBUILD_MODNAME, .id_table =3D cxl_mem_pci_tbl, .probe =3D cxl_pci_probe, - .err_handler =3D &cxl_error_handlers, + .err_handler =3D &pci_error_handlers, .dev_groups =3D cxl_rcd_groups, .driver =3D { .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index cb712772de5c..beb142054bda 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -128,6 +128,11 @@ void cxl_ras_exit(void) cancel_work_sync(&cxl_cper_prot_err_work); } =20 +static bool is_pcie_endpoint(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT; +} + static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -214,7 +219,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) +pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, void __iom= em *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -223,13 +228,13 @@ bool cxl_handle_ras(struct device *dev, u64 serial, v= oid __iomem *ras_base) =20 if (!ras_base) { dev_warn_once(dev, "CXL RAS register block is not mapped"); - return false; + return PCI_ERS_RESULT_NONE; } =20 addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status =3D readl(addr); if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; + return PCI_ERS_RESULT_NONE; =20 /* If multiple errors, log header points to first error from ctrl reg */ if (hweight32(status) > 1) { @@ -246,18 +251,19 @@ bool cxl_handle_ras(struct device *dev, u64 serial, v= oid __iomem *ras_base) trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 - return true; + return PCI_ERS_RESULT_PANIC; } =20 -void cxl_cor_error_detected(struct pci_dev *pdev) +void cxl_cor_error_detected(struct device *dev) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct device *dev =3D &cxlds->cxlmd->dev; + struct cxl_memdev *cxlmd =3D to_cxl_memdev(dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; =20 - guard(device)(dev); + device_lock_assert(cxlds->dev); + device_lock_assert(&cxlmd->dev); =20 if (!dev->driver) { - dev_warn(&pdev->dev, + dev_warn(cxlds->dev, "%s: memdev disabled, abort error handling\n", dev_name(dev)); return; @@ -270,18 +276,31 @@ void cxl_cor_error_detected(struct pci_dev *pdev) } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +void pci_cor_error_detected(struct pci_dev *pdev) +{ + struct cxl_dev_state *cxlds; + + device_lock_assert(&pdev->dev); + if (!cxl_pci_drv_bound(pdev)) + return; + + cxlds =3D pci_get_drvdata(pdev); + guard(device)(&cxlds->cxlmd->dev); + + cxl_cor_error_detected(&pdev->dev); +} +EXPORT_SYMBOL_NS_GPL(pci_cor_error_detected, "CXL"); + +pci_ers_result_t cxl_error_detected(struct device *dev) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; + struct cxl_memdev *cxlmd =3D to_cxl_memdev(dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; =20 - guard(device)(dev); + device_lock_assert(cxlds->dev); + device_lock_assert(&cxlmd->dev); =20 if (!dev->driver) { - dev_warn(&pdev->dev, + dev_warn(cxlds->dev, "%s: memdev disabled, abort error handling\n", dev_name(dev)); return PCI_ERS_RESULT_DISCONNECT; @@ -289,32 +308,34 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *p= dev, =20 if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); + /* * A frozen channel indicates an impending reset which is fatal to * CXL.mem operation, and will likely crash the system. On the off * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; + return cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); } EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); + +pci_ers_result_t pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error) +{ + struct cxl_dev_state *cxlds; + pci_ers_result_t rc; + + device_lock_assert(&pdev->dev); + if (!cxl_pci_drv_bound(pdev)) + return PCI_ERS_RESULT_NONE; + + cxlds =3D pci_get_drvdata(pdev); + guard(device)(&cxlds->cxlmd->dev); + + rc =3D cxl_error_detected(&cxlds->cxlmd->dev); + if (rc =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(pci_error_detected, "CXL"); diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index a0a491e7b5b9..3526e6d75f79 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -79,21 +79,10 @@ struct cxl_dev_state; void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS -void cxl_cor_error_detected(struct pci_dev *pdev); -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state); void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); void cxl_uport_init_ras_reporting(struct cxl_port *port, struct device *host); #else -static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } - -static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) -{ - return PCI_ERS_RESULT_NONE; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:06:54.2852 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f59a76e7-35c3-4119-ca3d-08de1bc48e10 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002319.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9616 Content-Type: text/plain; charset="utf-8" Add CXL protocol error handlers for CXL Port devices (Root Ports, Downstream Ports, and Upstream Ports). Implement cxl_port_cor_error_detecte= d() and cxl_port_error_detected() to handle correctable and uncorrectable errors respectively. Introduce cxl_get_ras_base() to retrieve the cached RAS register base address for a given CXL port. This function supports CXL Root Ports, Downstream Ports, and Upstream Ports by returning their previously mapped RAS register addresses. Add device lock assertions to protect against concurrent device or RAS register removal during error handling. The port error handlers require two device locks: 1. The port's CXL parent device - RAS registers are mapped using devm_* functions with the parent port as the host. Locking the parent prevents the RAS registers from being unmapped during error handling. 2. The PCI device (pdev->dev) - Locking prevents concurrent modifications to the PCI device structure during error handling. The lock assertions added here will be satisfied by device locks introduced in a subsequent patch. Introduce get_pci_cxl_host_dev() to return the device responsible for managing the RAS register mapping. This function increments the reference count on the host device to prevent premature resource release during error handling. The caller is responsible for decrementing the reference count. For CXL endpoints, which manage resources without a separate host device, this function returns NULL. Update the AER driver's is_cxl_error() to recognize CXL Port devices in addition to CXL Endpoints, as both now have CXL-specific error handlers. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang --- Changes in v12->v13: - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue patch (Terry) - Remove EP case in cxl_get_ras_base(), not used. (Terry) - Remove check for dport->dport_dev (Dave) - Remove whitespace (Terry) Changes in v11->v12: - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and pci_to_cxl_dev() - Change cxl_error_detected() -> cxl_cor_error_detected() - Remove NULL variable assignments - Replace bus_find_device() with find_cxl_port_by_uport() for upstream port searches. Changes in v10->v11: - None --- drivers/cxl/core/core.h | 10 +++++++ drivers/cxl/core/port.c | 7 ++--- drivers/cxl/core/ras.c | 49 +++++++++++++++++++++++++++++++++++ drivers/pci/pcie/aer_cxl_vh.c | 5 +++- 4 files changed, 67 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index b2c0ccd6803f..046ec65ed147 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -157,6 +157,8 @@ void cxl_cor_error_detected(struct device *dev); pci_ers_result_t pci_error_detected(struct pci_dev *pdev, pci_channel_state_t error); void pci_cor_error_detected(struct pci_dev *pdev); +pci_ers_result_t cxl_port_error_detected(struct device *dev); +void cxl_port_cor_error_detected(struct device *dev); #else static inline int cxl_ras_init(void) { @@ -176,6 +178,11 @@ static inline pci_ers_result_t pci_error_detected(stru= ct pci_dev *pdev, return PCI_ERS_RESULT_NONE; } static inline void pci_cor_error_detected(struct pci_dev *pdev) { } +static inline void cxl_port_cor_error_detected(struct device *dev) { } +static inline pci_ers_result_t cxl_port_error_detected(struct device *dev) +{ + return PCI_ERS_RESULT_NONE; +} #endif /* CONFIG_CXL_RAS */ =20 /* Restricted CXL Host specific RAS functions */ @@ -190,6 +197,9 @@ static inline void cxl_handle_rdport_errors(struct cxl_= dev_state *cxlds) { } #endif /* CONFIG_CXL_RCH_RAS */ =20 int cxl_gpf_port_setup(struct cxl_dport *dport); +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport); +struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev); =20 struct cxl_hdm; int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhd= m, diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index b70e1b505b5c..d060f864cf2e 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1360,8 +1360,8 @@ static struct cxl_port *__find_cxl_port(struct cxl_fi= nd_port_ctx *ctx) return NULL; } =20 -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, @@ -1564,7 +1564,7 @@ static int match_port_by_uport(struct device *dev, co= nst void *data) * Function takes a device reference on the port device. Caller should do a * put_device() when done. */ -static struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev) +struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev) { struct device *dev; =20 @@ -1573,6 +1573,7 @@ static struct cxl_port *find_cxl_port_by_uport(struct= device *uport_dev) return to_cxl_port(dev); return NULL; } +EXPORT_SYMBOL_NS_GPL(find_cxl_port_by_uport, "CXL"); =20 static int update_decoder_targets(struct device *dev, void *data) { diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index beb142054bda..142ca8794107 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -145,6 +145,39 @@ static void cxl_dport_map_ras(struct cxl_dport *dport) dev_dbg(dev, "Failed to map RAS capability.\n"); } =20 +static void __iomem *cxl_get_ras_base(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport; + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port(&pdev->dev,= &dport); + + if (!dport) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return dport->regs.ras; + } + case PCI_EXP_TYPE_UPSTREAM: + { + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&p= dev->dev); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port->uport_regs.ras; + } + } + + dev_warn_once(dev, "Error: Unsupported device type (%X)", pci_pcie_type(p= dev)); + return NULL; +} + /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized @@ -254,6 +287,22 @@ pci_ers_result_t cxl_handle_ras(struct device *dev, u6= 4 serial, void __iomem *ra return PCI_ERS_RESULT_PANIC; } =20 +void cxl_port_cor_error_detected(struct device *dev) +{ + void __iomem *ras_base =3D cxl_get_ras_base(dev); + + cxl_handle_cor_ras(dev, 0, ras_base); +} +EXPORT_SYMBOL_NS_GPL(cxl_port_cor_error_detected, "CXL"); + +pci_ers_result_t cxl_port_error_detected(struct device *dev) +{ + void __iomem *ras_base =3D cxl_get_ras_base(dev); + + return cxl_handle_ras(dev, 0, ras_base); +} +EXPORT_SYMBOL_NS_GPL(cxl_port_error_detected, "CXL"); + void cxl_cor_error_detected(struct device *dev) { struct cxl_memdev *cxlmd =3D to_cxl_memdev(dev); diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c index 5dbc81341dc4..25f9512b57f7 100644 --- a/drivers/pci/pcie/aer_cxl_vh.c +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -43,7 +43,10 @@ bool is_cxl_error(struct pci_dev *pdev, struct aer_err_i= nfo *info) if (!info || !info->is_cxl) return false; =20 - if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ROOT_PORT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_UPSTREAM) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_DOWNSTREAM)) return false; =20 return is_internal_error(info); --=20 2.34.1 From nobody Wed Dec 17 08:59:20 2025 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012066.outbound.protection.outlook.com [40.93.195.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2A9033BBA6; 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Tue, 4 Nov 2025 09:07:04 -0800 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [RESEND v13 21/25] PCI/AER: Dequeue forwarded CXL error Date: Tue, 4 Nov 2025 11:03:01 -0600 Message-ID: <20251104170305.4163840-22-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104170305.4163840-1-terry.bowman@amd.com> References: <20251104170305.4163840-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231F:EE_|SJ2PR12MB7799:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c55aac5-8eed-4065-70b5-08de1bc494cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:07:05.5779 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c55aac5-8eed-4065-70b5-08de1bc494cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7799 Content-Type: text/plain; charset="utf-8" The AER driver now forwards CXL protocol errors to the CXL driver via a kfifo. The CXL driver must consume these work items, initiate protocol error handling, and ensure RAS mappings remain valid throughout processing. Implement cxl_proto_err_work_fn() to dequeue work items forwarded by the AER service driver and begin protocol error processing by calling cxl_handle_proto_error(). Add a PCI device lock on &pdev->dev within cxl_proto_err_work_fn() to keep the PCI device structure valid during handling. Locking an Endpoint will also defer RAS unmapping until the device is unlocked. For Endpoints, add a lock on CXL memory device cxlds->dev. The CXL memory device structure holds the RAS register reference needed during error handling. Add lock for the parent CXL Port for Root Ports, Downstream Ports, and Upstream Ports to prevent destruction of structures holding mapped RAS addresses while they are in use. Invoke cxl_do_recovery() for uncorrectable errors. Treat this as a stub for now; implement its functionality in a future patch. Export pci_clean_device_status() to enable cleanup of AER status following error handling. Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Acked-by: Bjorn Helgaas --- Changes in v12->v13: - Add cxlmd lock using guard() (Terry) - Remove exporting of unused function, pci_aer_clear_fatal_status() (Dave J= iang) - Change pr_err() calls to ratelimited. (Terry) - Update commit message. (Terry) - Remove namespace qualifier from pcie_clear_device_status() export (Dave Jiang) - Move locks into cxl_proto_err_work_fn() (Dave) - Update log messages in cxl_forward_error() (Ben) Changes in v11->v12: - Add guard for CE case in cxl_handle_proto_error() (Dave) Changes in v10->v11: - Reword patch commit message to remove RCiEP details (Jonathan) - Add #include (Terry) - is_cxl_rcd() - Fix short comment message wrap (Jonathan) - is_cxl_rcd() - Combine return calls into 1 (Jonathan) - cxl_handle_proto_error() - Move comment earlier (Jonathan) - Use FIELD_GET() in discovering class code (Jonathan) - Remove BDF from cxl_proto_err_work_data. Use 'struct pci_dev *' (Dan) --- drivers/cxl/core/ras.c | 153 ++++++++++++++++++++++++++++++++++++++--- drivers/pci/pci.c | 1 + drivers/pci/pci.h | 1 - include/linux/pci.h | 2 + 4 files changed, 145 insertions(+), 12 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 142ca8794107..5bc144cde0ee 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -117,17 +117,6 @@ static void cxl_cper_prot_err_work_fn(struct work_stru= ct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 -int cxl_ras_init(void) -{ - return cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); -} - -void cxl_ras_exit(void) -{ - cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); - cancel_work_sync(&cxl_cper_prot_err_work); -} - static bool is_pcie_endpoint(struct pci_dev *pdev) { return pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT; @@ -178,6 +167,51 @@ static void __iomem *cxl_get_ras_base(struct device *d= ev) return NULL; } =20 +/* + * Return 'struct cxl_port *' parent CXL port of dev's + * + * Reference count increments on success + * + * dev: Find the parent port of this dev + */ +static struct cxl_port *get_cxl_port(struct pci_dev *pdev) +{ + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport; + struct cxl_port *port =3D find_cxl_port(&pdev->dev, &dport); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port; + } + case PCI_EXP_TYPE_UPSTREAM: + { + struct cxl_port *port =3D find_cxl_port_by_uport(&pdev->dev); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port; + } + case PCI_EXP_TYPE_ENDPOINT: + { + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct cxl_port *port =3D cxlds->cxlmd->endpoint; + + get_device(&port->dev); + return port; + } + } + pci_warn_once(pdev, "Error: Unsupported device type (%X)", pci_pcie_type(= pdev)); + return NULL; +} + /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized @@ -212,6 +246,23 @@ void cxl_uport_init_ras_reporting(struct cxl_port *por= t, } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); =20 +static bool device_lock_if(struct device *dev, bool cond) +{ + if (cond) + device_lock(dev); + return cond; +} + +static void device_unlock_if(struct device *dev, bool take) +{ + if (take) + device_unlock(dev); +} + +static void cxl_do_recovery(struct pci_dev *pdev) +{ +} + void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; @@ -388,3 +439,83 @@ pci_ers_result_t pci_error_detected(struct pci_dev *pd= ev, return rc; } EXPORT_SYMBOL_NS_GPL(pci_error_detected, "CXL"); + +static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) +{ + struct pci_dev *pdev =3D err_info->pdev; + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + + if (err_info->severity =3D=3D AER_CORRECTABLE) { + + if (pdev->aer_cap) + pci_clear_and_set_config_dword(pdev, + pdev->aer_cap + PCI_ERR_COR_STATUS, + 0, PCI_ERR_COR_INTERNAL); + + if (is_pcie_endpoint(pdev)) + cxl_cor_error_detected(&cxlds->cxlmd->dev); + else + cxl_port_cor_error_detected(&pdev->dev); + + pcie_clear_device_status(pdev); + } else { + cxl_do_recovery(pdev); + } +} + +static void cxl_proto_err_work_fn(struct work_struct *work) +{ + struct cxl_proto_err_work_data wd; + + while (cxl_proto_err_kfifo_get(&wd)) { + struct pci_dev *pdev __free(pci_dev_put) =3D pci_dev_get(wd.pdev); + struct device *cxlmd_dev; + + if (!pdev) { + pr_err_ratelimited("NULL PCI device passed in AER-CXL KFIFO\n"); + continue; + } + + guard(device)(&pdev->dev); + if (is_pcie_endpoint(pdev)) { + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + + if (!cxl_pci_drv_bound(pdev)) + return; + cxlmd_dev =3D &cxlds->cxlmd->dev; + device_lock_if(cxlmd_dev, cxlmd_dev); + } else { + cxlmd_dev =3D NULL; + } + + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + if (!port) + return; + guard(device)(&port->dev); + + cxl_handle_proto_error(&wd); + device_unlock_if(cxlmd_dev, cxlmd_dev); + } +} + +static struct work_struct cxl_proto_err_work; +static DECLARE_WORK(cxl_proto_err_work, cxl_proto_err_work_fn); + +int cxl_ras_init(void) +{ + if (cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work)) + pr_err("Failed to initialize CXL RAS CPER\n"); + + cxl_register_proto_err_work(&cxl_proto_err_work); + + return 0; +} + +void cxl_ras_exit(void) +{ + cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); + cancel_work_sync(&cxl_cper_prot_err_work); + + cxl_unregister_proto_err_work(); + cancel_work_sync(&cxl_proto_err_work); +} diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 53a49bb32514..6341ca6515a5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2277,6 +2277,7 @@ void pcie_clear_device_status(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); } +EXPORT_SYMBOL_GPL(pcie_clear_device_status); #endif =20 /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index a398e489318c..2af6ea82526d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -229,7 +229,6 @@ void pci_refresh_power_state(struct pci_dev *dev); int pci_power_up(struct pci_dev *dev); void pci_disable_enabled_device(struct pci_dev *dev); int pci_finish_runtime_suspend(struct pci_dev *dev); -void pcie_clear_device_status(struct pci_dev *dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:07:16.3807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9438ffe6-c2ee-4125-6710-08de1bc49b3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8334 Content-Type: text/plain; charset="utf-8" CXL uncorrectable errors (UCE) will soon be handled separately from the PCI AER handling. The merge_result() function can be made common to use in both handling paths. Rename the PCI subsystem's merge_result() to be pci_ers_merge_result(). Export pci_ers_merge_result() to make available for the CXL and other drivers to use. Update pci_ers_merge_result() to support recently introduced PCI_ERS_RESULT= _PANIC result. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- Changes in v12->v13: - Renamed pci_ers_merge_result() to pcie_ers_merge_result(). pci_ers_merge_result() is already used in eeh driver. (Bot) Changes in v11->v12: - Remove static inline pci_ers_merge_result() definition for !CONFIG_PCIEAE= R. Is not needed. (Lukas) Changes in v10->v11: - New patch - pci_ers_merge_result() - Change export to non-namespace and rename to be pci_ers_merge_result() - Move pci_ers_merge_result() definition to pci.h. Needs pci_ers_result --- drivers/pci/pcie/err.c | 14 +++++++++----- include/linux/pci.h | 7 +++++++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index bebe4bc111d7..9394bbdcf0fb 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -21,9 +21,12 @@ #include "portdrv.h" #include "../pci.h" =20 -static pci_ers_result_t merge_result(enum pci_ers_result orig, - enum pci_ers_result new) +pci_ers_result_t pcie_ers_merge_result(enum pci_ers_result orig, + enum pci_ers_result new) { + if (new =3D=3D PCI_ERS_RESULT_PANIC) + return PCI_ERS_RESULT_PANIC; + if (new =3D=3D PCI_ERS_RESULT_NO_AER_DRIVER) return PCI_ERS_RESULT_NO_AER_DRIVER; =20 @@ -45,6 +48,7 @@ static pci_ers_result_t merge_result(enum pci_ers_result = orig, =20 return orig; } +EXPORT_SYMBOL(pcie_ers_merge_result); =20 static int report_error_detected(struct pci_dev *dev, pci_channel_state_t state, @@ -81,7 +85,7 @@ static int report_error_detected(struct pci_dev *dev, vote =3D err_handler->error_detected(dev, state); } pci_uevent_ers(dev, vote); - *result =3D merge_result(*result, vote); + *result =3D pcie_ers_merge_result(*result, vote); device_unlock(&dev->dev); return 0; } @@ -139,7 +143,7 @@ static int report_mmio_enabled(struct pci_dev *dev, voi= d *data) =20 err_handler =3D pdrv->err_handler; vote =3D err_handler->mmio_enabled(dev); - *result =3D merge_result(*result, vote); + *result =3D pcie_ers_merge_result(*result, vote); out: device_unlock(&dev->dev); return 0; @@ -159,7 +163,7 @@ static int report_slot_reset(struct pci_dev *dev, void = *data) =20 err_handler =3D pdrv->err_handler; vote =3D err_handler->slot_reset(dev); - *result =3D merge_result(*result, vote); + *result =3D pcie_ers_merge_result(*result, vote); out: device_unlock(&dev->dev); return 0; diff --git a/include/linux/pci.h b/include/linux/pci.h index 33d16b212e0d..d3e3300f79ec 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1887,9 +1887,16 @@ static inline void pci_hp_unignore_link_change(struc= t pci_dev *pdev) { } #ifdef CONFIG_PCIEAER bool pci_aer_available(void); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:07:27.7155 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c34764d-eb9f-4f44-d959-08de1bc4a1fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5888 Content-Type: text/plain; charset="utf-8" Implement cxl_do_recovery() to handle uncorrectable protocol errors (UCE), following the design of pcie_do_recovery(). Unlike PCIe, all CXL UCEs are treated as fatal and trigger a kernel panic to avoid potential CXL memory corruption. Add cxl_walk_port(), analogous to pci_walk_bridge(), to traverse the CXL topology from the error source through downstream CXL ports and endpoints. Introduce cxl_report_error_detected(), mirroring PCI's report_error_detected(), and implement device locking for the affected subtree. Endpoints require locking the PCI device (pdev->dev) and the CXL memdev (cxlmd->dev). CXL ports require locking the PCI device (pdev->dev) and the parent CXL port. The device locks should be taken early where possible. The initially reporting device will be locked after kfifo dequeue. Iterated devices will be locked in cxl_report_error_detected() and must lock the iterated devices except for the first device as it has already been locked. Export pci_aer_clear_fatal_status() for use when a UCE is not present. Signed-off-by: Terry Bowman Acked-by: Bjorn Helgaas # drivers/pci/ --- Changes in v12->v13: - Add guard() before calling cxl_pci_drv_bound() (Dave Jiang) - Add guard() calls for EP (cxlds->cxlmd->dev & pdev->dev) and ports (pdev->dev & parent cxl_port) in cxl_report_error_detected() and cxl_handle_proto_error() (Terry) - Remove unnecessary check for endpoint port. (Dave Jiang) - Remove check for RCIEP EP in cxl_report_error_detected(). (Terry) Changes in v11->v12: - Clean up port discovery in cxl_do_recovery() (Dave) - Add PCI_EXP_TYPE_RC_END to type check in cxl_report_error_detected() Changes in v10->v11: - pci_ers_merge_results() - Move to earlier patch --- drivers/cxl/core/ras.c | 135 ++++++++++++++++++++++++++++++++++++++++- drivers/pci/pci.h | 1 - drivers/pci/pcie/aer.c | 1 + include/linux/aer.h | 2 + 4 files changed, 135 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 5bc144cde0ee..52c6f19564b6 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -259,8 +259,138 @@ static void device_unlock_if(struct device *dev, bool= take) device_unlock(dev); } =20 +/** + * cxl_report_error_detected + * @dev: Device being reported + * @data: Result + * @err_pdev: Device with initial detected error. Is locked immediately + * after KFIFO dequeue. + */ +static int cxl_report_error_detected(struct device *dev, void *data, struc= t pci_dev *err_pdev) +{ + bool need_lock =3D (dev !=3D &err_pdev->dev); + pci_ers_result_t vote, *result =3D data; + struct pci_dev *pdev; + + if (!dev || !dev_is_pci(dev)) + return 0; + pdev =3D to_pci_dev(dev); + + device_lock_if(&pdev->dev, need_lock); + if (is_pcie_endpoint(pdev) && !cxl_pci_drv_bound(pdev)) { + device_unlock_if(&pdev->dev, need_lock); + return PCI_ERS_RESULT_NONE; + } + + if (pdev->aer_cap) + pci_clear_and_set_config_dword(pdev, + pdev->aer_cap + PCI_ERR_COR_STATUS, + 0, PCI_ERR_COR_INTERNAL); + + if (is_pcie_endpoint(pdev)) { + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + + device_lock_if(&cxlds->cxlmd->dev, need_lock); + vote =3D cxl_error_detected(&cxlds->cxlmd->dev); + device_unlock_if(&cxlds->cxlmd->dev, need_lock); + } else { + vote =3D cxl_port_error_detected(dev); + } + + pcie_clear_device_status(pdev); + *result =3D pcie_ers_merge_result(*result, vote); + device_unlock_if(&pdev->dev, need_lock); + + return 0; +} + +static int match_port_by_parent_dport(struct device *dev, const void *dpor= t_dev) +{ + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port =3D to_cxl_port(dev); + + return port->parent_dport->dport_dev =3D=3D dport_dev; +} + +/** + * cxl_walk_port + * + * @port: Port be traversed into + * @cb: Callback for handling the CXL Ports + * @userdata: Result + * @err_pdev: Device with initial detected error. Is locked immediately + * after KFIFO dequeue. + */ +static void cxl_walk_port(struct cxl_port *port, + int (*cb)(struct device *, void *, struct pci_dev *), + void *userdata, + struct pci_dev *err_pdev) +{ + struct cxl_port *err_port __free(put_cxl_port) =3D get_cxl_port(err_pdev); + bool need_lock =3D (port !=3D err_port); + struct cxl_dport *dport =3D NULL; + unsigned long index; + + device_lock_if(&port->dev, need_lock); + if (is_cxl_endpoint(port)) { + cb(port->uport_dev->parent, userdata, err_pdev); + device_unlock_if(&port->dev, need_lock); + return; + } + + if (port->uport_dev && dev_is_pci(port->uport_dev)) + cb(port->uport_dev, userdata, err_pdev); + + /* + * Iterate over the set of Downstream Ports recorded in port->dports (XAr= ray): + * - For each dport, attempt to find a child CXL Port whose parent dport + * match. + * - Invoke the provided callback on the dport's device. + * - If a matching child CXL Port device is found, recurse into that por= t to + * continue the walk. + */ + xa_for_each(&port->dports, index, dport) + { + struct device *child_port_dev __free(put_device) =3D + bus_find_device(&cxl_bus_type, &port->dev, dport->dport_dev, + match_port_by_parent_dport); + + cb(dport->dport_dev, userdata, err_pdev); + if (child_port_dev) + cxl_walk_port(to_cxl_port(child_port_dev), cb, userdata, err_pdev); + } + device_unlock_if(&port->dev, need_lock); +} + static void cxl_do_recovery(struct pci_dev *pdev) { + pci_ers_result_t status =3D PCI_ERS_RESULT_CAN_RECOVER; + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device\n"); + return; + } + + cxl_walk_port(port, cxl_report_error_detected, &status, pdev); + if (status =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + /* + * If we have native control of AER, clear error status in the device + * that detected the error. If the platform retained control of AER, + * it is responsible for clearing this status. In that case, the + * signaling device may not even be visible to the OS. + */ + if (cxl_error_is_native(pdev)) { + pcie_clear_device_status(pdev); + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + } } =20 void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) @@ -483,16 +613,15 @@ static void cxl_proto_err_work_fn(struct work_struct = *work) if (!cxl_pci_drv_bound(pdev)) return; cxlmd_dev =3D &cxlds->cxlmd->dev; - device_lock_if(cxlmd_dev, cxlmd_dev); } else { cxlmd_dev =3D NULL; } =20 + /* Lock the CXL parent Port */ struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); - if (!port) - return; guard(device)(&port->dev); =20 + device_lock_if(cxlmd_dev, cxlmd_dev); cxl_handle_proto_error(&wd); device_unlock_if(cxlmd_dev, cxlmd_dev); } diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2af6ea82526d..3637996d37ab 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1174,7 +1174,6 @@ void pci_restore_aer_state(struct pci_dev *dev); static inline void pci_no_aer(void) { } static inline void pci_aer_init(struct pci_dev *d) { } static inline void pci_aer_exit(struct pci_dev *d) { } -static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINV= AL; } static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -= EINVAL; } static inline void pci_save_aer_state(struct pci_dev *dev) { } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index e806fa05280b..4cf44297bb24 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -297,6 +297,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev) if (status) pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); } +EXPORT_SYMBOL_GPL(pci_aer_clear_fatal_status); =20 /** * pci_aer_raw_clear_status - Clear AER error registers. diff --git a/include/linux/aer.h b/include/linux/aer.h index 6b2c87d1b5b6..64aef69fb546 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -66,6 +66,7 @@ struct cxl_proto_err_work_data { =20 #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:07:38.5986 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 995a63d4-ce9d-4966-8ad2-08de1bc4a87a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFE494AA682 Content-Type: text/plain; charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. These must be enabled inorder to process CXL protocol errors. Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_err= ors(). pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized. But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable A= ER correctable internal errors and uncorrectable internal errors for all CXL devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham --- Changes in v12->v13: - Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Te= rry) - Add Dave Jiang's and Ben's review-by Changes in v11->v12: - None Changes in v10->v11: - Added check for valid PCI devices in is_cxl_error() (Terry) - Removed check for RCiEP in cxl_handle_proto_err() and cxl_report_error_detected() (Terry) --- drivers/cxl/core/core.h | 4 ++++ drivers/cxl/core/port.c | 4 ++++ drivers/cxl/core/ras.c | 26 +++++++++++++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 046ec65ed147..a7a0838c8f23 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -159,6 +159,8 @@ pci_ers_result_t pci_error_detected(struct pci_dev *pde= v, void pci_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_port_error_detected(struct device *dev); void cxl_port_cor_error_detected(struct device *dev); +void cxl_mask_proto_interrupts(struct device *dev); +void cxl_unmask_proto_interrupts(struct device *dev); #else static inline int cxl_ras_init(void) { @@ -183,6 +185,8 @@ static inline pci_ers_result_t cxl_port_error_detected(= struct device *dev) { return PCI_ERS_RESULT_NONE; } +static inline void cxl_unmask_proto_interrupts(struct device *dev) { } +static inline void cxl_mask_proto_interrupts(struct device *dev) { } #endif /* CONFIG_CXL_RAS */ =20 /* Restricted CXL Host specific RAS functions */ diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index d060f864cf2e..a23c742eb670 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1747,6 +1747,8 @@ static int add_port_attach_ep(struct cxl_memdev *cxlm= d, rc =3D -ENXIO; } =20 + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); + return rc; } =20 @@ -1833,6 +1835,8 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) =20 rc =3D cxl_add_ep(dport, &cxlmd->dev); =20 + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); + /* * If the endpoint already exists in the port's list, * that's ok, it was added on a previous pass. diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 52c6f19564b6..101e55723785 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -122,6 +122,23 @@ static bool is_pcie_endpoint(struct pci_dev *pdev) return pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT; } =20 +void cxl_unmask_proto_interrupts(struct device *dev) +{ + if (!dev || !dev_is_pci(dev)) + return; + + struct pci_dev *pdev __free(pci_dev_put) =3D pci_dev_get(to_pci_dev(dev)); + + if (!pdev->aer_cap) { + pdev->aer_cap =3D pci_find_ext_capability(pdev, + PCI_EXT_CAP_ID_ERR); + if (!pdev->aer_cap) + return; + } + + pci_aer_unmask_internal_errors(pdev); +} + static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -230,7 +247,10 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) =20 cxl_dport_map_rch_aer(dport); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 17:07:49.5809 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56549393-698c-46ef-3b51-08de1bc4af06 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002319.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9230 Content-Type: text/plain; charset="utf-8" During CXL device cleanup the CXL PCIe Port device interrupts remain enabled. This potentially allows unnecessary interrupt processing on behalf of the CXL errors while the device is destroyed. Disable CXL protocol errors by setting the CXL devices' AER mask register. Introduce pci_aer_mask_internal_errors() similar to pci_aer_unmask_internal= _errors(). Add to the AER service driver allowing other subsystems to use. Introduce cxl_mask_proto_interrupts() to call pci_aer_mask_internal_errors(= ). Add calls to cxl_mask_proto_interrupts() within CXL Port teardown for CXL Root Ports, CXL Downstream Switch Ports, CXL Upstream Switch Ports, and CXL Endpoints. Follow the same "bottom-up" approach used during CXL Port teardown. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v12->v13: - Added dev and dev_is_pci() checks in cxl_mask_proto_interrupts() (Terry) Changes in v11->v12: - Keep pci_aer_mask_internal_errors() in driver/pci/pcie/aer.c (Lukas) - Update commit description for pci_aer_mask_internal_errors() - Add check `if (port->parent_dport)` in delete_switch_port() (Terry) Changes in v10->v11: - Removed guard() cxl_mask_proto_interrupts(). RP was blocking during testing. (Terry) --- drivers/cxl/core/port.c | 10 +++++++++- drivers/cxl/core/ras.c | 10 ++++++++++ drivers/pci/pcie/aer.c | 21 +++++++++++++++++++++ include/linux/aer.h | 2 ++ 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index a23c742eb670..d19ebf052d76 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1437,6 +1437,10 @@ EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, "CXL"); */ static void delete_switch_port(struct cxl_port *port) { + cxl_mask_proto_interrupts(port->uport_dev); + if (port->parent_dport) + cxl_mask_proto_interrupts(port->parent_dport->dport_dev); + devm_release_action(port->dev.parent, cxl_unlink_parent_dport, port); devm_release_action(port->dev.parent, cxl_unlink_uport, port); devm_release_action(port->dev.parent, unregister_port, port); @@ -1458,8 +1462,10 @@ static void del_dports(struct cxl_port *port) =20 device_lock_assert(&port->dev); =20 - xa_for_each(&port->dports, index, dport) + xa_for_each(&port->dports, index, dport) { + cxl_mask_proto_interrupts(dport->dport_dev); del_dport(dport); + } } =20 struct detach_ctx { @@ -1486,6 +1492,8 @@ static void cxl_detach_ep(void *data) { struct cxl_memdev *cxlmd =3D data; =20 + cxl_mask_proto_interrupts(cxlmd->cxlds->dev); + for (int i =3D cxlmd->depth - 1; i >=3D 1; i--) { struct cxl_port *port, *parent_port; struct detach_ctx ctx =3D { diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 101e55723785..6dccbe66c9ac 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -139,6 +139,16 @@ void cxl_unmask_proto_interrupts(struct device *dev) pci_aer_unmask_internal_errors(pdev); } =20 +void cxl_mask_proto_interrupts(struct device *dev) +{ + if (!dev || !dev_is_pci(dev)) + return; + + struct pci_dev *pdev __free(pci_dev_put) =3D pci_dev_get(to_pci_dev(dev)); + + pci_aer_mask_internal_errors(pdev); +} + static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 4cf44297bb24..fcc2f43c3383 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1149,6 +1149,27 @@ void pci_aer_unmask_internal_errors(struct pci_dev *= dev) } EXPORT_SYMBOL_GPL(pci_aer_unmask_internal_errors); =20 +/** + * pci_aer_mask_internal_errors - mask internal errors + * @dev: pointer to the pcie_dev data structure + * + * Masks internal errors in the Uncorrectable and Correctable Error + * Mask registers. + * + * Note: AER must be enabled and supported by the device which must be + * checked in advance, e.g. with pcie_aer_is_native(). + */ +void pci_aer_mask_internal_errors(struct pci_dev *dev) +{ + int aer =3D dev->aer_cap; + + pci_clear_and_set_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, + 0, PCI_ERR_UNC_INTN); + pci_clear_and_set_config_dword(dev, aer + PCI_ERR_COR_MASK, + 0, PCI_ERR_COR_INTERNAL); +} +EXPORT_SYMBOL_GPL(pci_aer_mask_internal_errors); + /** * pci_aer_handle_error - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device diff --git a/include/linux/aer.h b/include/linux/aer.h index 64aef69fb546..2b89bd940ac1 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -69,6 +69,7 @@ int pci_aer_clear_nonfatal_status(struct pci_dev *dev); void pci_aer_clear_fatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); void pci_aer_unmask_internal_errors(struct pci_dev *dev); +void pci_aer_mask_internal_errors(struct pci_dev *dev); #else static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) { @@ -77,6 +78,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pc= i_dev *dev) static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } +static inline void pci_aer_mask_internal_errors(struct pci_dev *dev) { } #endif =20 #ifdef CONFIG_CXL_RAS --=20 2.34.1