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Tue, 4 Nov 2025 06:27:55 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH RESEND v4 1/4] rust: io: factor common I/O helpers into Io trait Date: Tue, 4 Nov 2025 16:27:30 +0200 Message-ID: <20251104142733.5334-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251104142733.5334-1-zhiw@nvidia.com> References: <20251104142733.5334-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|PH8PR12MB7157:EE_ X-MS-Office365-Filtering-Correlation-Id: 978c3349-a828-4af9-d894-08de1bae6707 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2PvNus91scDJ9lGNg+WO8kpwQ7q4r8utuS/3oWAdVP0XCOnUNsqFTvhSb0Fw?= =?us-ascii?Q?h3Tv+mbK0VNbf5XcPkFIXa+oTdd3tUYt/vHklUhSFQv8ZfKMkMyRoBNZO3rL?= =?us-ascii?Q?c2IQdbIO+2L4CWRK66a9QbDw3T8UJ8U7Kt8reSNtpXGVOx8DSYKZJWkH2loP?= =?us-ascii?Q?+WqE9BU1RqAssvjs0EKq6D24C4Ldtq3tDTnR5cJGpWub/ciI/bJ4V3wBt+rc?= =?us-ascii?Q?StvO63Tlf2e8iox3scBX8zz5+tbv/A4ovsPe9lch465lWHlKR7P/7oeuRpmQ?= =?us-ascii?Q?5ACDGRtmdAF8qxaVlOZdccqHKcw8EUG5M3ev4tTcpOKt/q7gvkbX0Z1hN9uY?= =?us-ascii?Q?vABMU73/gwYOwZU9QO+Wm38oR9WsfsHAZIei+7YcI+fNdlYWMm3Z0we3pmhu?= =?us-ascii?Q?Pejn7voYDxVvpmxip/2G0vEL3Amzd6owCe6+kCyTpq99k5M4drUSuNvr4qfJ?= =?us-ascii?Q?9zM6VYk22rFGi8Ej9HmTozRHvwwMrl6LRV05xV4kyqLOETVKlh/uX0qLCE+W?= =?us-ascii?Q?zKFJmx0UOW8e1Cb1AoTcR49ncA+cWky+mdhK9XU3XIwakweVJyRsE5WdcAqy?= =?us-ascii?Q?j1tTSBYdntazEGFtBbXnsd92TDAKZd1pWNJUbmfcMvqvFBLng/JKzBpGq6h5?= =?us-ascii?Q?7sUoGTZxbKj42idXPxZLe/KHYCPXyUb5bAlzaeCcBzHksV95nFZzK6dxKzfr?= =?us-ascii?Q?3FgECZkXNZsOr50utwd0TdopIq+aewF9SqgRxXaQuoh00nyKXYC7jxP7oNkT?= =?us-ascii?Q?G3mObMGuxJwGiahCHxIe428qE/B79AeMjTe3QtLJcuyMMiKzdAKvhl5q5J06?= =?us-ascii?Q?0aiykjdy4OkN1KYAGn62n0LvxBJ1rygNMlHWEkIL8jUuVfO/JbvbAkaRf5Od?= =?us-ascii?Q?1JOtY1uL+Yb7gDn2U/PAA9EbSkkK3a9mkpodKBoBjSFcjRTvnS0bMTdrsnnH?= =?us-ascii?Q?lz2B/UbCHQjxJuU+sNS7nbK14jkm0i0c91gZiX68lJbsOgqPKWCBl9HH9a/Q?= =?us-ascii?Q?SGJ/l0BET79SaHfBKvu9yhLX/zAruPyYpDxRak0wRP+4fZHDGmsHJpPMao1U?= =?us-ascii?Q?lMF9r8OsSmWPFw3RWTLMYZVaMCJDbeCeeR0/NjNqNdyhiwylKrhmZvBLCgL0?= =?us-ascii?Q?JZ3UhyO2ut0N6X5GphAeQvixSHWkLmc27S5sEN7v36YzeaiOOO52PV4aZ38w?= =?us-ascii?Q?jRy9ZyQ5dTWLLXFukm06jRhe3Fu0L/0iU2mUAXJMtKOSdwbWUD+Ec18JjWKa?= =?us-ascii?Q?Sshlawqzb91ApQnsXAKCuuDZXkvtAUbtCzGL+9mbZj5bQlZJFjERv8qLaLtv?= =?us-ascii?Q?/RuLsVjSnD4+0tW6oqJf6+/x1eKuB9CtI4/g31Tx7ESNeNNg0NKriK1fuZ6B?= =?us-ascii?Q?j6i58seo6um05uAEFP1fGuCiCZCwCkyYp/YeZadMZUHmO4sx0fDYipZjI9Im?= =?us-ascii?Q?/g4Leht47XEfFabgepyhRXkqza94A+QtJvoPNjS9LcEjlBsIUuxPDVkz+6aE?= =?us-ascii?Q?I/EOJjWhxDnNmABnd9q+ZbOYTcvQfTDKWCAX/DwkJU7EYST7pT8QMji0ZR+W?= =?us-ascii?Q?KjzesZcX0Q18c9YUH48=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 14:28:19.8685 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 978c3349-a828-4af9-d894-08de1bae6707 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7157 Content-Type: text/plain; charset="utf-8" The previous Io type combined both the generic I/O access helpers and MMIO implementation details in a single struct. To establish a cleaner layering between the I/O interface and its concrete backends, paving the way for supporting additional I/O mechanisms in the future, Io need to be factored. Factor the common helpers into a new Io trait, and move the MMIO-specific logic into a dedicated Mmio type implementing that trait. Rename the IoRaw to MmioRaw and update the bus MMIO implementations to use MmioRaw. No functional change intended. Cc: Alexandre Courbot Cc: Bjorn Helgaas Cc: Danilo Krummrich Cc: John Hubbard Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/regs/macros.rs | 90 ++++++---- drivers/gpu/nova-core/vbios.rs | 1 + rust/kernel/devres.rs | 12 +- rust/kernel/io.rs | 248 +++++++++++++++++++-------- rust/kernel/io/mem.rs | 16 +- rust/kernel/io/poll.rs | 4 +- rust/kernel/pci.rs | 10 +- samples/rust/rust_driver_pci.rs | 2 +- 8 files changed, 255 insertions(+), 128 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index fd1a815fa57d..5033bc0929ab 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -369,16 +369,18 @@ impl $name { =20 /// Read the register from its address in `io`. #[inline(always)] - pub(crate) fn read(io: &T) -> Self where - T: ::core::ops::Deref>, + pub(crate) fn read(io: &T) -> Self where + T: ::core::ops::Deref, + I: ::kernel::io::Io, { Self(io.read32($offset)) } =20 /// Write the value contained in `self` to the register addres= s in `io`. #[inline(always)] - pub(crate) fn write(self, io: &T) where - T: ::core::ops::Deref>, + pub(crate) fn write(self, io: &T) where + T: ::core::ops::Deref, + I: ::kernel::io::Io, { io.write32(self.0, $offset) } @@ -386,11 +388,12 @@ pub(crate) fn write(self, io: &= T) where /// Read the register from its address in `io` and run `f` on = its value to obtain a new /// value to write back. #[inline(always)] - pub(crate) fn update( + pub(crate) fn update( io: &T, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io)); @@ -408,12 +411,13 @@ impl $name { /// Read the register from `io`, using the base address provid= ed by `base` and adding /// the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, #[allow(unused_variables)] base: &B, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -428,13 +432,14 @@ pub(crate) fn read( /// Write the value contained in `self` to `io`, using the bas= e address provided by /// `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, #[allow(unused_variables)] base: &B, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -449,12 +454,13 @@ pub(crate) fn write( /// the register's offset to it, then run `f` on its value to = obtain a new value to /// write back. #[inline(always)] - pub(crate) fn update( + pub(crate) fn update( io: &T, base: &B, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -474,11 +480,12 @@ impl $name { =20 /// Read the array register at index `idx` from its address in= `io`. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, { build_assert!(idx < Self::SIZE); =20 @@ -490,12 +497,13 @@ pub(crate) fn read( =20 /// Write the value contained in `self` to the array register = with index `idx` in `io`. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, { build_assert!(idx < Self::SIZE); =20 @@ -507,12 +515,13 @@ pub(crate) fn write( /// Read the array register at index `idx` in `io` and run `f`= on its value to obtain a /// new value to write back. #[inline(always)] - pub(crate) fn update( + pub(crate) fn update( io: &T, idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io, idx)); @@ -524,11 +533,12 @@ pub(crate) fn update( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_read( + pub(crate) fn try_read( io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, { if idx < Self::SIZE { Ok(Self::read(io, idx)) @@ -542,12 +552,13 @@ pub(crate) fn try_read( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_write( + pub(crate) fn try_write( self, io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, { if idx < Self::SIZE { Ok(self.write(io, idx)) @@ -562,12 +573,13 @@ pub(crate) fn try_write( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_update( + pub(crate) fn try_update( io: &T, idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, F: ::core::ops::FnOnce(Self) -> Self, { if idx < Self::SIZE { @@ -593,13 +605,14 @@ impl $name { /// Read the array register at index `idx` from `io`, using th= e base address provided /// by `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, #[allow(unused_variables)] base: &B, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -614,14 +627,15 @@ pub(crate) fn read( /// Write the value contained in `self` to `io`, using the bas= e address provided by /// `base` and adding the offset of array register `idx` to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, #[allow(unused_variables)] base: &B, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -636,13 +650,14 @@ pub(crate) fn write( /// by `base` and adding the register's offset to it, then run= `f` on its value to /// obtain a new value to write back. #[inline(always)] - pub(crate) fn update( + pub(crate) fn update( io: &T, base: &B, idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -656,12 +671,13 @@ pub(crate) fn update( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_read( + pub(crate) fn try_read( io: &T, base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -677,13 +693,14 @@ pub(crate) fn try_read( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_write( + pub(crate) fn try_write( self, io: &T, base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -700,13 +717,14 @@ pub(crate) fn try_write( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_update( + pub(crate) fn try_update( io: &T, base: &B, idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::Io, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs index 74ed6d61e6cc..cafb2d99c82b 100644 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@ -10,6 +10,7 @@ use kernel::error::Result; use kernel::prelude::*; use kernel::ptr::{Alignable, Alignment}; +use kernel::io::Io; use kernel::types::ARef; =20 /// The offset of the VBIOS ROM in the BAR0 space. diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs index 10a6a1789854..12a4474df3c3 100644 --- a/rust/kernel/devres.rs +++ b/rust/kernel/devres.rs @@ -52,11 +52,11 @@ struct Inner { /// # Examples /// /// ```no_run -/// # use kernel::{bindings, device::{Bound, Device}, devres::Devres, io::= {Io, IoRaw}}; +/// # use kernel::{bindings, device::{Bound, Device}, devres::Devres, io::= {Io, Mmio, MmioRaw}}; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -71,7 +71,7 @@ struct Inner { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -83,11 +83,11 @@ struct Inner { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// # fn no_run(dev: &Device) -> Result<(), Error> { @@ -230,7 +230,7 @@ pub fn device(&self) -> &Device { /// /// ```no_run /// # #![cfg(CONFIG_PCI)] - /// # use kernel::{device::Core, devres::Devres, pci}; + /// # use kernel::{device::Core, devres::Devres, io::Io, pci}; /// /// fn from_core(dev: &pci::Device, devres: Devres= >) -> Result { /// let bar =3D devres.access(dev.as_ref())?; diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index ee182b0b5452..0b1e79075c99 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -18,16 +18,16 @@ /// By itself, the existence of an instance of this structure does not pro= vide any guarantees that /// the represented MMIO region does exist or is properly mapped. /// -/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an `Io` -/// instance providing the actual memory accessors. Only by the conversion= into an `Io` structure -/// any guarantees are given. -pub struct IoRaw { +/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an +/// `Mmio` instance providing the actual memory accessors. Only by the con= version into an `Mmio` +/// structure any guarantees are given. +pub struct MmioRaw { addr: usize, maxsize: usize, } =20 -impl IoRaw { - /// Returns a new `IoRaw` instance on success, an error otherwise. +impl MmioRaw { + /// Returns a new `MmioRaw` instance on success, an error otherwise. pub fn new(addr: usize, maxsize: usize) -> Result { if maxsize < SIZE { return Err(EINVAL); @@ -62,11 +62,11 @@ pub fn maxsize(&self) -> usize { /// # Examples /// /// ```no_run -/// # use kernel::{bindings, ffi::c_void, io::{Io, IoRaw}}; +/// # use kernel::{bindings, ffi::c_void, io::{Io, Mmio, MmioRaw}}; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -81,7 +81,7 @@ pub fn maxsize(&self) -> usize { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -93,11 +93,11 @@ pub fn maxsize(&self) -> usize { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// @@ -111,29 +111,31 @@ pub fn maxsize(&self) -> usize { /// # } /// ``` #[repr(transparent)] -pub struct Io(IoRaw); +pub struct Mmio(MmioRaw); =20 macro_rules! define_read { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_= name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident -> $t= ype_name:ty) =3D> { /// Read IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile /// time, the build will fail. $(#[$attr])* #[inline] - pub fn $name(&self, offset: usize) -> $type_name { + $vis fn $name(&self, offset: usize) -> $type_name { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. unsafe { bindings::$c_fn(addr as *const c_void) } } + }; =20 + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident -> = $type_name:ty) =3D> { /// Read IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is /// out of bounds. $(#[$attr])* - pub fn $try_name(&self, offset: usize) -> Result<$type_name> { + $vis fn $try_name(&self, offset: usize) -> Result<$type_name> { let addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. @@ -143,26 +145,28 @@ pub fn $try_name(&self, offset: usize) -> Result<$typ= e_name> { } =20 macro_rules! define_write { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_= name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident <- $t= ype_name:ty) =3D> { /// Write IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile /// time, the build will fail. $(#[$attr])* #[inline] - pub fn $name(&self, value: $type_name, offset: usize) { + $vis fn $name(&self, value: $type_name, offset: usize) { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. unsafe { bindings::$c_fn(value, addr as *mut c_void) } } + }; =20 + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident <- = $type_name:ty) =3D> { /// Write IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is /// out of bounds. $(#[$attr])* - pub fn $try_name(&self, value: $type_name, offset: usize) -> Resul= t { + $vis fn $try_name(&self, value: $type_name, offset: usize) -> Resu= lt { let addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. @@ -172,43 +176,40 @@ pub fn $try_name(&self, value: $type_name, offset: us= ize) -> Result { }; } =20 -impl Io { - /// Converts an `IoRaw` into an `Io` instance, providing the accessors= to the MMIO mapping. - /// - /// # Safety - /// - /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size - /// `maxsize`. - pub unsafe fn from_raw(raw: &IoRaw) -> &Self { - // SAFETY: `Io` is a transparent wrapper around `IoRaw`. - unsafe { &*core::ptr::from_ref(raw).cast() } +/// Checks whether an access of type `U` at the given `offset` +/// is valid within this region. +#[inline] +const fn offset_valid(offset: usize, size: usize) -> bool { + let type_size =3D core::mem::size_of::(); + if let Some(end) =3D offset.checked_add(type_size) { + end <=3D size && offset % type_size =3D=3D 0 + } else { + false } +} + +/// Represents a region of I/O space of a fixed size. +/// +/// Provides common helpers for offset validation and address +/// calculation on top of a base address and maximum size. +/// +/// Types implementing this trait (e.g. MMIO BARs or PCI config +/// regions) can share the same accessors. +pub trait Io { + /// Minimum usable size + const MIN_SIZE: usize; =20 /// Returns the base address of this mapping. - #[inline] - pub fn addr(&self) -> usize { - self.0.addr() - } + fn addr(&self) -> usize; =20 /// Returns the maximum size of this mapping. - #[inline] - pub fn maxsize(&self) -> usize { - self.0.maxsize() - } - - #[inline] - const fn offset_valid(offset: usize, size: usize) -> bool { - let type_size =3D core::mem::size_of::(); - if let Some(end) =3D offset.checked_add(type_size) { - end <=3D size && offset % type_size =3D=3D 0 - } else { - false - } - } + fn maxsize(&self) -> usize; =20 + /// Returns the absolute I/O address for a given `offset`. + /// Performs runtime bounds checks using [`offset_valid`] #[inline] fn io_addr(&self, offset: usize) -> Result { - if !Self::offset_valid::(offset, self.maxsize()) { + if !offset_valid::(offset, self.maxsize()) { return Err(EINVAL); } =20 @@ -217,50 +218,157 @@ fn io_addr(&self, offset: usize) -> Result= { self.addr().checked_add(offset).ok_or(EINVAL) } =20 + /// Returns the absolute I/O address for a given `offset`, + /// performing compile-time bound checks. #[inline] fn io_addr_assert(&self, offset: usize) -> usize { - build_assert!(Self::offset_valid::(offset, SIZE)); + build_assert!(offset_valid::(offset, Self::MIN_SIZE)); =20 self.addr() + offset } =20 - define_read!(read8, try_read8, readb -> u8); - define_read!(read16, try_read16, readw -> u16); - define_read!(read32, try_read32, readl -> u32); + /// Infallible 8-bit read with compile-time bounds check. + fn read8(&self, offset: usize) -> u8; + + /// Infallible 16-bit read with compile-time bounds check. + fn read16(&self, offset: usize) -> u16; + + /// Infallible 32-bit read with compile-time bounds check. + fn read32(&self, offset: usize) -> u32; + + /// Fallible 8-bit read with runtime bounds check. + fn try_read8(&self, offset: usize) -> Result; + + /// Fallible 16-bit read with runtime bounds check. + fn try_read16(&self, offset: usize) -> Result; + + /// Fallible 32-bit read with runtime bounds check. + fn try_read32(&self, offset: usize) -> Result; + + /// Infallible 8-bit write with compile-time bounds check. + fn write8(&self, value: u8, offset: usize); + + /// Infallible 16-bit write with compile-time bounds check. + fn write16(&self, value: u16, offset: usize); + + /// Infallible 32-bit write with compile-time bounds check. + fn write32(&self, value: u32, offset: usize); + + /// Fallible 8-bit write with runtime bounds check. + fn try_write8(&self, value: u8, offset: usize) -> Result; + + /// Fallible 16-bit write with runtime bounds check. + fn try_write16(&self, value: u16, offset: usize) -> Result; + + /// Fallible 32-bit write with runtime bounds check. + fn try_write32(&self, value: u32, offset: usize) -> Result; +} + +/// Implement this trait if a backend supports 64-bit access. +pub trait Io64: Io { + /// Infallible 64-bit read with compile-time bounds check (64-bit only= ). + fn read64(&self, offset: usize) -> u64; + + /// Fallible 64-bit read with runtime bounds check (64-bit only). + fn try_read64(&self, offset: usize) -> Result; + + /// Infallible 64-bit write with compile-time bounds check (64-bit onl= y). + fn write64(&self, value: u64, offset: usize); + + /// Fallible 64-bit write with runtime bounds check (64-bit only). + fn try_write64(&self, value: u64, offset: usize) -> Result; +} + +impl Io for Mmio { + const MIN_SIZE: usize =3D SIZE; + + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + self.0.addr() + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.0.maxsize() + } + + define_read!(infallible, read8, readb -> u8); + define_read!(infallible, read16, readw -> u16); + define_read!(infallible, read32, readl -> u32); + + define_read!(fallible, try_read8, readb -> u8); + define_read!(fallible, try_read16, readw -> u16); + define_read!(fallible, try_read32, readl -> u32); + + define_write!(infallible, write8, writeb <- u8); + define_write!(infallible, write16, writew <- u16); + define_write!(infallible, write32, writel <- u32); + + define_write!(fallible, try_write8, writeb <- u8); + define_write!(fallible, try_write16, writew <- u16); + define_write!(fallible, try_write32, writel <- u32); +} + +#[cfg(CONFIG_64BIT)] +impl Io64 for Mmio { + define_read!(infallible, read64, readq -> u64); + define_read!(fallible, try_read64, readq -> u64); + + define_write!(infallible, write64, writeq <- u64); + define_write!(fallible, try_write64, writeq <- u64); +} + +impl Mmio { + /// Converts an `MmioRaw` into an `Mmio` instance, providing the acces= sors to the MMIO mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size + /// `maxsize`. + pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { + // SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`. + unsafe { &*core::ptr::from_ref(raw).cast() } + } + + define_read!(infallible, pub read8_relaxed, readb_relaxed -> u8); + define_read!(infallible, pub read16_relaxed, readw_relaxed -> u16); + define_read!(infallible, pub read32_relaxed, readl_relaxed -> u32); define_read!( + infallible, #[cfg(CONFIG_64BIT)] - read64, - try_read64, - readq -> u64 + pub read64_relaxed, + readq_relaxed -> u64 ); =20 - define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8); - define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16); - define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32); + define_read!(fallible, pub try_read8_relaxed, readb_relaxed -> u8); + define_read!(fallible, pub try_read16_relaxed, readw_relaxed -> u16); + define_read!(fallible, pub try_read32_relaxed, readl_relaxed -> u32); define_read!( + fallible, #[cfg(CONFIG_64BIT)] - read64_relaxed, - try_read64_relaxed, + pub try_read64_relaxed, readq_relaxed -> u64 ); =20 - define_write!(write8, try_write8, writeb <- u8); - define_write!(write16, try_write16, writew <- u16); - define_write!(write32, try_write32, writel <- u32); + define_write!(infallible, pub write8_relaxed, writeb_relaxed <- u8); + define_write!(infallible, pub write16_relaxed, writew_relaxed <- u16); + define_write!(infallible, pub write32_relaxed, writel_relaxed <- u32); define_write!( + infallible, #[cfg(CONFIG_64BIT)] - write64, - try_write64, - writeq <- u64 + pub write64_relaxed, + writeq_relaxed <- u64 ); =20 - define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8= ); - define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- = u16); - define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- = u32); + define_write!(fallible, pub try_write8_relaxed, writeb_relaxed <- u8); + define_write!(fallible, pub try_write16_relaxed, writew_relaxed <- u16= ); + define_write!(fallible, pub try_write32_relaxed, writel_relaxed <- u32= ); define_write!( + fallible, #[cfg(CONFIG_64BIT)] - write64_relaxed, - try_write64_relaxed, + pub try_write64_relaxed, writeq_relaxed <- u64 ); } diff --git a/rust/kernel/io/mem.rs b/rust/kernel/io/mem.rs index 6f99510bfc3a..93cad8539b18 100644 --- a/rust/kernel/io/mem.rs +++ b/rust/kernel/io/mem.rs @@ -11,8 +11,8 @@ use crate::io; use crate::io::resource::Region; use crate::io::resource::Resource; -use crate::io::Io; -use crate::io::IoRaw; +use crate::io::Mmio; +use crate::io::MmioRaw; use crate::prelude::*; =20 /// An IO request for a specific device and resource. @@ -195,7 +195,7 @@ pub fn new<'a>(io_request: IoRequest<'a>) -> impl PinIn= it, Error> + } =20 impl Deref for ExclusiveIoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { &self.iomem @@ -209,10 +209,10 @@ fn deref(&self) -> &Self::Target { /// /// # Invariants /// -/// [`IoMem`] always holds an [`IoRaw`] instance that holds a valid pointe= r to the +/// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid poin= ter to the /// start of the I/O memory mapped region. pub struct IoMem { - io: IoRaw, + io: MmioRaw, } =20 impl IoMem { @@ -247,7 +247,7 @@ fn ioremap(resource: &Resource) -> Result { return Err(ENOMEM); } =20 - let io =3D IoRaw::new(addr as usize, size)?; + let io =3D MmioRaw::new(addr as usize, size)?; let io =3D IoMem { io }; =20 Ok(io) @@ -270,10 +270,10 @@ fn drop(&mut self) { } =20 impl Deref for IoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { // SAFETY: Safe as by the invariant of `IoMem`. - unsafe { Io::from_raw(&self.io) } + unsafe { Mmio::from_raw(&self.io) } } } diff --git a/rust/kernel/io/poll.rs b/rust/kernel/io/poll.rs index 613eb25047ef..a9fea091303b 100644 --- a/rust/kernel/io/poll.rs +++ b/rust/kernel/io/poll.rs @@ -37,12 +37,12 @@ /// # Examples /// /// ```no_run -/// use kernel::io::{Io, poll::read_poll_timeout}; +/// use kernel::io::{Io, Mmio, poll::read_poll_timeout}; /// use kernel::time::Delta; /// /// const HW_READY: u16 =3D 0x01; /// -/// fn wait_for_hardware(io: &Io) -> Result<()> { +/// fn wait_for_hardware(io: &Mmio) -> Result<()>= { /// match read_poll_timeout( /// // The `op` closure reads the value of a specific status regis= ter. /// || io.try_read16(0x1000), diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 7fcc5f6022c1..77a8eb39ad32 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -10,7 +10,7 @@ devres::Devres, driver, error::{from_result, to_result, Result}, - io::{Io, IoRaw}, + io::{Mmio, MmioRaw}, irq::{self, IrqRequest}, str::CStr, sync::aref::ARef, @@ -313,7 +313,7 @@ pub struct Device( /// memory mapped PCI bar and its size. pub struct Bar { pdev: ARef, - io: IoRaw, + io: MmioRaw, num: i32, } =20 @@ -349,7 +349,7 @@ fn new(pdev: &Device, num: u32, name: &CStr) -> Result<= Self> { return Err(ENOMEM); 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Tue, 4 Nov 2025 06:28:15 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Nov 2025 06:28:14 -0800 Received: from inno-vm-xubuntu (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Nov 2025 06:28:05 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH RESEND v4 2/4] rust: io: factor out MMIO read/write macros Date: Tue, 4 Nov 2025 16:27:31 +0200 Message-ID: <20251104142733.5334-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251104142733.5334-1-zhiw@nvidia.com> References: <20251104142733.5334-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|MW4PR12MB7190:EE_ X-MS-Office365-Filtering-Correlation-Id: 89468016-6724-472e-9556-08de1bae6d98 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 14:28:30.8406 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89468016-6724-472e-9556-08de1bae6d98 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7190 Content-Type: text/plain; charset="utf-8" Refactor the existing MMIO accessors to use common call macros instead of inlining the bindings calls in each `define_{read,write}!` expansion. This factoring separates the common offset/bounds checks from the low-level call pattern, making it easier to add additional I/O accessor families. No functional change intended. Signed-off-by: Zhi Wang --- rust/kernel/io.rs | 114 +++++++++++++++++++++++++++++----------------- 1 file changed, 73 insertions(+), 41 deletions(-) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 0b1e79075c99..2f4206166b86 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -113,8 +113,34 @@ pub fn maxsize(&self) -> usize { #[repr(transparent)] pub struct Mmio(MmioRaw); =20 +macro_rules! call_mmio_read { + (infallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) =3D> { + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + unsafe { bindings::$c_fn($addr as *const c_void) as $type } + }; + + (fallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) =3D> {{ + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + Ok(unsafe { bindings::$c_fn($addr as *const c_void) as $type }) + }}; +} + +macro_rules! call_mmio_write { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr= ) =3D> { + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + unsafe { bindings::$c_fn($value, $addr as *mut c_void) } + }; + + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) = =3D> {{ + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + unsafe { bindings::$c_fn($value, $addr as *mut c_void) }; + Ok(()) + }}; +} + macro_rules! define_read { - (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident -> $t= ype_name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident= , $c_fn:ident -> + $type_name:ty) =3D> { /// Read IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile @@ -124,12 +150,13 @@ macro_rules! define_read { $vis fn $name(&self, offset: usize) -> $type_name { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(addr as *const c_void) } + // SAFETY: By the type invariant `addr` is a valid address for= IO operations. + $call_macro!(infallible, $c_fn, self, $type_name, addr) } }; =20 - (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident -> = $type_name:ty) =3D> { + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ide= nt, $c_fn:ident -> + $type_name:ty) =3D> { /// Read IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is @@ -138,14 +165,16 @@ macro_rules! define_read { $vis fn $try_name(&self, offset: usize) -> Result<$type_name> { let addr =3D self.io_addr::<$type_name>(offset)?; =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - Ok(unsafe { bindings::$c_fn(addr as *const c_void) }) + // SAFETY: By the type invariant `addr` is a valid address for= IO operations. + $call_macro!(fallible, $c_fn, self, $type_name, addr) } }; } +pub(crate) use define_read; =20 macro_rules! define_write { - (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident <- $t= ype_name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident= , $c_fn:ident <- + $type_name:ty) =3D> { /// Write IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile @@ -155,12 +184,12 @@ macro_rules! define_write { $vis fn $name(&self, value: $type_name, offset: usize) { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as *mut c_void) } + $call_macro!(infallible, $c_fn, self, $type_name, addr, value); } }; =20 - (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident <- = $type_name:ty) =3D> { + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ide= nt, $c_fn:ident <- + $type_name:ty) =3D> { /// Write IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is @@ -169,12 +198,11 @@ macro_rules! define_write { $vis fn $try_name(&self, value: $type_name, offset: usize) -> Resu= lt { let addr =3D self.io_addr::<$type_name>(offset)?; =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as *mut c_void) } - Ok(()) + $call_macro!(fallible, $c_fn, self, $type_name, addr, value) } }; } +pub(crate) use define_write; =20 /// Checks whether an access of type `U` at the given `offset` /// is valid within this region. @@ -294,30 +322,30 @@ fn maxsize(&self) -> usize { self.0.maxsize() } =20 - define_read!(infallible, read8, readb -> u8); - define_read!(infallible, read16, readw -> u16); - define_read!(infallible, read32, readl -> u32); + define_read!(infallible, read8, call_mmio_read, readb -> u8); + define_read!(infallible, read16, call_mmio_read, readw -> u16); + define_read!(infallible, read32, call_mmio_read, readl -> u32); =20 - define_read!(fallible, try_read8, readb -> u8); - define_read!(fallible, try_read16, readw -> u16); - define_read!(fallible, try_read32, readl -> u32); + define_read!(fallible, try_read8, call_mmio_read, readb -> u8); + define_read!(fallible, try_read16, call_mmio_read, readw -> u16); + define_read!(fallible, try_read32, call_mmio_read, readl -> u32); =20 - define_write!(infallible, write8, writeb <- u8); - define_write!(infallible, write16, writew <- u16); - define_write!(infallible, write32, writel <- u32); + define_write!(infallible, write8, call_mmio_write, writeb <- u8); + define_write!(infallible, write16, call_mmio_write, writew <- u16); + define_write!(infallible, write32, call_mmio_write, writel <- u32); =20 - define_write!(fallible, try_write8, writeb <- u8); - define_write!(fallible, try_write16, writew <- u16); - define_write!(fallible, try_write32, writel <- u32); + define_write!(fallible, try_write8, call_mmio_write, writeb <- u8); + define_write!(fallible, try_write16, call_mmio_write, writew <- u16); + define_write!(fallible, try_write32, call_mmio_write, writel <- u32); } =20 #[cfg(CONFIG_64BIT)] impl Io64 for Mmio { - define_read!(infallible, read64, readq -> u64); - define_read!(fallible, try_read64, readq -> u64); + define_read!(infallible, read64, call_mmio_read, readq -> u64); + define_read!(fallible, try_read64, call_mmio_read, readq -> u64); =20 - define_write!(infallible, write64, writeq <- u64); - define_write!(fallible, try_write64, writeq <- u64); + define_write!(infallible, write64, call_mmio_write, writeq <- u64); + define_write!(fallible, try_write64, call_mmio_write, writeq <- u64); } =20 impl Mmio { @@ -332,43 +360,47 @@ pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { unsafe { &*core::ptr::from_ref(raw).cast() } } =20 - define_read!(infallible, pub read8_relaxed, readb_relaxed -> u8); - define_read!(infallible, pub read16_relaxed, readw_relaxed -> u16); - define_read!(infallible, pub read32_relaxed, readl_relaxed -> u32); + define_read!(infallible, pub read8_relaxed, call_mmio_read, readb_rela= xed -> u8); + define_read!(infallible, pub read16_relaxed, call_mmio_read, readw_rel= axed -> u16); + define_read!(infallible, pub read32_relaxed, call_mmio_read, readl_rel= axed -> u32); define_read!( infallible, #[cfg(CONFIG_64BIT)] pub read64_relaxed, + call_mmio_read, readq_relaxed -> u64 ); =20 - define_read!(fallible, pub try_read8_relaxed, readb_relaxed -> u8); - define_read!(fallible, pub try_read16_relaxed, readw_relaxed -> u16); - define_read!(fallible, pub try_read32_relaxed, readl_relaxed -> u32); + define_read!(fallible, pub try_read8_relaxed, call_mmio_read, readb_re= laxed -> u8); + define_read!(fallible, pub try_read16_relaxed, call_mmio_read, readw_r= elaxed -> u16); + define_read!(fallible, pub try_read32_relaxed, call_mmio_read, readl_r= elaxed -> u32); define_read!( fallible, #[cfg(CONFIG_64BIT)] pub try_read64_relaxed, + call_mmio_read, readq_relaxed -> u64 ); =20 - define_write!(infallible, pub write8_relaxed, writeb_relaxed <- u8); - define_write!(infallible, pub write16_relaxed, writew_relaxed <- u16); - define_write!(infallible, pub write32_relaxed, writel_relaxed <- u32); + define_write!(infallible, pub write8_relaxed, call_mmio_write, writeb_= relaxed <- u8); + define_write!(infallible, pub write16_relaxed, call_mmio_write, writew= _relaxed <- u16); + define_write!(infallible, pub write32_relaxed, call_mmio_write, writel= _relaxed <- u32); define_write!( infallible, #[cfg(CONFIG_64BIT)] pub write64_relaxed, + call_mmio_write, writeq_relaxed <- u64 ); =20 - define_write!(fallible, pub try_write8_relaxed, writeb_relaxed <- u8); - define_write!(fallible, pub try_write16_relaxed, writew_relaxed <- u16= ); - define_write!(fallible, pub try_write32_relaxed, writel_relaxed <- u32= ); + define_write!(fallible, pub try_write8_relaxed, call_mmio_write, write= b_relaxed <- u8); + define_write!(fallible, pub try_write16_relaxed, call_mmio_write, writ= ew_relaxed <- u16); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 14:28:38.3975 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 035d0237-e42b-45ac-6970-08de1bae7219 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4044 Content-Type: text/plain; charset="utf-8" Drivers might need to access PCI config space for querying capability structures and access the registers inside the structures. For Rust drivers need to access PCI config space, the Rust PCI abstraction needs to support it in a way that upholds Rust's safety principles. Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe accessors for PCI config space. The new type implements the `Io` trait to share offset validation and bound-checking logic with others. Cc: Danilo Krummrich Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 148 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 142 insertions(+), 6 deletions(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 77a8eb39ad32..630660a7f05d 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -5,13 +5,31 @@ //! C header: [`include/linux/pci.h`](srctree/include/linux/pci.h) =20 use crate::{ - bindings, container_of, device, - device_id::{RawDeviceId, RawDeviceIdIndex}, + bindings, + container_of, + device, + device_id::{ + RawDeviceId, + RawDeviceIdIndex + }, devres::Devres, driver, - error::{from_result, to_result, Result}, - io::{Mmio, MmioRaw}, - irq::{self, IrqRequest}, + error::{ + from_result, + to_result, + Result + }, + io::{ + define_read, + define_write, + Io, + Mmio, + MmioRaw + }, + irq::{ + self, + IrqRequest + }, str::CStr, sync::aref::ARef, types::Opaque, @@ -20,7 +38,10 @@ use core::{ marker::PhantomData, ops::Deref, - ptr::{addr_of_mut, NonNull}, + ptr::{ + addr_of_mut, + NonNull + }, }; use kernel::prelude::*; =20 @@ -305,6 +326,83 @@ pub struct Device( PhantomData, ); =20 +/// Represents the PCI configuration space of a device. +/// +/// Provides typed read and write accessors for configuration registers +/// using the standard `pci_read_config_*` and `pci_write_config_*` helper= s. +/// +/// The generic const parameter `SIZE` can be used to indicate the +/// maximum size of the configuration space (e.g. 256 bytes for legacy, +/// 4096 bytes for extended config space). The actual size is obtained +/// from the underlying `struct pci_dev` via [`Device::cfg_size`]. +pub struct ConfigSpace<'a, const SIZE: usize =3D { ConfigSpaceSize::Extend= ed as usize }> { + pdev: &'a Device, +} + +macro_rules! call_config_read { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =3D> {{ + let mut val: $ty =3D 0; + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, &mut val) }; + match ret { + 0 =3D> val, + _ =3D> !0, + } + }}; + + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =3D> {{ + let mut val: $ty =3D 0; + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, &mut val) }; + (ret =3D=3D 0) + .then_some(Ok(val)) + .unwrap_or_else(|| Err(Error::from_errno(ret))) + }}; +} + +macro_rules! call_config_write { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr= ) =3D> { + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, $value) }; + }; + + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) = =3D> {{ + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, $value) }; + (ret =3D=3D 0) + .then_some(Ok(())) + .unwrap_or_else(|| Err(Error::from_errno(ret))) + }}; +} + +impl<'a, const SIZE: usize> Io for ConfigSpace<'a, SIZE> { + const MIN_SIZE: usize =3D SIZE; + + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + 0 + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.pdev.cfg_size().map_or(0, |v| v as usize) + } + + define_read!(infallible, read8, call_config_read, pci_read_config_byte= -> u8); + define_read!(infallible, read16, call_config_read, pci_read_config_wor= d -> u16); + define_read!(infallible, read32, call_config_read, pci_read_config_dwo= rd -> u32); + + define_read!(fallible, try_read8, call_config_read, pci_read_config_by= te -> u8); + define_read!(fallible, try_read16, call_config_read, pci_read_config_w= ord -> u16); + define_read!(fallible, try_read32, call_config_read, pci_read_config_d= word -> u32); + + define_write!(infallible, write8, call_config_write, pci_write_config_= byte <- u8); + define_write!(infallible, write16, call_config_write, pci_write_config= _word <- u16); + define_write!(infallible, write32, call_config_write, pci_write_config= _dword <- u32); + + define_write!(fallible, try_write8, call_config_write, pci_write_confi= g_byte <- u8); + define_write!(fallible, try_write16, call_config_write, pci_write_conf= ig_word <- u16); + define_write!(fallible, try_write32, call_config_write, pci_write_conf= ig_dword <- u32); +} + /// A PCI BAR to perform I/O-Operations on. /// /// # Invariants @@ -418,6 +516,19 @@ fn as_raw(&self) -> *mut bindings::pci_dev { } } =20 +/// Represents the size of a PCI configuration space. +/// +/// PCI devices can have either a *normal* (legacy) configuration space of= 256 bytes, +/// or an *extended* configuration space of 4096 bytes as defined in the P= CI Express +/// specification. +pub enum ConfigSpaceSize { + /// 256-byte legacy PCI configuration space. + Normal =3D 256, + + /// 4096-byte PCIe extended configuration space. + Extended =3D 4096, +} + impl Device { /// Returns the PCI vendor ID as [`Vendor`]. /// @@ -514,6 +625,17 @@ pub fn pci_class(&self) -> Class { // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. Class::from_raw(unsafe { (*self.as_raw()).class }) } + + /// Returns the size of configuration space. + fn cfg_size(&self) -> Result { + // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. + let size =3D unsafe { (*self.as_raw()).cfg_size }; + match size { + 256 =3D> Ok(ConfigSpaceSize::Normal), + 4096 =3D> Ok(ConfigSpaceSize::Extended), + _ =3D> Err(EINVAL), + } + } } =20 impl Device { @@ -591,6 +713,20 @@ pub fn set_master(&self) { // SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid = `struct pci_dev`. unsafe { bindings::pci_set_master(self.as_raw()) }; } + + /// Return an initialized config space object. + pub fn config_space<'a>( + &'a self, + ) -> Result> { + Ok(ConfigSpace { pdev: self }) + } + + /// Return an initialized config space object. + pub fn config_space_exteneded<'a>( + &'a self, + ) -> Result> { + Ok(ConfigSpace { pdev: self }) + } } =20 // SAFETY: `Device` is a transparent wrapper of a type that doesn't depend= on `Device`'s generic --=20 2.51.0 From nobody Sat Feb 7 02:36:50 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011017.outbound.protection.outlook.com [40.93.194.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46F3A3314D9; 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Tue, 4 Nov 2025 06:28:34 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Nov 2025 06:28:34 -0800 Received: from inno-vm-xubuntu (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Nov 2025 06:28:24 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines Date: Tue, 4 Nov 2025 16:27:33 +0200 Message-ID: <20251104142733.5334-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251104142733.5334-1-zhiw@nvidia.com> References: <20251104142733.5334-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B5:EE_|CH3PR12MB7572:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f1cbbfd-6606-48bd-3a55-08de1bae7579 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 14:28:44.1324 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f1cbbfd-6606-48bd-3a55-08de1bae7579 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7572 Content-Type: text/plain; charset="utf-8" Add tests exercising the PCI configuration space helpers. Suggested-by: Danilo Krummrich Signed-off-by: Zhi Wang --- samples/rust/rust_driver_pci.rs | 46 +++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci= .rs index 528e672b6b89..6f0324b6bdf6 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -58,6 +58,50 @@ fn testdev(index: &TestIndex, bar: &Bar0) -> Result= { =20 Ok(bar.read32(Regs::COUNT)) } + + fn config_space(pdev: &pci::Device) -> Result { + let config =3D pdev.config_space()?; + + // TODO: use the register!() macro for defining PCI configuration = space registers once it + // has been move out of nova-core. + dev_info!( + pdev.as_ref(), + "pci-testdev config space read8 rev ID: {:x}\n", + config.read8(0x8) + ); + + dev_info!( + pdev.as_ref(), + "pci-testdev config space read16 vendor ID: {:x}\n", + config.read16(0) + ); + + dev_info!( + pdev.as_ref(), + "pci-testdev config space read32 BAR 0: {:x}\n", + config.read32(0x10) + ); + + dev_info!( + pdev.as_ref(), + "pci-testdev config space try_read8 rev ID: {:x}\n", + config.try_read8(0x8)? + ); + + dev_info!( + pdev.as_ref(), + "pci-testdev config space try_read16 vendor ID: {:x}\n", + config.try_read16(0)? + ); + + dev_info!( + pdev.as_ref(), + "pci-testdev config space try_read32 BAR 0: {:x}\n", + config.try_read32(0x10)? + ); + + Ok(()) + } } =20 impl pci::Driver for SampleDriver { @@ -93,6 +137,8 @@ fn probe(pdev: &pci::Device, info: &Self::IdInfo) = -> Result Self::testdev(info, bar)? ); =20 + Self::config_space(pdev)?; + Ok(drvdata) } =20 --=20 2.51.0