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([103.218.174.23]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-ba1f2a80459sm2338616a12.15.2025.11.04.04.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Nov 2025 04:51:38 -0800 (PST) From: Sudarshan Shetty To: andersson@kernel.org, konradybcio@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sudarshan Shetty , Krzysztof Kozlowski Subject: [PATCH v5 1/2] dt-bindings: arm: qcom: talos-evk: Add QCS615 Talos EVK SMARC platform Date: Tue, 4 Nov 2025 18:21:25 +0530 Message-Id: <20251104125126.1006400-2-tessolveupstream@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104125126.1006400-1-tessolveupstream@gmail.com> References: <20251104125126.1006400-1-tessolveupstream@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add binding support for the Qualcomm Technologies, Inc. Talos EVK SMARC platform based on the QCS615 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Sudarshan Shetty --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 0a3222d6f368..a323be3d2ba2 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -862,6 +862,7 @@ properties: - items: - enum: - qcom,qcs615-ride + - qcom,talos-evk - const: qcom,qcs615 - const: qcom,sm6150 =20 --=20 2.34.1 From nobody Fri Dec 19 09:24:04 2025 Received: from mail-pg1-f175.google.com (mail-pg1-f175.google.com [209.85.215.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E25262ECEAC for ; Tue, 4 Nov 2025 12:51:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762260707; cv=none; b=ei8q1PRcA4t6O+lKR9C8CoVqVW6Vnjiru3VDK/QdDtvT+Byqw5whGRB0RLzWSfn0aXqswJbpLkDt4DwmOqIV3HyjSCG/cY80m0768LKIS3TJnQcaRmsZK5RZXAUAY0dncsyywEDW6vsPkA9W7VDqrAvXpC2+RG4EMy7GQDHbKvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762260707; c=relaxed/simple; bh=umN5l8StSYcAXX615IvJJ6xj97ou8axD767gnADwPGo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jkbjvYpczYB2gzspX0OkdIoSaOw7QYvvHY0eyBcpMJKDKvMNUPb2wZLJEEazEEH6G/83D+bfqvExdd1a+cuJE0IZPgZK2uUcetVK5Nj/DwpEINFouWo9V5ISa0oxmUWaHHkHa0eyCa0DVkH5cZNvjnq4bFIfC17GWnoyDw6XsOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PLdvuTDh; arc=none smtp.client-ip=209.85.215.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PLdvuTDh" Received: by mail-pg1-f175.google.com with SMTP id 41be03b00d2f7-b6ce696c18bso5015326a12.1 for ; Tue, 04 Nov 2025 04:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1762260704; x=1762865504; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B3dVV0fbe4+16JR+CzHEMp6pCup16uQ8IZ7ccH1sBow=; b=PLdvuTDh/VJENqPLNj/qwSyjFOVioD+k251R/cUFekOacN2foBIJq14aCbukgrBGZc DC3/UptApG4yjC/7lkSJw2q3tzXixbKLtjpBincdbo79210DZK3Kyj2SQWkMOuz7Qrzl oJpFjCPlYEwk5BsmR+hzV6uAzTftHHH+y+KiVZb45iF9eAS/gAdpjTyVOa5Pi08jAZWp dezJpDlSKy8pNNJTlT68dIN4s46no4kvkovdbkSe1xvJdFLUHufbmj96kTCTO0xLNu2l Ec9g39I80TJEu+QfZnViZ4+vqs2jiHDQdExHyusfnrB/exviw6QWqZtVdyvwHYwSgZKQ wJlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762260704; x=1762865504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B3dVV0fbe4+16JR+CzHEMp6pCup16uQ8IZ7ccH1sBow=; b=hphXmbfOSYPTCYy7OweRv3qNiYl7Ebjk2W832YQIoj7WFNMfzBCWTNqEhObF1taWyF s9+nrdrHx06GcBX8uBGBo+lkKu1dgyBC/DXkdRp2IAiDBmDtrLf9qrbnUpojPYsjOZoz 4/LvMh8Euo//3wrFqmSwRo5czW53a5b2mXjVuBmAxzCEWS02cNJGduMxxBtDACEQ3T2f 3PDqEj1iIk51/Ra7hep/GvEtRK3Jx5RKFJwTDv+T4WK+fnYTPyUyfjxnz/9HukXYYIMc 8ACSy5TsCnRxdOuz9JA9NmHmyVQDf1T0r/5bL5bq5YZeRK5WrhkqF5azzZZMh8rusgoB LbWw== X-Forwarded-Encrypted: i=1; AJvYcCWnwZrAp3Ei8H9tGMlhdbFteRws9O3hG+iozHraYCv4anyrGWrPhdgwB5uLwavvJ+KYJJ7+q74IAjW905c=@vger.kernel.org X-Gm-Message-State: AOJu0YyEs7PPrcGXIeThzfLSl4mBl0jf2qxZ6W+KNYnmIfdL1yByVhiZ o4wf4tX/78n+Y+oZCGMuCLQkzOv3bHNXv2mmz76zIPyv910cRB+iyuK1 X-Gm-Gg: ASbGncvx480Jq3nDjgqwp5G4YOHSvoQ4N0QYCP4XUm8wnp6sl8YjXBd5DOiXaMi+pBD wsBDbRpUJSuJMGOg9SwjcVKLmghNYKlebyFTNIXkYUmgXM8GDqxA9leBprJdMH01pL59lv1+6QM sdGS9mTzQZRfm0Wt56qZTiLnxlxwLkB6fFoULaeSZ1ipQ7dvppMZ5hP7aKgQyFcYgwpbmz4xyCL RHfcJe2YRcB7tQQsKkWG1vEzACfm/fHSTDClr8Ln4150voZ2mxtFrdQ/PjjOYtWn1JJqmP/IPLW XNgVyP1qrC3JmEWp9Ov1DWIW7mObn7j9p1k9q/aNndrMjYafRo0vdzqEntMvzqn9SpP50of4Kqw x2UtlEwSNc1qMZHxD2b2vMVMHG1aefeVlkGHM/zrpOHf0ne9sqwI6OjQPAmaI64GQP+kETlgFmB bo95bJdVL+4T6pu6rIzPxpu81eRA== X-Google-Smtp-Source: AGHT+IG/kMf8g4KPNtRZsfexK25BQmufHhX3PH2hXFkK4FhnW4rIgdDTyRQI9AX4JIUsoV/3C0s/0g== X-Received: by 2002:a05:6a20:9151:b0:2e5:c9ee:96fb with SMTP id adf61e73a8af0-348cd20f92amr23820110637.59.1762260704020; Tue, 04 Nov 2025 04:51:44 -0800 (PST) Received: from test-HP-Desktop-Pro-G3.. ([103.218.174.23]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-ba1f2a80459sm2338616a12.15.2025.11.04.04.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Nov 2025 04:51:43 -0800 (PST) From: Sudarshan Shetty To: andersson@kernel.org, konradybcio@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sudarshan Shetty Subject: [PATCH v5 2/2] arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board Date: Tue, 4 Nov 2025 18:21:26 +0530 Message-Id: <20251104125126.1006400-3-tessolveupstream@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104125126.1006400-1-tessolveupstream@gmail.com> References: <20251104125126.1006400-1-tessolveupstream@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the device tree support for the QCS615-based talos-evk platform, which follows the SMARC (Smart Mobility ARChitecture) standard. The platform is composed of two main hardware components: the talos-evk-som and the talos-evk carrier board. The initial device tree includes basic support for: - CPU and memory - UART - GPIOs - Regulators - PMIC - Early console - AT24MAC602 EEPROM - MCP2515 SPI to CAN - ADV7535 DSI-to-HDMI bridge - DisplayPort Signed-off-by: Sudarshan Shetty --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/talos-evk-cb.dtsi | 56 +++ arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 442 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/talos-evk.dts | 87 ++++ 4 files changed, 586 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-cb.dtsi create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-som.dtsi create mode 100644 arch/arm64/boot/dts/qcom/talos-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 5b52f9e4e5f3..282d744acd73 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -305,6 +305,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D talos-evk.dtb x1e001de-devkit-el2-dtbs :=3D x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1e001de-devkit.dtb x1e001de-devkit-el2.dtb x1e78100-lenovo-thinkpad-t14s-el2-dtbs :=3D x1e78100-lenovo-thinkpad-t14s.= dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/talos-evk-cb.dtsi b/arch/arm64/boot/d= ts/qcom/talos-evk-cb.dtsi new file mode 100644 index 000000000000..81d15ee4f366 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-cb.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "talos-evk-som.dtsi" + +/ { + model =3D "Qualcomm QCS615 IQ 615 EVK"; + compatible =3D "qcom,talos-evk", "qcom,qcs615", "qcom,sm6150"; + chassis-type =3D "embedded"; + + aliases { + mmc1 =3D &sdhc_2; + }; + + dp-connector { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + + hpd-gpios =3D <&tlmm 104 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; + }; + }; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&sdhc_2 { + pinctrl-0 =3D <&sdc2_state_on>; + pinctrl-1 =3D <&sdc2_state_off>; + pinctrl-names =3D "default", "sleep"; + + bus-width =3D <4>; + cd-gpios =3D <&tlmm 99 GPIO_ACTIVE_LOW>; + + vmmc-supply =3D <&vreg_l10a>; + vqmmc-supply =3D <&vreg_s4a>; + + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/= dts/qcom/talos-evk-som.dtsi new file mode 100644 index 000000000000..1acb6997156a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include +#include +#include "sm6150.dtsi" +#include "pm8150.dtsi" +/ { + aliases { + mmc0 =3D &sdhc_1; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + }; + + regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "USB2_VBUS"; + gpio =3D <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&usb2_en>; + pinctrl-names =3D "default"; + enable-active-high; + regulator-always-on; + }; + + vreg_v3p3_can: regulator-v3p3-can { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v3p3-can"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v5p0_can: regulator-v5p0-can { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v5p0-can"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_s3a: smps3 { + regulator-name =3D "vreg_s3a"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <650000>; + regulator-initial-mode =3D ; + }; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1829000>; + regulator-initial-mode =3D ; + }; + + vreg_s5a: smps5 { + regulator-name =3D "vreg_s5a"; + regulator-min-microvolt =3D <1896000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + + vreg_s6a: smps6 { + regulator-name =3D "vreg_s6a"; + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1404000>; + regulator-initial-mode =3D ; + }; + + vreg_l1a: ldo1 { + regulator-name =3D "vreg_l1a"; + regulator-min-microvolt =3D <488000>; + regulator-max-microvolt =3D <852000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2a: ldo2 { + regulator-name =3D "vreg_l2a"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1248000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <875000>; + regulator-max-microvolt =3D <975000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1900000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10a: ldo10 { + regulator-name =3D "vreg_l10a"; + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11a: ldo11 { + regulator-name =3D "vreg_l11a"; + regulator-min-microvolt =3D <1232000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12a: ldo12 { + regulator-name =3D "vreg_l12a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1890000>; + regulator-initial-mode =3D ; + }; + + vreg_l13a: ldo13 { + regulator-name =3D "vreg_l13a"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3230000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15a: ldo15 { + regulator-name =3D "vreg_l15a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16a: ldo16 { + regulator-name =3D "vreg_l16a"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17a: ldo17 { + regulator-name =3D "vreg_l17a"; + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&i2c5 { + status =3D "okay"; + + eeprom@57 { + compatible =3D "atmel,24c02"; + reg =3D <0x57>; + pagesize =3D <16>; + }; + + eeprom@5f { + compatible =3D "atmel,24mac602"; + reg =3D <0x5f>; + pagesize =3D <16>; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint =3D <&dp0_connector_in>; +}; + +&mdss_dp_phy { + vdda-phy-supply =3D <&vreg_l11a>; + vdda-pll-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l11a>; + + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&adv7535_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&pcie { + perst-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + +&pm8150_gpios { + usb2_en: usb2-en-state { + pins =3D "gpio10"; + function =3D "normal"; + output-enable; + power-source =3D <0>; + }; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/qcs615/adsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/qcs615/cdsp.mbn"; + + status =3D "okay"; +}; + +&sdhc_1 { + pinctrl-0 =3D <&sdc1_state_on>; + pinctrl-1 =3D <&sdc1_state_off>; + pinctrl-names =3D "default", "sleep"; + + bus-width =3D <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + vmmc-supply =3D <&vreg_l17a>; + vqmmc-supply =3D <&vreg_s4a>; + + non-removable; + no-sd; + no-sdio; + + status =3D "okay"; +}; + +&spi6 { + status =3D "okay"; + + can@0 { + compatible =3D "microchip,mcp2515"; + reg =3D <0>; + clock-frequency =3D <20000000>; + interrupts-extended =3D <&tlmm 87 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency =3D <10000000>; + vdd-supply =3D <&vreg_v3p3_can>; + xceiver-supply =3D <&vreg_v5p0_can>; + }; +}; + +&tlmm { + pcie_default_state: pcie-default-state { + clkreq-pins { + pins =3D "gpio90"; + function =3D "pcie_clk_req"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio101"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wake-pins { + pins =3D "gpio100"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + vdda-phy-dpdm-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_hsphy_2 { + vdd-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + vdda-phy-dpdm-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_2 { + status =3D "okay"; +}; + +&usb_2_dwc3 { + dr_mode =3D "host"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 123 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l17a>; + vcc-max-microamp =3D <600000>; + vccq2-supply =3D <&vreg_s4a>; + vccq2-max-microamp =3D <600000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + +&venus { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/q= com/talos-evk.dts new file mode 100644 index 000000000000..a099fbafb6a2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "talos-evk-cb.dtsi" + +/ { + hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint =3D <&adv7535_out>; + }; + }; + }; + + vreg_v5p0_out: regulator-v5p0-out { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v5p0-out"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + /* Powered by system 20V rail (USBC_VBUS_IN) */ + }; + + vreg_v3p3_out: regulator-v3p3-out { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v3p3-out"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vreg_v5p0_out>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v1p8_out: regulator-v1p8-out { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v1p8-out"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vreg_v5p0_out>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + bridge: bridge@3d { + compatible =3D "adi,adv7535"; + reg =3D <0x3d>; + avdd-supply =3D <&vreg_v1p8_out>; + dvdd-supply =3D <&vreg_v1p8_out>; + pvdd-supply =3D <&vreg_v1p8_out>; + a2vdd-supply =3D <&vreg_v1p8_out>; + v3p3-supply =3D <&vreg_v3p3_out>; + interrupts-extended =3D <&tlmm 26 IRQ_TYPE_LEVEL_LOW>; + adi,dsi-lanes =3D <4>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + adv7535_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + adv7535_out: endpoint { + remote-endpoint =3D <&hdmi_con_out>; + }; + }; + }; + }; +}; --=20 2.34.1