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charset="utf-8" Enable Inline Crypto Engine (ICE) support for eMMC devices that operate without Command Queue Engine (CQE).This allows hardware-accelerated encryption and decryption for standard (non-CMDQ) requests. This patch: - Adds ICE register definitions for non-CMDQ crypto configuration - Implements a per-request crypto setup via sdhci_msm_ice_cfg() - Hooks into the request path via mmc_host_ops.request - Initializes ICE hardware during CQE setup for compatible platforms With this, non-CMDQ eMMC devices can benefit from inline encryption, improving performance for encrypted I/O while maintaining compatibility with existing CQE crypto support. Signed-off-by: Md Sadre Alam Acked-by: Adrian Hunter --- Change in [v3] * Refactored logic to use separate code paths for crypto_ctx !=3D NULL and crypto_ctx =3D=3D NULL to improve readability. * Renamed bypass to crypto_enable to align with bitfield semantics. * Removed slot variable * Added ICE initialization sequence for non-CMDQ eMMC devices before __sdhci_add_host() Change in [v2] * Moved NONCQ_CRYPTO_PARM and NONCQ_CRYPTO_DUN register definitions into sdhci-msm.c * Introduced use of GENMASK() and FIELD_PREP() macros for cleaner and more maintainable bitfield handling in ICE configuration. * Removed redundant if (!mrq || !cq_host) check from sdhci_msm_ice_cfg() as both are guaranteed to be valid in the current call path. * Added assignment of host->mmc_host_ops.request =3D sdhci_msm_request; to integrate ICE configuration into the standard request path for non-CMDQ eMMC devices. * Removed sdhci_crypto_cfg() from sdhci.c and its invocation in sdhci_reque= st() Change in [v1] * Added initial support for Inline Crypto Engine (ICE) on non-CMDQ eMMC devices. drivers/mmc/host/sdhci-msm.c | 71 ++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4e5edbf2fc9b..6ce205238720 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -157,6 +157,18 @@ #define CQHCI_VENDOR_CFG1 0xA00 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13) =20 +/* non command queue crypto enable register*/ +#define NONCQ_CRYPTO_PARM 0x70 +#define NONCQ_CRYPTO_DUN 0x74 + +#define DISABLE_CRYPTO BIT(15) +#define CRYPTO_GENERAL_ENABLE BIT(1) +#define HC_VENDOR_SPECIFIC_FUNC4 0x260 +#define ICE_HCI_SUPPORT BIT(28) + +#define ICE_HCI_PARAM_CCI GENMASK(7, 0) +#define ICE_HCI_PARAM_CE GENMASK(8, 8) + struct sdhci_msm_offset { u32 core_hc_mode; u32 core_mci_data_cnt; @@ -1885,6 +1897,48 @@ static void sdhci_msm_set_clock(struct sdhci_host *h= ost, unsigned int clock) =20 #ifdef CONFIG_MMC_CRYPTO =20 +static int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *= mrq) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + struct mmc_host *mmc =3D msm_host->mmc; + struct cqhci_host *cq_host =3D mmc->cqe_private; + unsigned int crypto_params =3D 0; + int key_index; + bool crypto_enable; + u64 dun =3D 0; + + if (mrq->crypto_ctx) { + crypto_enable =3D true; + dun =3D mrq->crypto_ctx->bc_dun[0]; + key_index =3D mrq->crypto_key_slot; + crypto_params =3D FIELD_PREP(ICE_HCI_PARAM_CE, crypto_enable) | + FIELD_PREP(ICE_HCI_PARAM_CCI, key_index); + + cqhci_writel(cq_host, crypto_params, NONCQ_CRYPTO_PARM); + cqhci_writel(cq_host, lower_32_bits(dun), NONCQ_CRYPTO_DUN); + } else { + crypto_enable =3D false; + key_index =3D 0; + cqhci_writel(cq_host, crypto_params, NONCQ_CRYPTO_PARM); + } + + /* Ensure crypto configuration is written before proceeding */ + wmb(); + + return 0; +} + +static void sdhci_msm_request(struct mmc_host *mmc, struct mmc_request *mr= q) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + + if (mmc->caps2 & MMC_CAP2_CRYPTO) + sdhci_msm_ice_cfg(host, mrq); + + sdhci_request(mmc, mrq); +} + static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward dec= l */ =20 static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, @@ -2131,6 +2185,8 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *= host, struct cqhci_host *cq_host; bool dma64; u32 cqcfg; + u32 config; + u32 ice_cap; int ret; =20 /* @@ -2181,6 +2237,18 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host = *host, if (host->flags & SDHCI_USE_64_BIT_DMA) host->desc_sz =3D 12; =20 + /* Initialize ICE for non-CMDQ eMMC devices */ + config =3D sdhci_readl(host, HC_VENDOR_SPECIFIC_FUNC4); + config &=3D ~DISABLE_CRYPTO; + sdhci_writel(host, config, HC_VENDOR_SPECIFIC_FUNC4); + ice_cap =3D cqhci_readl(cq_host, CQHCI_CAP); + if (ice_cap & ICE_HCI_SUPPORT) { + config =3D cqhci_readl(cq_host, CQHCI_CFG); + config |=3D CRYPTO_GENERAL_ENABLE; + cqhci_writel(cq_host, config, CQHCI_CFG); + } + sdhci_msm_ice_enable(msm_host); + ret =3D __sdhci_add_host(host); if (ret) goto cleanup; @@ -2759,6 +2827,9 @@ static int sdhci_msm_probe(struct platform_device *pd= ev) =20 msm_host->mmc->caps |=3D MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; =20 +#ifdef CONFIG_MMC_CRYPTO + host->mmc_host_ops.request =3D sdhci_msm_request; +#endif /* Set the timeout value to max possible */ host->max_timeout_count =3D 0xF; =20 --=20 2.34.1