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This value is used by the ASPM driver to compute the LTR_L1.2_THRESHOLD. Currently, the root port exposes a T_POWER_ON value of zero in the L1SS capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations. This can result in improper L1.2 exit behavior and can trigger AER's. To address this, program the T_POWER_ON value to 80us (scale =3D 1, value =3D 8) in the PCI_L1SS_CAP register during host initialization. This ensures that ASPM can take the root port's T_POWER_ON value into account while calculating the LTR_L1.2_THRESHOLD value. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index c48a20602d7fa4c50056ccf6502d3b5bf0a8287f..52a3412bd2584c8bf5d281fa6a0= ed22141ad1989 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1252,6 +1252,27 @@ static bool qcom_pcie_link_up(struct dw_pcie *pci) return val & PCI_EXP_LNKSTA_DLLLA; } =20 +static void qcom_pcie_program_t_pwr_on(struct dw_pcie *pci) +{ + u16 offset; + u32 val; + + offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); + if (offset) { + dw_pcie_dbi_ro_wr_en(pci); + + val =3D readl(pci->dbi_base + offset + PCI_L1SS_CAP); + /* Program T power ON value to 80us */ + val &=3D ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE); + val |=3D FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_SCALE, 1); + val |=3D FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_VALUE, 8); + + writel(val, pci->dbi_base + offset + PCI_L1SS_CAP); + + dw_pcie_dbi_ro_wr_dis(pci); + } +} + static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) { struct qcom_pcie_port *port; @@ -1302,6 +1323,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) goto err_disable_phy; } =20 + qcom_pcie_program_t_pwr_on(pci); + qcom_ep_reset_deassert(pcie); =20 if (pcie->cfg->ops->config_sid) { --- base-commit: c9cfc122f03711a5124b4aafab3211cf4d35a2ac change-id: 20251104-t_power_on_fux-70dc68377941 Best regards, --=20 Krishna Chaitanya Chundru