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Mon, 03 Nov 2025 23:36:57 -0800 (PST) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3415c8b5cfcsm3484367a91.19.2025.11.03.23.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Nov 2025 23:36:57 -0800 (PST) From: Mukesh Ojha Date: Tue, 04 Nov 2025 13:05:53 +0530 Subject: [PATCH v6 13/14] remoteproc: qcom: pas: Enable Secure PAS support with IOMMU managed by Linux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251104-kvm_rproc_v6-v6-13-7017b0adc24e@oss.qualcomm.com> References: <20251104-kvm_rproc_v6-v6-0-7017b0adc24e@oss.qualcomm.com> In-Reply-To: <20251104-kvm_rproc_v6-v6-0-7017b0adc24e@oss.qualcomm.com> To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mukesh Ojha X-Mailer: b4 0.14-dev-f7c49 X-Developer-Signature: v=1; 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This includes mapping memory regions and device memory resources for remote processors by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are later removed during teardown. Additionally, SHM bridge setup is required to enable memory protection for both remoteproc metadata and its memory regions. When the aforementioned hypervisor is absent, the operating system must perform these configurations instead. When Linux runs as the hypervisor (@ EL2) on a SoC, it will have its own device tree overlay file that specifies the firmware stream ID now managed by Linux for a particular remote processor. If the iommus property is specified in the remoteproc device tree node, it indicates that IOMMU configuration must be handled by Linux. In this case, the has_iommu flag is set for the remote processor, which ensures that the resource table, carveouts, and SHM bridge are properly configured before memory is passed to TrustZone for authentication. Otherwise, the has_iommu flag remains unset, which indicates default behavior. Enables Secure PAS support for remote processors when IOMMU configuration is managed by Linux. Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 48 ++++++++++++++++++++++++++++++++++= ---- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index a8d3d2e9a70e..59196a13e3a1 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -256,6 +257,22 @@ static int qcom_pas_load(struct rproc *rproc, const st= ruct firmware *fw) return ret; } =20 +static void qcom_pas_unmap_carveout(struct rproc *rproc, phys_addr_t mem_p= hys, size_t size) +{ + if (rproc->has_iommu) + iommu_unmap(rproc->domain, mem_phys, size); +} + +static int qcom_pas_map_carveout(struct rproc *rproc, phys_addr_t mem_phys= , size_t size) +{ + int ret =3D 0; + + if (rproc->has_iommu) + ret =3D iommu_map(rproc->domain, mem_phys, mem_phys, size, + IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); + return ret; +} + static int qcom_pas_start(struct rproc *rproc) { struct qcom_pas *pas =3D rproc->priv; @@ -290,11 +307,15 @@ static int qcom_pas_start(struct rproc *rproc) } =20 if (pas->dtb_pas_id) { - ret =3D qcom_scm_pas_auth_and_reset(pas->dtb_pas_id); + ret =3D qcom_pas_map_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_siz= e); + if (ret) + goto disable_px_supply; + + ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->dtb_pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate dtb image and release reset\n"); - goto disable_px_supply; + goto unmap_dtb_carveout; } } =20 @@ -305,18 +326,22 @@ static int qcom_pas_start(struct rproc *rproc) =20 qcom_pil_info_store(pas->info_name, pas->mem_phys, pas->mem_size); =20 - ret =3D qcom_scm_pas_auth_and_reset(pas->pas_id); + ret =3D qcom_pas_map_carveout(rproc, pas->mem_phys, pas->mem_size); + if (ret) + goto release_pas_metadata; + + ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate image and release reset\n"); - goto release_pas_metadata; + goto unmap_carveout; } =20 ret =3D qcom_q6v5_wait_for_start(&pas->q6v5, msecs_to_jiffies(5000)); if (ret =3D=3D -ETIMEDOUT) { dev_err(pas->dev, "start timed out\n"); qcom_scm_pas_shutdown(pas->pas_id); - goto release_pas_metadata; + goto unmap_carveout; } =20 qcom_scm_pas_metadata_release(pas->pas_ctx); @@ -328,10 +353,16 @@ static int qcom_pas_start(struct rproc *rproc) =20 return 0; =20 +unmap_carveout: + qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); release_pas_metadata: qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + +unmap_dtb_carveout: + if (pas->dtb_pas_id) + qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size); disable_px_supply: if (pas->px_supply) regulator_disable(pas->px_supply); @@ -387,8 +418,12 @@ static int qcom_pas_stop(struct rproc *rproc) ret =3D qcom_scm_pas_shutdown(pas->dtb_pas_id); if (ret) dev_err(pas->dev, "failed to shutdown dtb: %d\n", ret); + + qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size); } =20 + qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); + handover =3D qcom_q6v5_unprepare(&pas->q6v5); if (handover) qcom_pas_handover(&pas->q6v5); @@ -758,6 +793,7 @@ static int qcom_pas_probe(struct platform_device *pdev) return -ENOMEM; } =20 + rproc->has_iommu =3D of_property_present(pdev->dev.of_node, "iommus"); rproc->auto_boot =3D desc->auto_boot; rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); =20 @@ -837,6 +873,8 @@ static int qcom_pas_probe(struct platform_device *pdev) goto remove_ssr_sysmon; } =20 + pas->pas_ctx->has_iommu =3D rproc->has_iommu; + pas->dtb_pas_ctx->has_iommu =3D rproc->has_iommu; ret =3D rproc_add(rproc); if (ret) goto remove_ssr_sysmon; --=20 2.50.1