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Mon, 03 Nov 2025 06:10:06 -0800 (PST) From: Usama Arif To: dwmw@amazon.co.uk, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, ardb@kernel.org, hpa@zytor.com Cc: x86@kernel.org, apopple@nvidia.com, thuth@redhat.com, nik.borisov@suse.com, kas@kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kernel-team@meta.com, Usama Arif , Michael van der Westhuizen , Tobias Fleig Subject: [PATCH v3 1/2] x86/boot: Fix page table access in 5-level to 4-level paging transition Date: Mon, 3 Nov 2025 14:09:22 +0000 Message-ID: <20251103141002.2280812-2-usamaarif642@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251103141002.2280812-1-usamaarif642@gmail.com> References: <20251103141002.2280812-1-usamaarif642@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When transitioning from 5-level to 4-level paging, the existing code incorrectly accesses page table entries by directly dereferencing CR3 and applying PAGE_MASK. This approach has several issues: - __native_read_cr3() returns the raw CR3 register value, which on x86_64 includes not just the physical address but also flags. Bits above the physical address width of the system i.e. above __PHYSICAL_MASK_SHIFT) are also not masked. - The PGD entry is masked by PAGE_SIZE which doesn't take into account the higher bits such as _PAGE_BIT_NOPTISHADOW. Replace this with proper accessor functions: - native_read_cr3_pa(): Uses CR3_ADDR_MASK to additionally mask metadata out of CR3 (like SME or LAM bits). All remaining bits are real address bits or reserved and must be 0. - mask pgd value with PTE_PFN_MASK instead of PAGE_MASK, accounting for flags above bit 51 (_PAGE_BIT_NOPTISHADOW in particular). Bits below 51, but above the max physical address are reserved and must be 0. Fixes: e9d0e6330eb8 ("x86/boot/compressed/64: Prepare new top-level page ta= ble for trampoline") Co-developed-by: Kiryl Shutsemau Signed-off-by: Kiryl Shutsemau Signed-off-by: Usama Arif Reported-by: Michael van der Westhuizen Reported-by: Tobias Fleig Reviewed-by: Ard Biesheuvel Acked-by: Dave Hansen --- arch/x86/boot/compressed/pgtable_64.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compress= ed/pgtable_64.c index bdd26050dff77..0e89e197e1126 100644 --- a/arch/x86/boot/compressed/pgtable_64.c +++ b/arch/x86/boot/compressed/pgtable_64.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include "../string.h" #include "efi.h" @@ -168,9 +169,10 @@ asmlinkage void configure_5level_paging(struct boot_pa= rams *bp, void *pgtable) * For 4- to 5-level paging transition, set up current CR3 as * the first and the only entry in a new top-level page table. */ - *trampoline_32bit =3D __native_read_cr3() | _PAGE_TABLE_NOENC; + *trampoline_32bit =3D native_read_cr3_pa() | _PAGE_TABLE_NOENC; } else { - unsigned long src; + u64 *new_cr3; + pgd_t *pgdp; =20 /* * For 5- to 4-level paging transition, copy page table pointed @@ -180,8 +182,9 @@ asmlinkage void configure_5level_paging(struct boot_par= ams *bp, void *pgtable) * We cannot just point to the page table from trampoline as it * may be above 4G. */ - src =3D *(unsigned long *)__native_read_cr3() & PAGE_MASK; - memcpy(trampoline_32bit, (void *)src, PAGE_SIZE); + pgdp =3D (pgd_t *)native_read_cr3_pa(); + new_cr3 =3D (u64 *)(native_pgd_val(pgdp[0]) & PTE_PFN_MASK); + memcpy(trampoline_32bit, new_cr3, PAGE_SIZE); } =20 toggle_la57(trampoline_32bit); --=20 2.47.3 From nobody Sat Feb 7 08:24:13 2026 Received: from mail-yx1-f49.google.com (mail-yx1-f49.google.com [74.125.224.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33CE12D8DB8 for ; Mon, 3 Nov 2025 14:10:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 03 Nov 2025 06:10:07 -0800 (PST) Received: from localhost ([2a03:2880:25ff:50::]) by smtp.gmail.com with ESMTPSA id 00721157ae682-78691db135esm935267b3.14.2025.11.03.06.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Nov 2025 06:10:07 -0800 (PST) From: Usama Arif To: dwmw@amazon.co.uk, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, ardb@kernel.org, hpa@zytor.com Cc: x86@kernel.org, apopple@nvidia.com, thuth@redhat.com, nik.borisov@suse.com, kas@kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kernel-team@meta.com, Usama Arif , Michael van der Westhuizen , Tobias Fleig Subject: [PATCH v3 2/2] efi/libstub: Fix page table access in 5-level to 4-level paging transition Date: Mon, 3 Nov 2025 14:09:23 +0000 Message-ID: <20251103141002.2280812-3-usamaarif642@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251103141002.2280812-1-usamaarif642@gmail.com> References: <20251103141002.2280812-1-usamaarif642@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When transitioning from 5-level to 4-level paging, the existing code incorrectly accesses page table entries by directly dereferencing CR3 and applying PAGE_MASK. This approach has several issues: - __native_read_cr3() returns the raw CR3 register value, which on x86_64 includes not just the physical address but also flags Bits above the physical address width of the system (i.e. above __PHYSICAL_MASK_SHIFT) are also not masked. - The pgd value is masked by PAGE_SIZE which doesn't take into account the higher bits such as _PAGE_BIT_NOPTISHADOW. Replace this with proper accessor functions: - native_read_cr3_pa(): Uses CR3_ADDR_MASK to additionally mask metadata out of CR3 (like SME or LAM bits). All remaining bits are real address bits or reserved and must be 0. - mask pgd value with PTE_PFN_MASK instead of PAGE_MASK, accounting for flags above bit 51 (_PAGE_BIT_NOPTISHADOW in particular). Bits below 51, but above the max physical address are reserved and must be 0. Fixes: cb1c9e02b0c1 ("x86/efistub: Perform 4/5 level paging switch from the= stub") Co-developed-by: Kiryl Shutsemau Signed-off-by: Kiryl Shutsemau Signed-off-by: Usama Arif Reported-by: Michael van der Westhuizen Reported-by: Tobias Fleig Reviewed-by: Ard Biesheuvel --- drivers/firmware/efi/libstub/x86-5lvl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi= /libstub/x86-5lvl.c index f1c5fb45d5f7c..c00d0ae7ed5d5 100644 --- a/drivers/firmware/efi/libstub/x86-5lvl.c +++ b/drivers/firmware/efi/libstub/x86-5lvl.c @@ -66,7 +66,7 @@ void efi_5level_switch(void) bool have_la57 =3D native_read_cr4() & X86_CR4_LA57; bool need_toggle =3D want_la57 ^ have_la57; u64 *pgt =3D (void *)la57_toggle + PAGE_SIZE; - u64 *cr3 =3D (u64 *)__native_read_cr3(); + pgd_t *cr3 =3D (pgd_t *)native_read_cr3_pa(); u64 *new_cr3; =20 if (!la57_toggle || !need_toggle) @@ -82,7 +82,7 @@ void efi_5level_switch(void) new_cr3[0] =3D (u64)cr3 | _PAGE_TABLE_NOENC; } else { /* take the new root table pointer from the current entry #0 */ - new_cr3 =3D (u64 *)(cr3[0] & PAGE_MASK); + new_cr3 =3D (u64 *)(native_pgd_val(cr3[0]) & PTE_PFN_MASK); =20 /* copy the new root table if it is not 32-bit addressable */ if ((u64)new_cr3 > U32_MAX) --=20 2.47.3