From nobody Mon Feb 9 20:30:11 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BDD2B28DB3 for ; Mon, 3 Nov 2025 05:26:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147591; cv=none; b=aWWkDwOu0T9pvappKy/BfWOhb7VQftsV72LrsBFXb2Dgrzr6N/ELljcd9mo/9+8N+IK125P0qSTRsh2T1kSgetRdAX/BjUVXoBDe0v/mANRQKrwUEYNOJ9sDY+ZLNseH0lO3R21qXfD+rLZ7ovIRm1hmg4dL0ASCUfcY1KQ1gdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147591; c=relaxed/simple; bh=+8B9nK2NwQ4tZJu3O02bdjaoACAiFxg47VSJaGzF8IU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XHg34NmKX+gHfEcFzWu3obPiQzC//XbKWTcrokjIhN1GJKL5U3NJm5XqfDhphHtyf+VUruy7EB8z+l53D0xiLrGHFMkDr7DUuy00LbRbMRUf0cXbaEpqFe3zD4D0Mqe39vaMEmvbZ7EW/lJG/N6n83kwXOVuifwxZKHPB/9U4us= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F02E7292B; Sun, 2 Nov 2025 21:26:19 -0800 (PST) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6E7403F63F; Sun, 2 Nov 2025 21:26:26 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 1/6] arm64/mm: Directly use TTBRx_EL1_ASID_MASK Date: Mon, 3 Nov 2025 05:26:13 +0000 Message-Id: <20251103052618.586763-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251103052618.586763-1-anshuman.khandual@arm.com> References: <20251103052618.586763-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace all TTBR_ASID_MASK macro instances with TTBRx_EL1_ASID_MASK which is a standard field mask from tools sysreg format. No functional change. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/asm-uaccess.h | 2 +- arch/arm64/include/asm/mmu_context.h | 2 +- arch/arm64/include/asm/uaccess.h | 6 +++--- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/context.c | 6 +++--- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/= asm-uaccess.h index 9148f5a31968..12aa6a283249 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -15,7 +15,7 @@ #ifdef CONFIG_ARM64_SW_TTBR0_PAN .macro __uaccess_ttbr0_disable, tmp1 mrs \tmp1, ttbr1_el1 // swapper_pg_dir - bic \tmp1, \tmp1, #TTBR_ASID_MASK + bic \tmp1, \tmp1, #TTBRx_EL1_ASID_MASK sub \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET // reserved_pg_dir msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 add \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/= mmu_context.h index 0dbe3b29049b..59f8b9b40184 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -218,7 +218,7 @@ static inline void update_saved_ttbr0(struct task_struc= t *tsk, if (mm =3D=3D &init_mm) ttbr =3D phys_to_ttbr(__pa_symbol(reserved_pg_dir)); else - ttbr =3D phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; + ttbr =3D phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << TTBRx_EL1_ASI= D_SHIFT; =20 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); } diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uacc= ess.h index 1aa4ecb73429..52daf9c2ba42 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -62,7 +62,7 @@ static inline void __uaccess_ttbr0_disable(void) =20 local_irq_save(flags); ttbr =3D read_sysreg(ttbr1_el1); - ttbr &=3D ~TTBR_ASID_MASK; + ttbr &=3D ~TTBRx_EL1_ASID_MASK; /* reserved_pg_dir placed before swapper_pg_dir */ write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); /* Set reserved ASID */ @@ -85,8 +85,8 @@ static inline void __uaccess_ttbr0_enable(void) =20 /* Restore active ASID */ ttbr1 =3D read_sysreg(ttbr1_el1); - ttbr1 &=3D ~TTBR_ASID_MASK; /* safety measure */ - ttbr1 |=3D ttbr0 & TTBR_ASID_MASK; + ttbr1 &=3D ~TTBRx_EL1_ASID_MASK; /* safety measure */ + ttbr1 |=3D ttbr0 & TTBRx_EL1_ASID_MASK; write_sysreg(ttbr1, ttbr1_el1); =20 /* Restore user page table */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index f8018b5c1f9a..9e1bcc821a16 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -473,7 +473,7 @@ alternative_else_nop_endif */ SYM_CODE_START_LOCAL(__swpan_entry_el1) mrs x21, ttbr0_el1 - tst x21, #TTBR_ASID_MASK // Check for the reserved ASID + tst x21, #TTBRx_EL1_ASID_MASK // Check for the reserved ASID orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR b.eq 1f // TTBR0 access already disabled and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index b2ac06246327..718c495832d0 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -358,11 +358,11 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm= _struct *mm) =20 /* SW PAN needs a copy of the ASID in TTBR0 for entry */ if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN)) - ttbr0 |=3D FIELD_PREP(TTBR_ASID_MASK, asid); + ttbr0 |=3D FIELD_PREP(TTBRx_EL1_ASID_MASK, asid); =20 /* Set ASID in TTBR1 since TCR.A1 is set */ - ttbr1 &=3D ~TTBR_ASID_MASK; - ttbr1 |=3D FIELD_PREP(TTBR_ASID_MASK, asid); + ttbr1 &=3D ~TTBRx_EL1_ASID_MASK; + ttbr1 |=3D FIELD_PREP(TTBRx_EL1_ASID_MASK, asid); =20 cpu_set_reserved_ttbr0_nosync(); write_sysreg(ttbr1, ttbr1_el1); --=20 2.30.2