From nobody Sun Feb 8 11:06:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BDD2B28DB3 for ; Mon, 3 Nov 2025 05:26:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147591; cv=none; b=aWWkDwOu0T9pvappKy/BfWOhb7VQftsV72LrsBFXb2Dgrzr6N/ELljcd9mo/9+8N+IK125P0qSTRsh2T1kSgetRdAX/BjUVXoBDe0v/mANRQKrwUEYNOJ9sDY+ZLNseH0lO3R21qXfD+rLZ7ovIRm1hmg4dL0ASCUfcY1KQ1gdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147591; c=relaxed/simple; bh=+8B9nK2NwQ4tZJu3O02bdjaoACAiFxg47VSJaGzF8IU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XHg34NmKX+gHfEcFzWu3obPiQzC//XbKWTcrokjIhN1GJKL5U3NJm5XqfDhphHtyf+VUruy7EB8z+l53D0xiLrGHFMkDr7DUuy00LbRbMRUf0cXbaEpqFe3zD4D0Mqe39vaMEmvbZ7EW/lJG/N6n83kwXOVuifwxZKHPB/9U4us= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F02E7292B; Sun, 2 Nov 2025 21:26:19 -0800 (PST) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6E7403F63F; Sun, 2 Nov 2025 21:26:26 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 1/6] arm64/mm: Directly use TTBRx_EL1_ASID_MASK Date: Mon, 3 Nov 2025 05:26:13 +0000 Message-Id: <20251103052618.586763-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251103052618.586763-1-anshuman.khandual@arm.com> References: <20251103052618.586763-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace all TTBR_ASID_MASK macro instances with TTBRx_EL1_ASID_MASK which is a standard field mask from tools sysreg format. No functional change. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/asm-uaccess.h | 2 +- arch/arm64/include/asm/mmu_context.h | 2 +- arch/arm64/include/asm/uaccess.h | 6 +++--- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/context.c | 6 +++--- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/= asm-uaccess.h index 9148f5a31968..12aa6a283249 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -15,7 +15,7 @@ #ifdef CONFIG_ARM64_SW_TTBR0_PAN .macro __uaccess_ttbr0_disable, tmp1 mrs \tmp1, ttbr1_el1 // swapper_pg_dir - bic \tmp1, \tmp1, #TTBR_ASID_MASK + bic \tmp1, \tmp1, #TTBRx_EL1_ASID_MASK sub \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET // reserved_pg_dir msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 add \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/= mmu_context.h index 0dbe3b29049b..59f8b9b40184 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -218,7 +218,7 @@ static inline void update_saved_ttbr0(struct task_struc= t *tsk, if (mm =3D=3D &init_mm) ttbr =3D phys_to_ttbr(__pa_symbol(reserved_pg_dir)); else - ttbr =3D phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; + ttbr =3D phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << TTBRx_EL1_ASI= D_SHIFT; =20 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); } diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uacc= ess.h index 1aa4ecb73429..52daf9c2ba42 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -62,7 +62,7 @@ static inline void __uaccess_ttbr0_disable(void) =20 local_irq_save(flags); ttbr =3D read_sysreg(ttbr1_el1); - ttbr &=3D ~TTBR_ASID_MASK; + ttbr &=3D ~TTBRx_EL1_ASID_MASK; /* reserved_pg_dir placed before swapper_pg_dir */ write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); /* Set reserved ASID */ @@ -85,8 +85,8 @@ static inline void __uaccess_ttbr0_enable(void) =20 /* Restore active ASID */ ttbr1 =3D read_sysreg(ttbr1_el1); - ttbr1 &=3D ~TTBR_ASID_MASK; /* safety measure */ - ttbr1 |=3D ttbr0 & TTBR_ASID_MASK; + ttbr1 &=3D ~TTBRx_EL1_ASID_MASK; /* safety measure */ + ttbr1 |=3D ttbr0 & TTBRx_EL1_ASID_MASK; write_sysreg(ttbr1, ttbr1_el1); =20 /* Restore user page table */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index f8018b5c1f9a..9e1bcc821a16 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -473,7 +473,7 @@ alternative_else_nop_endif */ SYM_CODE_START_LOCAL(__swpan_entry_el1) mrs x21, ttbr0_el1 - tst x21, #TTBR_ASID_MASK // Check for the reserved ASID + tst x21, #TTBRx_EL1_ASID_MASK // Check for the reserved ASID orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR b.eq 1f // TTBR0 access already disabled and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index b2ac06246327..718c495832d0 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -358,11 +358,11 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm= _struct *mm) =20 /* SW PAN needs a copy of the ASID in TTBR0 for entry */ if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN)) - ttbr0 |=3D FIELD_PREP(TTBR_ASID_MASK, asid); + ttbr0 |=3D FIELD_PREP(TTBRx_EL1_ASID_MASK, asid); =20 /* Set ASID in TTBR1 since TCR.A1 is set */ - ttbr1 &=3D ~TTBR_ASID_MASK; - ttbr1 |=3D FIELD_PREP(TTBR_ASID_MASK, asid); + ttbr1 &=3D ~TTBRx_EL1_ASID_MASK; + ttbr1 |=3D FIELD_PREP(TTBRx_EL1_ASID_MASK, asid); =20 cpu_set_reserved_ttbr0_nosync(); write_sysreg(ttbr1, ttbr1_el1); --=20 2.30.2 From nobody Sun Feb 8 11:06:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1C587241695 for ; Mon, 3 Nov 2025 05:26:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147591; cv=none; b=YdhOXddy+x0G+y35KlLs2Bmmji/dOm/D4IzpQiNaH2M6eIg5ceBkSZmemhEiQrAA15Qc5n60DzthxPegkuqWIEaMeJ6R8eTtc1Rtj1PlJSlcQUt8M4yuP3krK3NSnw2DjMG28c4gsCzLbnYD2P6cjRnXNkH0WKA0wQbZVk+/mTY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147591; 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Sun, 2 Nov 2025 21:26:27 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 2/6] arm64/mm: Directly use TTBRx_EL1_CnP Date: Mon, 3 Nov 2025 05:26:14 +0000 Message-Id: <20251103052618.586763-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251103052618.586763-1-anshuman.khandual@arm.com> References: <20251103052618.586763-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace all TTBR_CNP_BIT macro instances with TTBRx_EL1_CNP_BIT which is a standard field from tools sysreg format. No functional change. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/kernel/mte.c | 4 ++-- arch/arm64/mm/context.c | 2 +- arch/arm64/mm/mmu.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 43f7a2f39403..ba2e3e9d1f73 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -315,8 +315,8 @@ void mte_cpu_setup(void) * CnP is not a boot feature so MTE gets enabled before CnP, but let's * make sure that is the case. */ - BUG_ON(read_sysreg(ttbr0_el1) & TTBR_CNP_BIT); - BUG_ON(read_sysreg(ttbr1_el1) & TTBR_CNP_BIT); + BUG_ON(read_sysreg(ttbr0_el1) & TTBRx_EL1_CnP); + BUG_ON(read_sysreg(ttbr1_el1) & TTBRx_EL1_CnP); =20 /* Normal Tagged memory type at the corresponding MAIR index */ sysreg_clear_set(mair_el1, diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 718c495832d0..0f4a28b87469 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -354,7 +354,7 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_s= truct *mm) =20 /* Skip CNP for the reserved ASID */ if (system_supports_cnp() && asid) - ttbr0 |=3D TTBR_CNP_BIT; + ttbr0 |=3D TTBRx_EL1_CnP; =20 /* SW PAN needs a copy of the ASID in TTBR0 for entry */ if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN)) diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index b8d37eb037fc..e80bb623ef53 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -2084,7 +2084,7 @@ void __cpu_replace_ttbr1(pgd_t *pgdp, bool cnp) phys_addr_t ttbr1 =3D phys_to_ttbr(virt_to_phys(pgdp)); =20 if (cnp) - ttbr1 |=3D TTBR_CNP_BIT; + ttbr1 |=3D TTBRx_EL1_CnP; =20 replace_phys =3D (void *)__pa_symbol(idmap_cpu_replace_ttbr1); =20 --=20 2.30.2 From nobody Sun Feb 8 11:06:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C1CFA72614 for ; Mon, 3 Nov 2025 05:26:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147594; cv=none; b=YYTdZVJdX0R5Zl3c4IqQ0R8VZG2+WhlEe0IR5SnkhRYeNYfbdSj0rBxD58Ld+U9vVUHwv1KCamm/rcusTIXvDM69qx9o+B3QXGiCA8WIxGaaIsXqkVLaZk6zhauqTk4IrVm7Kdg0y+T3zCygWnqyDk2sHoLu2MlPJ08P+Us+3oQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147594; c=relaxed/simple; bh=NsA6MstwVKVb6qAUKC43Hsur9WtUnv6BWJyTcFCB9aM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QEqWu3XJp9DiVNeJg3+jlmGmcK9Z3qnrDihqIMd8royTb7zQuBxdysveb420hUz44CeJL0WwmH7bCU9NTNgBiqzcEaAjEDGhAGMGR1zr2qdGNW8w5SDNTSTzoC5HZ4VAtk1A5/AynLNu3B1c/PVQy+vhNknUdIypHS5n+YPFbKE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 626E42938; Sun, 2 Nov 2025 21:26:23 -0800 (PST) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CACD53F63F; Sun, 2 Nov 2025 21:26:29 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 3/6] arm64/mm: Represent TTBR_BADDR_MASK_52 with TTBRx_EL1_BADDR_MASK Date: Mon, 3 Nov 2025 05:26:15 +0000 Message-Id: <20251103052618.586763-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251103052618.586763-1-anshuman.khandual@arm.com> References: <20251103052618.586763-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TTBR_BADDR_MASK_52 discards bit[1] which is RES0, when TTBRx_EL1 register contains 52 bits PA. Let's just keep the custom macro but redefine it via tools sysreg register field format TTBRx_EL1_BADDR_MASK. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/pgtable-hwdef.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/as= m/pgtable-hwdef.h index f3b77deedfa2..e192c4dc624b 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -332,7 +332,7 @@ /* * TTBR_ELx[1] is RES0 in this configuration. */ -#define TTBR_BADDR_MASK_52 GENMASK_ULL(47, 2) +#define TTBR_BADDR_MASK_52 (TTBRx_EL1_BADDR_MASK & ~GENMASK(1, 1)) #endif =20 #ifdef CONFIG_ARM64_VA_BITS_52 --=20 2.30.2 From nobody Sun Feb 8 11:06:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7C0BB241695 for ; Mon, 3 Nov 2025 05:26:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147594; cv=none; b=TFmtqWK+5ERwVoAyI/xLtdWxdbEJMO95taM3TqM0NIqeT2xJwkCOiDiNB34NkasiuIb+/SG2ibV2GJu+M9Mjt6OmRgBzR92lODAVAkKeAGynuAVY1sOvIL0ylHSJlBnDYFEJZgBXqUUTWxn7R92cTTxULTxDevsYaAxKuWl246Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147594; c=relaxed/simple; bh=OzfK6dEVcshY/zkzH05K6gZlKS8WuKVkwI+Kb/zEX4M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lzivWJ/S04NpvuHeGla2ZebY+TtPxze0YMymTlQ36zIJ8tv2qRB4cKN3e18ReRaAIY2/qs5rHLV+bXyPbtM0yhs1OBQeyaBBxAr2fcPqbAl/7sl/65Wh47kdd8JmZztf0g4iPMFVHuOaZazvE9kURqdp4jIs8Zlw0NcsrmRVcxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E2C328FA; Sun, 2 Nov 2025 21:26:25 -0800 (PST) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 891F23F63F; Sun, 2 Nov 2025 21:26:31 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 4/6] arm64/mm: Ensure correct 48 bit PA gets into TTBRx_EL1 Date: Mon, 3 Nov 2025 05:26:16 +0000 Message-Id: <20251103052618.586763-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251103052618.586763-1-anshuman.khandual@arm.com> References: <20251103052618.586763-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Even though 48 bit PA representation in TTBRx_EL1 does not involve shifting partial bits like 52 bit variant does, they sill need to be masked properly for correctness. Hence mask 48 bit PA with TTBRx_EL1_BADDR_MASK. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/assembler.h | 1 + arch/arm64/include/asm/pgtable.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index 23be85d93348..d5eb09fc5f8a 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -609,6 +609,7 @@ alternative_endif and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 #else mov \ttbr, \phys + and \ttbr, \ttbr, #TTBRx_EL1_BADDR_MASK #endif .endm =20 diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index 0944e296dd4a..c3110040c137 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -1604,7 +1604,7 @@ static inline void update_mmu_cache_range(struct vm_f= ault *vmf, #ifdef CONFIG_ARM64_PA_BITS_52 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) #else -#define phys_to_ttbr(addr) (addr) +#define phys_to_ttbr(addr) (addr & TTBRx_EL1_BADDR_MASK) #endif =20 /* --=20 2.30.2 From nobody Sun Feb 8 11:06:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D4C8328B4F0 for ; Mon, 3 Nov 2025 05:26:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147596; cv=none; b=G9ce0JKqGhgj1shhI2fTka6nn8Qk84M/Xs0Pb0FtWKe2RcsHJgr0nOVQ8f0Rflm9hSzlRgtC61i9aDaXFz35j4GdZ2+TVoJ0CeZAMERfmvcdBxZhSmCnDsaxdDO5McB3WOfLC5AziXZHUcXYCc2XuYDDg7X6SBPjiM+Z4Tf4lVo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147596; c=relaxed/simple; bh=aGvapYLXCuLH4VJFyaZvlpdc6h+prlxUfBzZN3jrGsE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=l+s20uSjzNc3gNbHwKJuB2pxDcOqPq1m6bafK2WgV8DGEwLVP8EkDWxh3YaiIsDsluSKUcJrn6FXhFUIswMsyU3qIhgMcLXMJ5dMR8yHtfkrcjFCwbbeJSY0dZFa03QIW6WUpq9eFDg6rHbBmYPqPBJi+pztynKjlRMaZwA8seE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF7E5292B; Sun, 2 Nov 2025 21:26:26 -0800 (PST) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 479CF3F63F; Sun, 2 Nov 2025 21:26:33 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 5/6] arm64/mm: Describe 52 PA folding into TTBRx_EL1 Date: Mon, 3 Nov 2025 05:26:17 +0000 Message-Id: <20251103052618.586763-6-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251103052618.586763-1-anshuman.khandual@arm.com> References: <20251103052618.586763-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A 52 bit physical address gets stored in TTBR_BADDR_MASK_52 in a folded manner. Shifting PA[51:0] right ward by '46' bits aligns PA[51:48] into TTBRx_EL1[5:2] which gets ORed for the final TTBRx_EL1 encoding. Define TTBR_BADDR_HIGH_52_PA_PIVOT which describes this inflection point where this right shift is done thus bringing some clarity to this 52 PA address folding process in TTBRx_EL1. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/assembler.h | 2 +- arch/arm64/include/asm/pgtable-hwdef.h | 14 ++++++++++++++ arch/arm64/include/asm/pgtable.h | 3 ++- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index d5eb09fc5f8a..731b29d0506c 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -605,7 +605,7 @@ alternative_endif */ .macro phys_to_ttbr, ttbr, phys #ifdef CONFIG_ARM64_PA_BITS_52 - orr \ttbr, \phys, \phys, lsr #46 + orr \ttbr, \phys, \phys, lsr #TTBR_BADDR_52_PA_PIVOT and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 #else mov \ttbr, \phys diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/as= m/pgtable-hwdef.h index e192c4dc624b..fb9f651375a9 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -333,6 +333,20 @@ * TTBR_ELx[1] is RES0 in this configuration. */ #define TTBR_BADDR_MASK_52 (TTBRx_EL1_BADDR_MASK & ~GENMASK(1, 1)) + +/* + * A 52 bit physical address gets stored in TTBR_BADDR_MASK_52 i.e + * GENMASK(47, 2) in a folded manner. Shifting PA[51:0] right ward + * by 46 bits aligns PA[51:48] into TTBRx_EL1[5:2] which gets ORed + * subsequently for the final TTBRx_EL1 encoding. + * + * 47 5 2 0 + * +----------------------------------------------+-----------+--+ + * | PA[47:X] | PA[51:48] | | + * +----------------------------------------------+-----------+--+ + * + */ +#define TTBR_BADDR_52_PA_PIVOT 46 #endif =20 #ifdef CONFIG_ARM64_VA_BITS_52 diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index c3110040c137..3457045c1045 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -1602,7 +1602,8 @@ static inline void update_mmu_cache_range(struct vm_f= ault *vmf, #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) =20 #ifdef CONFIG_ARM64_PA_BITS_52 -#define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) +#define phys_to_ttbr(addr) (((addr) | ((addr) >> TTBR_BADDR_52_PA_PIVOT)) = & \ + TTBR_BADDR_MASK_52) #else #define phys_to_ttbr(addr) (addr & TTBRx_EL1_BADDR_MASK) #endif --=20 2.30.2 From nobody Sun Feb 8 11:06:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8D17528D8CC for ; Mon, 3 Nov 2025 05:26:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147597; cv=none; b=sfQLOHo+j1TbFNTNeJac774bDCYBlEtkRTYpU8Pv5Is3RW8IJUdp7fLBR6lfpHQf3EMRDRV0ZxzFOFiPDTJhLqcPNtZhjZwna+cSG7dplhcYNmmbvvKSOMSrB7A2/cBGCLVHP76HNH6E6NZRhaL+sFJrP59y9SLr8IXj06OaEGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762147597; c=relaxed/simple; bh=Z/y6w325RCO5ce3AI9VlqvFaOO28YYFIcCVhqt1U7Vo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q0QfGPs5WkrROx8udRkw7G5f8yoGduwL2Uq48SdI1dXRiJqbSmvEv83jj9ELKUXvpRWSBIYVTpt1M+go9YV6sUsogcASqm07WI94dpDDp7J9v4yabKpYT6zD1gr1p2Ezdn10tLvmbv6lSmpKLq6qsfNphaQGcyhLRxDU5icREfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C7F228FA; Sun, 2 Nov 2025 21:26:28 -0800 (PST) Received: from ergosum.cambridge.arm.com (ergosum.cambridge.arm.com [10.1.196.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 037DA3F63F; Sun, 2 Nov 2025 21:26:34 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Ard Biesheuvel , linux-kernel@vger.kernel.org Subject: [PATCH 6/6] arm64/mm: Describe TTBR1_BADDR_4852_OFFSET Date: Mon, 3 Nov 2025 05:26:18 +0000 Message-Id: <20251103052618.586763-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20251103052618.586763-1-anshuman.khandual@arm.com> References: <20251103052618.586763-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TTBR1_BADDR_4852_OFFSET is a constant offset which gets added into kernel page table physical address for TTBR1_EL1 when kernel is build for 52 bit VA but found to be running on 48 bit VA capable system. Although there is no explanation on how the macro is computed. Describe TTBR1_BADDR_4852_OFFSET computation in detail via deriving from all required parameters involved thus improving clarity and readability. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/pgtable-hwdef.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/as= m/pgtable-hwdef.h index fb9f651375a9..e3d070fdae6a 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -350,9 +350,12 @@ #endif =20 #ifdef CONFIG_ARM64_VA_BITS_52 +#define PTRS_PER_PGD_52_VA (UL(1) << (52 - PGDIR_SHIFT)) +#define PTRS_PER_PGD_48_VA (UL(1) << (48 - PGDIR_SHIFT)) +#define PTRS_PER_PGD_EXTRA (PTRS_PER_PGD_52_VA - PTRS_PER_PGD_48_VA) + /* Must be at least 64-byte aligned to prevent corruption of the TTBR */ -#define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \ - (UL(1) << (48 - PGDIR_SHIFT))) * 8) +#define TTBR1_BADDR_4852_OFFSET (PTRS_PER_PGD_EXTRA << PTDESC_ORDER) #endif =20 #endif --=20 2.30.2