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Sun, 02 Nov 2025 12:27:35 -0800 (PST) From: Peter Griffin Date: Sun, 02 Nov 2025 20:27:17 +0000 Subject: [PATCH v3 4/4] clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251102-automatic-clocks-v3-4-ff10eafe61c8@linaro.org> References: <20251102-automatic-clocks-v3-0-ff10eafe61c8@linaro.org> In-Reply-To: <20251102-automatic-clocks-v3-0-ff10eafe61c8@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Enable auto clock mode, and define the additional fields which are used when this mode is enabled. /sys/kernel/debug/clk/clk_summary now reports approximately 308 running clocks and 298 disabled clocks. Prior to this commit 586 clocks were running and 17 disabled. Signed-off-by: Peter Griffin --- drivers/clk/samsung/clk-gs101.c | 56 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 70b26db9b95ad0b376d23f637c7683fbc8c8c600..68c5ed8f0fe1cac5169313b6ec7= 05f9eec44ff53 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include @@ -26,6 +27,10 @@ #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) =20 +#define GS101_GATE_DBG_OFFSET 0x4000 +#define GS101_DRCG_EN_OFFSET 0x104 +#define GS101_MEMCLK_OFFSET 0x108 + /* ---- CMU_TOP ----------------------------------------------------------= --- */ =20 /* Register Offset definitions for CMU_TOP (0x1e080000) */ @@ -1433,6 +1438,9 @@ static const struct samsung_cmu_info top_cmu_info __i= nitconst =3D { .nr_clk_ids =3D CLKS_NR_TOP, .clk_regs =3D cmu_top_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cmu_top_clk_regs), + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D CMU_CMU_TOP_CONTROLLER_OPTION, }; =20 static void __init gs101_cmu_top_init(struct device_node *np) @@ -1900,6 +1908,11 @@ static const struct samsung_gate_clock apm_gate_clks= [] __initconst =3D { CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_C= RITICAL, 0), }; =20 +static const unsigned long dcrg_memclk_sysreg[] __initconst =3D { + GS101_DRCG_EN_OFFSET, + GS101_MEMCLK_OFFSET, +}; + static const struct samsung_cmu_info apm_cmu_info __initconst =3D { .mux_clks =3D apm_mux_clks, .nr_mux_clks =3D ARRAY_SIZE(apm_mux_clks), @@ -1912,6 +1925,12 @@ static const struct samsung_cmu_info apm_cmu_info __= initconst =3D { .nr_clk_ids =3D CLKS_NR_APM, .clk_regs =3D apm_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(apm_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_HSI0 ---------------------------------------------------------= --- */ @@ -2375,7 +2394,14 @@ static const struct samsung_cmu_info hsi0_cmu_info _= _initconst =3D { .nr_clk_ids =3D CLKS_NR_HSI0, .clk_regs =3D hsi0_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(hsi0_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D HSI0_CMU_HSI0_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_HSI2 ---------------------------------------------------------= --- */ @@ -2863,7 +2889,14 @@ static const struct samsung_cmu_info hsi2_cmu_info _= _initconst =3D { .nr_clk_ids =3D CLKS_NR_HSI2, .clk_regs =3D cmu_hsi2_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cmu_hsi2_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D HSI2_CMU_HSI2_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_MISC ---------------------------------------------------------= --- */ @@ -3423,7 +3456,14 @@ static const struct samsung_cmu_info misc_cmu_info _= _initconst =3D { .nr_clk_ids =3D CLKS_NR_MISC, .clk_regs =3D misc_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(misc_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D MISC_CMU_MISC_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 static void __init gs101_cmu_misc_init(struct device_node *np) @@ -4010,6 +4050,10 @@ static const struct samsung_gate_clock peric0_gate_c= lks[] __initconst =3D { 21, 0, 0), }; =20 +static const unsigned long dcrg_sysreg[] __initconst =3D { + GS101_DRCG_EN_OFFSET, +}; + static const struct samsung_cmu_info peric0_cmu_info __initconst =3D { .mux_clks =3D peric0_mux_clks, .nr_mux_clks =3D ARRAY_SIZE(peric0_mux_clks), @@ -4020,7 +4064,13 @@ static const struct samsung_cmu_info peric0_cmu_info= __initconst =3D { .nr_clk_ids =3D CLKS_NR_PERIC0, .clk_regs =3D peric0_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(peric0_clk_regs), + .sysreg_clk_regs =3D dcrg_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D PERIC0_CMU_PERIC0_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, }; =20 /* ---- CMU_PERIC1 -------------------------------------------------------= --- */ @@ -4368,7 +4418,13 @@ static const struct samsung_cmu_info peric1_cmu_info= __initconst =3D { .nr_clk_ids =3D CLKS_NR_PERIC1, .clk_regs =3D peric1_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(peric1_clk_regs), + .sysreg_clk_regs =3D dcrg_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D PERIC1_CMU_PERIC1_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, }; =20 /* ---- platform_driver --------------------------------------------------= --- */ --=20 2.51.1.930.gacf6e81ea2-goog