From nobody Mon Dec 15 19:06:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ACDB2F7479; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931636; cv=none; b=nJrIvcRTmv3pWQNzCSEulAJwMB5IsDr9YipESArs6mK47brq9R6cKa3of09x+xm7RUTW2gam9Ty/v+B+9F6Unn66mBG8rjdVto7x4Hk08sQWgKvhX5DxTv8YPaGoQDztBG2mRwFNlsDG942VhfBn2VGI+BZMYUKX2vY/XUGlBbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931636; c=relaxed/simple; bh=p2mT5ghCrdyTCWnU0vH7XPeN9JbRC4F/94aiLq32Z9Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kNQaQoDQtkqHW1gIV626vv1cSUmBdOZUAWkSUcymhS99c7XkuXJY9EPmwOnjOlSCFNas/zDlhIrON5mAFC2xxb5AY9V9FVQk7glxMy2V3DjKW0n/kPdYxO/bDYSUzv2E8DObhRmGRoSUICb9rYZPZpTs0cc+qM2NwMtt9foUisk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a1q94A7e; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a1q94A7e" Received: by smtp.kernel.org (Postfix) with ESMTPS id F38D6C4CEFD; Fri, 31 Oct 2025 17:27:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761931636; bh=p2mT5ghCrdyTCWnU0vH7XPeN9JbRC4F/94aiLq32Z9Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=a1q94A7e1tB/Ndw3YaERBAvBBHnHmwpkQz1T/cx1sKJyueluvPzr5uULV30AELkko OYMfz/tmwhjXX1x9BsRr/mX7t3aGc/uLGNv3jmE5GJc76maQs8Nh357oRzeAsRoBbv 6eWDyr1snOYReKrsAI/wnr1DZqcBjRED15OZZWDTDhNp1BsYH9oVJc1oLQ49WsafGs Ydhm8lQrn/fF3SAUV0NUymlT3Knmvw4usVDIc7ZNMhi0uBbrc5Wy0uWhBIfFUcAnjt 0Sjk9gV9CX35hzLSeQ6mqq/PG6yrVpXg/F/6CWiAVT06WScPNE8VjGBryECA6RF0oP 3q2Gi5wfgIJGw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E39B9CCFA00; Fri, 31 Oct 2025 17:27:15 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Sat, 01 Nov 2025 01:27:07 +0800 Subject: [PATCH net-next v2 1/4] net: stmmac: socfpga: Agilex5 EMAC platform configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251101-agilex5_ext-v2-1-a6b51b4dca4d@altera.com> References: <20251101-agilex5_ext-v2-0-a6b51b4dca4d@altera.com> In-Reply-To: <20251101-agilex5_ext-v2-0-a6b51b4dca4d@altera.com> To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Steffen Trumtrar Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761931634; l=3455; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=vntBDZwpth1lYOT1gYNvvzXdYXYWr60f8HSNHxW366k=; b=HqeT8OjjuqcrdJzqlau3nGAQRSE7vEu6aZPenJXIQ6PQ2HX6N2GytKv8laI1uw9z9vSrrXAwf QLHNl52JUwxAY+CrHPyW+OGjd+sKn5ppyam5qhcFD+DdH1WPKYgc3eb X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga platforms which use dwmac1000 IP. Due to differences in platform configuration, Agilex5 requires a distinct setup. Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle platform-specific setup. This callback is invoked before stmmac_dvr_probe() to ensure the platform data is correctly configured. Also, implemented separate setup_plat_dat() callback for current socfpga platforms and Agilex5. Signed-off-by: Rohan G Thomas Reviewed-by: Maxime Chevallier Tested-by: Maxime Chevallier --- .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 30 ++++++++++++++++++= +--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 2ff5db6d41ca08a1652d57f3eb73923b9a9558bf..5666b01723643984f21b996e765= 3a36f4dc22e30 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -44,6 +44,7 @@ struct socfpga_dwmac; struct socfpga_dwmac_ops { int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv); + void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv); }; =20 struct socfpga_dwmac { @@ -441,6 +442,23 @@ static int socfpga_dwmac_init(struct platform_device *= pdev, void *bsp_priv) return dwmac->ops->set_phy_mode(dwmac); } =20 +static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac) +{ + struct plat_stmmacenet_data *plat_dat =3D dwmac->plat_dat; + + plat_dat->core_type =3D DWMAC_CORE_GMAC; + + /* Rx watchdog timer in dwmac is buggy in this hw */ + plat_dat->riwt_off =3D 1; +} + +static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac) +{ + struct plat_stmmacenet_data *plat_dat =3D dwmac->plat_dat; + + plat_dat->core_type =3D DWMAC_CORE_XGMAC; +} + static int socfpga_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; @@ -497,25 +515,31 @@ static int socfpga_dwmac_probe(struct platform_device= *pdev) plat_dat->pcs_init =3D socfpga_dwmac_pcs_init; plat_dat->pcs_exit =3D socfpga_dwmac_pcs_exit; plat_dat->select_pcs =3D socfpga_dwmac_select_pcs; - plat_dat->core_type =3D DWMAC_CORE_GMAC; =20 - plat_dat->riwt_off =3D 1; + ops->setup_plat_dat(dwmac); =20 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } =20 static const struct socfpga_dwmac_ops socfpga_gen5_ops =3D { .set_phy_mode =3D socfpga_gen5_set_phy_mode, + .setup_plat_dat =3D socfpga_gen5_setup_plat_dat, }; =20 static const struct socfpga_dwmac_ops socfpga_gen10_ops =3D { .set_phy_mode =3D socfpga_gen10_set_phy_mode, + .setup_plat_dat =3D socfpga_gen5_setup_plat_dat, +}; + +static const struct socfpga_dwmac_ops socfpga_agilex5_ops =3D { + .set_phy_mode =3D socfpga_gen10_set_phy_mode, + .setup_plat_dat =3D socfpga_agilex5_setup_plat_dat, }; =20 static const struct of_device_id socfpga_dwmac_match[] =3D { { .compatible =3D "altr,socfpga-stmmac", .data =3D &socfpga_gen5_ops }, { .compatible =3D "altr,socfpga-stmmac-a10-s10", .data =3D &socfpga_gen10= _ops }, - { .compatible =3D "altr,socfpga-stmmac-agilex5", .data =3D &socfpga_gen10= _ops }, + { .compatible =3D "altr,socfpga-stmmac-agilex5", .data =3D &socfpga_agile= x5_ops }, { } }; MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); --=20 2.43.7 From nobody Mon Dec 15 19:06:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AC642F6182; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931636; cv=none; b=C7qr4gcwvHcTzx/mHDBlLYLx/9kkgu9FBBpBASlkic968LZJZxAvgHBy/VJhm4fAyb93J5dj9ht+SwZcRpmqedfIZG80dof193Aj0WG0j2964vMxfmNC+6U9besDfFJrr5CyfX74m3XvNh9kcaWCxU8qTYt6vKRQOO1ym7mayp4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931636; c=relaxed/simple; bh=GYem28TIcz0PWGQwlrg2H0OZ4/ZTAm/l/zRLYIjV6ZM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qg2TjuMhyH1gVFktZr47o5TQOMAa17t739r1pxX8IEagmsdgKzKKDZFFpIwIXuV9/dZieVTSZS6r5drQEO23+ry1iqSGpg1EDenZIMVoUaH6jGzI+2vggS4vNqP935o7wmm8oNN1kPbLV7NUoAeNqqdFKE1Y+w4jaIHamDPnRcU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CXcS3Dd6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CXcS3Dd6" Received: by smtp.kernel.org (Postfix) with ESMTPS id 118FFC4CEF1; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761931636; bh=GYem28TIcz0PWGQwlrg2H0OZ4/ZTAm/l/zRLYIjV6ZM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CXcS3Dd6m4Hq4K2iZHXFSqje7Mp80IrdEFkrTAQmJtn2Kh4QaPCvzJPzaXlH7wR2J aSlkEj2GQTgRmQ7UjWqIJ39bdlGQZNbEWEmopNN3ewWkRYdkqIRup71wS07eoOIUb4 xBBVN9v7Ltku8GiNXGUKeRhCtaZJvWPcLCYAIm4VssjopEiLyvPgYtEPabfhZL52+n YrJ8d5Houvi9qT1CNyerui8Rb/kHgp9rkdLGe3IVcE/OXJ47L7+tskAIoyiysouyRd DfhJVGNhcpUm+Ka5xS6OirqVc912fNSHp1hlYrXuqHJWNjwpoHsecYfyZsVoUk9r8s oomv4DGDsCHtg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F377ECCF9F8; Fri, 31 Oct 2025 17:27:15 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Sat, 01 Nov 2025 01:27:08 +0800 Subject: [PATCH net-next v2 2/4] net: stmmac: socfpga: Enable TBS support for Agilex5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251101-agilex5_ext-v2-2-a6b51b4dca4d@altera.com> References: <20251101-agilex5_ext-v2-0-a6b51b4dca4d@altera.com> In-Reply-To: <20251101-agilex5_ext-v2-0-a6b51b4dca4d@altera.com> To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Steffen Trumtrar Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761931634; l=1214; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=Rehj3W/2337ILzEH6ON7+yaibhBp9L+MAU32vI9ki2k=; b=7dqHPuanqJE3mi6rIM7SP88BAecpYWdfi2p7QVL22kjPa9vppTpBken6O7JMOAiCZ33oy/ClL snYeN9ZAW/bCTmWX6ZQb9332UdAyyEZAuBZHgHjPjf8hM5qniPffkub X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Agilex5 supports Time-Based Scheduling(TBS) for Tx queue 6 and Tx queue 7. This commit enables TBS support for these queues. Signed-off-by: Rohan G Thomas --- drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 5666b01723643984f21b996e7653a36f4dc22e30..4f256f0ae05c15d28e4836d676e= 2f2c052540184 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -457,6 +457,19 @@ static void socfpga_agilex5_setup_plat_dat(struct socf= pga_dwmac *dwmac) struct plat_stmmacenet_data *plat_dat =3D dwmac->plat_dat; =20 plat_dat->core_type =3D DWMAC_CORE_XGMAC; + + /* Enable TBS */ + switch (plat_dat->tx_queues_to_use) { + case 8: + plat_dat->tx_queues_cfg[7].tbs_en =3D true; + fallthrough; + case 7: + plat_dat->tx_queues_cfg[6].tbs_en =3D true; + break; + default: + /* Tx Queues 0 - 5 doesn't support TBS on Agilex5 */ + break; + } } =20 static int socfpga_dwmac_probe(struct platform_device *pdev) --=20 2.43.7 From nobody Mon Dec 15 19:06:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ABCF2F3C34; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931636; cv=none; b=MzxqpKPoxTflSOEDyEYm3B+h9IZ6VepK2bcLzs9pV5yhntEb+J/upkkrWXkBgYjHxQwyfHceojpTK4ZIk0aC8ywdtinr6m+ZCefmsv1zBUSJ1vAXGmTWnxDyQfRi4HixKz7WHKp8APV6XesLVq0qKNLOUe5av8Z7wFkgVpsK1/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931636; c=relaxed/simple; bh=RohrhTza2xAFrs7CezlnV5dAmx3p2a4uuSdG6YJAqwg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WPDjVBo8v5AIY8iMr2TAnEWtvnZ5Btjsv5H6fiMavIwNlzALnhGLydKWxmeOjpceStUKj3vbdTwriF31XQvpR2mEOsK0mu4WJlU6/0Y42rCz+58mwGWkjsNDSsci2jeLBrcj33xQTaVFpMU0sQ7J5iOTi9OjU7KV1nAQGwO7vvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iPNWb7uO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iPNWb7uO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1A0CBC116B1; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761931636; bh=RohrhTza2xAFrs7CezlnV5dAmx3p2a4uuSdG6YJAqwg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iPNWb7uOYK0sALyAQtVjPwJ9HIZ5dFMoTNwxtSNLb29zOQjrDsGmMRkSIhNvEMxAs arowbfFq5CvvszJo21oTnP6fH820QucS3uoLS67GGrOTupOMMrT8ebih4IT+UhyAPK Af349P5DHeOyOCQ3rCpDYr2i/XX2cghA7b/P8kTmuxB54l0yfhM84VwJLb7Hf7oZLL VkGIGH6yHfPdrdiF9ELnKcsdAj7jTkulQzM3o6fqkrmC4ET9rth/tXlA3lZf5Yy0DR GLXh2FUaCKXBY4qZioXW1rk42WqRPBiZW/ODh1CAU5Fcy+gg8J1sQXRoPogsB5yFdd g+FundlZBu4fg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10BBECCFA05; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Sat, 01 Nov 2025 01:27:09 +0800 Subject: [PATCH net-next v2 3/4] net: stmmac: socfpga: Enable TSO for Agilex5 platform Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251101-agilex5_ext-v2-3-a6b51b4dca4d@altera.com> References: <20251101-agilex5_ext-v2-0-a6b51b4dca4d@altera.com> In-Reply-To: <20251101-agilex5_ext-v2-0-a6b51b4dca4d@altera.com> To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Steffen Trumtrar Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761931634; l=898; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=7La402FNfWCHW7j+XKQ6FKNGivUWIK2yY2YFq0PbKn8=; b=qyEa1i+Sp+Z+47IiaDkmTF96tqOrqVij/aA0ZAXBlDqEpiqC+S+bZIll82jlrFrbONdseYOmz Z6FCoaHOYBWAWe9ddUIaPglfUtbijCuJA8aDZ08S+aAri2TSvsmQwlt X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Agilex5 supports TCP Segmentation Offload(TSO). This commit enables TSO for Agilex5 socfpga platforms. Signed-off-by: Rohan G Thomas --- drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 4f256f0ae05c15d28e4836d676e2f2c052540184..1837346ca2d438018ae161a233f= 415fe0181c78d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -458,6 +458,9 @@ static void socfpga_agilex5_setup_plat_dat(struct socfp= ga_dwmac *dwmac) =20 plat_dat->core_type =3D DWMAC_CORE_XGMAC; =20 + /* Enable TSO */ + plat_dat->flags |=3D STMMAC_FLAG_TSO_EN; + /* Enable TBS */ switch (plat_dat->tx_queues_to_use) { case 8: --=20 2.43.7 From nobody Mon Dec 15 19:06:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7763A272E63; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931636; cv=none; b=G6q1DL6AE/Jzyr0wLVnH8tGze1ozjkS8B8We+m94+YYavoIfcwd95WoMpYLwtwI76W42txgvY0n5oBviieb2fMw2HKXCx43DCryWfJTncMgFRHskoR/45OSU6s32Zu0SG1lVJqwUB9RUGO+8LgHErgcTwKcC/AiCOi7UJ7bIoHM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931636; c=relaxed/simple; bh=5A/kLq8po/AIfsNGO6cLTZ+fIVCQT5AElgJFBCeehsg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O3OM0ZlkDyAVs8K4ShdWkeOfxo2Fj+YWXG4b/VbMfbEYNZRGCR2a7vpzRK6bom1oH6UavTT12pRRIsApVqlCulDLRZ79lut2Mpo+J6UvXzZvYQcs4T+A2MC6rJP6Ko1N8xL0Q0714yGq6gL3YVNFzAjXvF6EBKofMEiMS4MhO5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vyi6NX87; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vyi6NX87" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2BF65C116C6; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761931636; bh=5A/kLq8po/AIfsNGO6cLTZ+fIVCQT5AElgJFBCeehsg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Vyi6NX87iJN6ZbeYYAXbf63YVcp/ADMBFRvE1zXks28mK87vEUU6cQd/3z/uLcIHG aJbbmy+g7ZLdH0W7wm6sJgIEbMjNm0m1ZtC0KgxNjvylyPcC3rlZOza6J7Ay7uWH7l UwFV9D8XGq61zQ5vK55swVToo0gUX0ICWhykzmT4DBYnmnmlCVjSE97/EQl5KakL3U VAnwV/j4s5KgbTVAukt09NwqSpb4STcRGbTXtPm2B2mv/3gLOaqqjvm6PAsQcdXJui UsYz0Qw+KgDKyh8FFJCkXhoRAMAyz4uJg1Ss7zUERlImmPy/MMw/MGmyAtD3tLBshF kPpp6Alu9hn0A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22808CCFA03; Fri, 31 Oct 2025 17:27:16 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Sat, 01 Nov 2025 01:27:10 +0800 Subject: [PATCH net-next v2 4/4] net: stmmac: socfpga: Add hardware supported cross-timestamp Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251101-agilex5_ext-v2-4-a6b51b4dca4d@altera.com> References: <20251101-agilex5_ext-v2-0-a6b51b4dca4d@altera.com> In-Reply-To: <20251101-agilex5_ext-v2-0-a6b51b4dca4d@altera.com> To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Steffen Trumtrar Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761931634; l=7078; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=9EkvKknTEFMhFgiG4guzPV0b/EvK3DNx3dlBmCIhiac=; b=uOn4rWvTDMcdAQ1HyyZkaYCxtJBnVLAs8rfsa590bz7r8rgMCrSuY56YVXV7Ee82E4rG1yhuk 3ix7Ne28jO4Do5xeB7MLMu5HdpyewAFibr4FJBycKZ5nKY1qKwg/Dji X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Cross timestamping is supported on Agilex5 platform with Synchronized Multidrop Timestamp Gathering(SMTG) IP. The hardware cross-timestamp result is made available the applications through the ioctl call PTP_SYS_OFFSET_PRECISE, which inturn calls stmmac_getcrosststamp(). Device time is stored in the MAC Auxiliary register. The 64-bit System time (ARM_ARCH_COUNTER) is stored in SMTG IP. SMTG IP is an MDIO device with 0xC - 0xF MDIO register space holds 64-bit system time. This commit is similar to following commit for Intel platforms: Commit 341f67e424e5 ("net: stmmac: Add hardware supported cross-timestamp") Signed-off-by: Rohan G Thomas --- .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 120 +++++++++++++++++= ++++ drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 5 + 2 files changed, 125 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 1837346ca2d438018ae161a233f415fe0181c78d..49d651948e2bd41faeecaebb371= 21aef757a66a7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -15,8 +16,10 @@ #include #include =20 +#include "dwxgmac2.h" #include "stmmac.h" #include "stmmac_platform.h" +#include "stmmac_ptp.h" =20 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 @@ -41,6 +44,13 @@ #define SGMII_ADAPTER_ENABLE 0x0000 #define SGMII_ADAPTER_DISABLE 0x0001 =20 +#define SMTG_MDIO_ADDR 0x15 +#define SMTG_TSC_WORD0 0xC +#define SMTG_TSC_WORD1 0xD +#define SMTG_TSC_WORD2 0xE +#define SMTG_TSC_WORD3 0xF +#define SMTG_TSC_SHIFT 16 + struct socfpga_dwmac; struct socfpga_dwmac_ops { int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv); @@ -269,6 +279,112 @@ static int socfpga_set_phy_mode_common(int phymode, u= 32 *val) return 0; } =20 +static void get_smtgtime(struct mii_bus *mii, int smtg_addr, u64 *smtg_tim= e) +{ + u64 ns; + + ns =3D mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD3); + ns <<=3D SMTG_TSC_SHIFT; + ns |=3D mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD2); + ns <<=3D SMTG_TSC_SHIFT; + ns |=3D mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD1); + ns <<=3D SMTG_TSC_SHIFT; + ns |=3D mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD0); + + *smtg_time =3D ns; +} + +static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *s= ystem, + void *ctx) +{ + struct stmmac_priv *priv =3D (struct stmmac_priv *)ctx; + u32 num_snapshot, gpio_value, acr_value; + void __iomem *ptpaddr =3D priv->ptpaddr; + void __iomem *ioaddr =3D priv->hw->pcsr; + unsigned long flags; + u64 smtg_time =3D 0; + u64 ptp_time =3D 0; + int i, ret; + u32 v; + + /* Both internal crosstimestamping and external triggered event + * timestamping cannot be run concurrently. + */ + if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN) + return -EBUSY; + + mutex_lock(&priv->aux_ts_lock); + /* Enable Internal snapshot trigger */ + acr_value =3D readl(ptpaddr + PTP_ACR); + acr_value &=3D ~PTP_ACR_MASK; + switch (priv->plat->int_snapshot_num) { + case AUX_SNAPSHOT0: + acr_value |=3D PTP_ACR_ATSEN0; + break; + case AUX_SNAPSHOT1: + acr_value |=3D PTP_ACR_ATSEN1; + break; + case AUX_SNAPSHOT2: + acr_value |=3D PTP_ACR_ATSEN2; + break; + case AUX_SNAPSHOT3: + acr_value |=3D PTP_ACR_ATSEN3; + break; + default: + mutex_unlock(&priv->aux_ts_lock); + return -EINVAL; + } + writel(acr_value, ptpaddr + PTP_ACR); + + /* Clear FIFO */ + acr_value =3D readl(ptpaddr + PTP_ACR); + acr_value |=3D PTP_ACR_ATSFC; + writel(acr_value, ptpaddr + PTP_ACR); + /* Release the mutex */ + mutex_unlock(&priv->aux_ts_lock); + + /* Trigger Internal snapshot signal. Create a rising edge by just toggle + * the GPO0 to low and back to high. + */ + gpio_value =3D readl(ioaddr + XGMAC_GPIO_STATUS); + gpio_value &=3D ~XGMAC_GPIO_GPO0; + writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS); + gpio_value |=3D XGMAC_GPIO_GPO0; + writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS); + + /* Poll for time sync operation done */ + ret =3D readl_poll_timeout(priv->ioaddr + XGMAC_INT_STATUS, v, + (v & XGMAC_INT_TSIS), 100, 10000); + if (ret) { + netdev_err(priv->dev, "%s: Wait for time sync operation timeout\n", + __func__); + return ret; + } + + *system =3D (struct system_counterval_t) { + .cycles =3D 0, + .cs_id =3D CSID_ARM_ARCH_COUNTER, + .use_nsecs =3D false, + }; + + num_snapshot =3D (readl(ioaddr + XGMAC_TIMESTAMP_STATUS) & + XGMAC_TIMESTAMP_ATSNS_MASK) >> + XGMAC_TIMESTAMP_ATSNS_SHIFT; + + /* Repeat until the timestamps are from the FIFO last segment */ + for (i =3D 0; i < num_snapshot; i++) { + read_lock_irqsave(&priv->ptp_lock, flags); + stmmac_get_ptptime(priv, ptpaddr, &ptp_time); + *device =3D ns_to_ktime(ptp_time); + read_unlock_irqrestore(&priv->ptp_lock, flags); + } + + get_smtgtime(priv->mii, SMTG_MDIO_ADDR, &smtg_time); + system->cycles =3D smtg_time; + + return 0; +} + static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac) { struct regmap *sys_mgr_base_addr =3D dwmac->sys_mgr_base_addr; @@ -473,6 +589,10 @@ static void socfpga_agilex5_setup_plat_dat(struct socf= pga_dwmac *dwmac) /* Tx Queues 0 - 5 doesn't support TBS on Agilex5 */ break; } + + /* Hw supported cross-timestamp */ + plat_dat->int_snapshot_num =3D AUX_SNAPSHOT0; + plat_dat->crosststamp =3D smtg_crosststamp; } =20 static int socfpga_dwmac_probe(struct platform_device *pdev) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index 0d408ee17f337851502cbcba8e82d2b839b9db02..e48cfa05000c07ed9194de786ef= a530a61a9dbfa 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -79,6 +79,7 @@ #define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8) #define XGMAC_PSRQ_SHIFT(x) ((x) * 8) #define XGMAC_INT_STATUS 0x000000b0 +#define XGMAC_INT_TSIS BIT(12) #define XGMAC_LPIIS BIT(5) #define XGMAC_PMTIS BIT(4) #define XGMAC_INT_EN 0x000000b4 @@ -173,6 +174,8 @@ #define XGMAC_MDIO_ADDR 0x00000200 #define XGMAC_MDIO_DATA 0x00000204 #define XGMAC_MDIO_C22P 0x00000220 +#define XGMAC_GPIO_STATUS 0x0000027c +#define XGMAC_GPIO_GPO0 BIT(16) #define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8) #define XGMAC_ADDR_MAX 32 #define XGMAC_AE BIT(31) @@ -220,6 +223,8 @@ #define XGMAC_OB BIT(0) #define XGMAC_RSS_DATA 0x00000c8c #define XGMAC_TIMESTAMP_STATUS 0x00000d20 +#define XGMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25) +#define XGMAC_TIMESTAMP_ATSNS_SHIFT 25 #define XGMAC_TXTSC BIT(15) #define XGMAC_TXTIMESTAMP_NSEC 0x00000d30 #define XGMAC_TXTSSTSLO GENMASK(30, 0) --=20 2.43.7