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[46.135.14.82]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4773c53eafbsm6728865e9.12.2025.10.31.10.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 10:42:32 -0700 (PDT) From: Mateusz Guzik To: torvalds@linux-foundation.org Cc: brauner@kernel.org, viro@zeniv.linux.org.uk, jack@suse.cz, linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, tglx@linutronix.de, pfalcato@suse.de, Mateusz Guzik Subject: [PATCH 1/3] x86: fix access_ok() and valid_user_address() using wrong USER_PTR_MAX in modules Date: Fri, 31 Oct 2025 18:42:18 +0100 Message-ID: <20251031174220.43458-2-mjguzik@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251031174220.43458-1-mjguzik@gmail.com> References: <20251031174220.43458-1-mjguzik@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" [real commit message will land here later] --- arch/x86/include/asm/uaccess_64.h | 17 +++++++++-------- arch/x86/kernel/cpu/common.c | 8 +++++--- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uacce= ss_64.h index c8a5ae35c871..f60c0ed147c3 100644 --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h @@ -12,13 +12,14 @@ #include #include #include -#include =20 -/* - * Virtual variable: there's no actual backing store for this, - * it can purely be used as 'runtime_const_ptr(USER_PTR_MAX)' - */ -extern unsigned long USER_PTR_MAX; +extern unsigned long user_ptr_max; +#ifdef MODULE +#define __user_ptr_max_accessor user_ptr_max +#else +#include +#define __user_ptr_max_accessor runtime_const_ptr(user_ptr_max) +#endif =20 #ifdef CONFIG_ADDRESS_MASKING /* @@ -54,7 +55,7 @@ static inline unsigned long __untagged_addr_remote(struct= mm_struct *mm, #endif =20 #define valid_user_address(x) \ - likely((__force unsigned long)(x) <=3D runtime_const_ptr(USER_PTR_MAX)) + likely((__force unsigned long)(x) <=3D __user_ptr_max_accessor) =20 /* * Masking the user address is an alternative to a conditional @@ -67,7 +68,7 @@ static inline void __user *mask_user_address(const void _= _user *ptr) asm("cmp %1,%0\n\t" "cmova %1,%0" :"=3Dr" (ret) - :"r" (runtime_const_ptr(USER_PTR_MAX)), + :"r" (__user_ptr_max_accessor), "0" (ptr)); return ret; } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3ff9682d8bc4..f338f5e9adfc 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -78,6 +78,9 @@ DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); EXPORT_PER_CPU_SYMBOL(cpu_info); =20 +unsigned long user_ptr_max __ro_after_init; +EXPORT_SYMBOL(user_ptr_max); + u32 elf_hwcap2 __read_mostly; =20 /* Number of siblings per CPU package */ @@ -2575,14 +2578,13 @@ void __init arch_cpu_finalize_init(void) alternative_instructions(); =20 if (IS_ENABLED(CONFIG_X86_64)) { - unsigned long USER_PTR_MAX =3D TASK_SIZE_MAX; - + user_ptr_max =3D TASK_SIZE_MAX; /* * Enable this when LAM is gated on LASS support if (cpu_feature_enabled(X86_FEATURE_LAM)) USER_PTR_MAX =3D (1ul << 63) - PAGE_SIZE; */ - runtime_const_init(ptr, USER_PTR_MAX); + runtime_const_init(ptr, user_ptr_max); =20 /* * Make sure the first 2MB area is not mapped by huge pages --=20 2.34.1 From nobody Sat Feb 7 21:24:41 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 465CA302151 for ; Fri, 31 Oct 2025 17:42:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[46.135.14.82]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4773c53eafbsm6728865e9.12.2025.10.31.10.42.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 10:42:35 -0700 (PDT) From: Mateusz Guzik To: torvalds@linux-foundation.org Cc: brauner@kernel.org, viro@zeniv.linux.org.uk, jack@suse.cz, linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, tglx@linutronix.de, pfalcato@suse.de, Mateusz Guzik Subject: [PATCH 2/3] runtime-const: split headers between accessors and fixup; disable for modules Date: Fri, 31 Oct 2025 18:42:19 +0100 Message-ID: <20251031174220.43458-3-mjguzik@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251031174220.43458-1-mjguzik@gmail.com> References: <20251031174220.43458-1-mjguzik@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" risv and x86 covered as a POC --- .../include/asm/runtime-const-accessors.h | 151 ++++++++++++++++++ arch/riscv/include/asm/runtime-const.h | 142 +--------------- .../x86/include/asm/runtime-const-accessors.h | 45 ++++++ arch/x86/include/asm/runtime-const.h | 38 +---- 4 files changed, 200 insertions(+), 176 deletions(-) create mode 100644 arch/riscv/include/asm/runtime-const-accessors.h create mode 100644 arch/x86/include/asm/runtime-const-accessors.h diff --git a/arch/riscv/include/asm/runtime-const-accessors.h b/arch/riscv/= include/asm/runtime-const-accessors.h new file mode 100644 index 000000000000..5b8e0349ee0d --- /dev/null +++ b/arch/riscv/include/asm/runtime-const-accessors.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_RUNTIME_CONST_ACCESSORS_H +#define _ASM_RISCV_RUNTIME_CONST_ACCESSORS_H + +#ifdef MODULE +#error "this functionality is not available for modules" +#endif + +#ifdef CONFIG_32BIT +#define runtime_const_ptr(sym) \ +({ \ + typeof(sym) __ret; \ + asm_inline(".option push\n\t" \ + ".option norvc\n\t" \ + "1:\t" \ + "lui %[__ret],0x89abd\n\t" \ + "addi %[__ret],%[__ret],-0x211\n\t" \ + ".option pop\n\t" \ + ".pushsection runtime_ptr_" #sym ",\"a\"\n\t" \ + ".long 1b - .\n\t" \ + ".popsection" \ + : [__ret] "=3Dr" (__ret)); \ + __ret; \ +}) +#else +/* + * Loading 64-bit constants into a register from immediates is a non-trivi= al + * task on riscv64. To get it somewhat performant, load 32 bits into two + * different registers and then combine the results. + * + * If the processor supports the Zbkb extension, we can combine the final + * "slli,slli,srli,add" into the single "pack" instruction. If the process= or + * doesn't support Zbkb but does support the Zbb extension, we can + * combine the final "slli,srli,add" into one instruction "add.uw". + */ +#define RISCV_RUNTIME_CONST_64_PREAMBLE \ + ".option push\n\t" \ + ".option norvc\n\t" \ + "1:\t" \ + "lui %[__ret],0x89abd\n\t" \ + "lui %[__tmp],0x1234\n\t" \ + "addiw %[__ret],%[__ret],-0x211\n\t" \ + "addiw %[__tmp],%[__tmp],0x567\n\t" \ + +#define RISCV_RUNTIME_CONST_64_BASE \ + "slli %[__tmp],%[__tmp],32\n\t" \ + "slli %[__ret],%[__ret],32\n\t" \ + "srli %[__ret],%[__ret],32\n\t" \ + "add %[__ret],%[__ret],%[__tmp]\n\t" \ + +#define RISCV_RUNTIME_CONST_64_ZBA \ + ".option push\n\t" \ + ".option arch,+zba\n\t" \ + ".option norvc\n\t" \ + "slli %[__tmp],%[__tmp],32\n\t" \ + "add.uw %[__ret],%[__ret],%[__tmp]\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + ".option pop\n\t" \ + +#define RISCV_RUNTIME_CONST_64_ZBKB \ + ".option push\n\t" \ + ".option arch,+zbkb\n\t" \ + ".option norvc\n\t" \ + "pack %[__ret],%[__ret],%[__tmp]\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + ".option pop\n\t" \ + +#define RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ + ".option pop\n\t" \ + ".pushsection runtime_ptr_" #sym ",\"a\"\n\t" \ + ".long 1b - .\n\t" \ + ".popsection" \ + +#if defined(CONFIG_RISCV_ISA_ZBA) && defined(CONFIG_TOOLCHAIN_HAS_ZBA) \ + && defined(CONFIG_RISCV_ISA_ZBKB) +#define runtime_const_ptr(sym) \ +({ \ + typeof(sym) __ret, __tmp; \ + asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \ + ALTERNATIVE_2( \ + RISCV_RUNTIME_CONST_64_BASE, \ + RISCV_RUNTIME_CONST_64_ZBA, \ + 0, RISCV_ISA_EXT_ZBA, 1, \ + RISCV_RUNTIME_CONST_64_ZBKB, \ + 0, RISCV_ISA_EXT_ZBKB, 1 \ + ) \ + RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ + : [__ret] "=3Dr" (__ret), [__tmp] "=3Dr" (__tmp)); \ + __ret; \ +}) +#elif defined(CONFIG_RISCV_ISA_ZBA) && defined(CONFIG_TOOLCHAIN_HAS_ZBA) +#define runtime_const_ptr(sym) \ +({ \ + typeof(sym) __ret, __tmp; \ + asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \ + ALTERNATIVE( \ + RISCV_RUNTIME_CONST_64_BASE, \ + RISCV_RUNTIME_CONST_64_ZBA, \ + 0, RISCV_ISA_EXT_ZBA, 1 \ + ) \ + RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ + : [__ret] "=3Dr" (__ret), [__tmp] "=3Dr" (__tmp)); \ + __ret; \ +}) +#elif defined(CONFIG_RISCV_ISA_ZBKB) +#define runtime_const_ptr(sym) \ +({ \ + typeof(sym) __ret, __tmp; \ + asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \ + ALTERNATIVE( \ + RISCV_RUNTIME_CONST_64_BASE, \ + RISCV_RUNTIME_CONST_64_ZBKB, \ + 0, RISCV_ISA_EXT_ZBKB, 1 \ + ) \ + RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ + : [__ret] "=3Dr" (__ret), [__tmp] "=3Dr" (__tmp)); \ + __ret; \ +}) +#else +#define runtime_const_ptr(sym) \ +({ \ + typeof(sym) __ret, __tmp; \ + asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \ + RISCV_RUNTIME_CONST_64_BASE \ + RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ + : [__ret] "=3Dr" (__ret), [__tmp] "=3Dr" (__tmp)); \ + __ret; \ +}) +#endif +#endif + +#define runtime_const_shift_right_32(val, sym) \ +({ \ + u32 __ret; \ + asm_inline(".option push\n\t" \ + ".option norvc\n\t" \ + "1:\t" \ + SRLI " %[__ret],%[__val],12\n\t" \ + ".option pop\n\t" \ + ".pushsection runtime_shift_" #sym ",\"a\"\n\t" \ + ".long 1b - .\n\t" \ + ".popsection" \ + : [__ret] "=3Dr" (__ret) \ + : [__val] "r" (val)); \ + __ret; \ +}) + +#endif /* _ASM_RISCV_RUNTIME_CONST_ACCESSORS_H */ diff --git a/arch/riscv/include/asm/runtime-const.h b/arch/riscv/include/as= m/runtime-const.h index d766e2b9e6df..14994be81487 100644 --- a/arch/riscv/include/asm/runtime-const.h +++ b/arch/riscv/include/asm/runtime-const.h @@ -11,147 +11,7 @@ =20 #include =20 -#ifdef CONFIG_32BIT -#define runtime_const_ptr(sym) \ -({ \ - typeof(sym) __ret; \ - asm_inline(".option push\n\t" \ - ".option norvc\n\t" \ - "1:\t" \ - "lui %[__ret],0x89abd\n\t" \ - "addi %[__ret],%[__ret],-0x211\n\t" \ - ".option pop\n\t" \ - ".pushsection runtime_ptr_" #sym ",\"a\"\n\t" \ - ".long 1b - .\n\t" \ - ".popsection" \ - : [__ret] "=3Dr" (__ret)); \ - __ret; \ -}) -#else -/* - * Loading 64-bit constants into a register from immediates is a non-trivi= al - * task on riscv64. To get it somewhat performant, load 32 bits into two - * different registers and then combine the results. - * - * If the processor supports the Zbkb extension, we can combine the final - * "slli,slli,srli,add" into the single "pack" instruction. If the process= or - * doesn't support Zbkb but does support the Zbb extension, we can - * combine the final "slli,srli,add" into one instruction "add.uw". - */ -#define RISCV_RUNTIME_CONST_64_PREAMBLE \ - ".option push\n\t" \ - ".option norvc\n\t" \ - "1:\t" \ - "lui %[__ret],0x89abd\n\t" \ - "lui %[__tmp],0x1234\n\t" \ - "addiw %[__ret],%[__ret],-0x211\n\t" \ - "addiw %[__tmp],%[__tmp],0x567\n\t" \ - -#define RISCV_RUNTIME_CONST_64_BASE \ - "slli %[__tmp],%[__tmp],32\n\t" \ - "slli %[__ret],%[__ret],32\n\t" \ - "srli %[__ret],%[__ret],32\n\t" \ - "add %[__ret],%[__ret],%[__tmp]\n\t" \ - -#define RISCV_RUNTIME_CONST_64_ZBA \ - ".option push\n\t" \ - ".option arch,+zba\n\t" \ - ".option norvc\n\t" \ - "slli %[__tmp],%[__tmp],32\n\t" \ - "add.uw %[__ret],%[__ret],%[__tmp]\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - ".option pop\n\t" \ - -#define RISCV_RUNTIME_CONST_64_ZBKB \ - ".option push\n\t" \ - ".option arch,+zbkb\n\t" \ - ".option norvc\n\t" \ - "pack %[__ret],%[__ret],%[__tmp]\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - ".option pop\n\t" \ - -#define RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ - ".option pop\n\t" \ - ".pushsection runtime_ptr_" #sym ",\"a\"\n\t" \ - ".long 1b - .\n\t" \ - ".popsection" \ - -#if defined(CONFIG_RISCV_ISA_ZBA) && defined(CONFIG_TOOLCHAIN_HAS_ZBA) \ - && defined(CONFIG_RISCV_ISA_ZBKB) -#define runtime_const_ptr(sym) \ -({ \ - typeof(sym) __ret, __tmp; \ - asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \ - ALTERNATIVE_2( \ - RISCV_RUNTIME_CONST_64_BASE, \ - RISCV_RUNTIME_CONST_64_ZBA, \ - 0, RISCV_ISA_EXT_ZBA, 1, \ - RISCV_RUNTIME_CONST_64_ZBKB, \ - 0, RISCV_ISA_EXT_ZBKB, 1 \ - ) \ - RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ - : [__ret] "=3Dr" (__ret), [__tmp] "=3Dr" (__tmp)); \ - __ret; \ -}) -#elif defined(CONFIG_RISCV_ISA_ZBA) && defined(CONFIG_TOOLCHAIN_HAS_ZBA) -#define runtime_const_ptr(sym) \ -({ \ - typeof(sym) __ret, __tmp; \ - asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \ - ALTERNATIVE( \ - RISCV_RUNTIME_CONST_64_BASE, \ - RISCV_RUNTIME_CONST_64_ZBA, \ - 0, RISCV_ISA_EXT_ZBA, 1 \ - ) \ - RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ - : [__ret] "=3Dr" (__ret), [__tmp] "=3Dr" (__tmp)); \ - __ret; \ -}) -#elif defined(CONFIG_RISCV_ISA_ZBKB) -#define runtime_const_ptr(sym) \ -({ \ - typeof(sym) __ret, __tmp; \ - asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \ - ALTERNATIVE( \ - RISCV_RUNTIME_CONST_64_BASE, \ - RISCV_RUNTIME_CONST_64_ZBKB, \ - 0, RISCV_ISA_EXT_ZBKB, 1 \ - ) \ - RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ - : [__ret] "=3Dr" (__ret), [__tmp] "=3Dr" (__tmp)); \ - __ret; \ -}) -#else -#define runtime_const_ptr(sym) \ -({ \ - typeof(sym) __ret, __tmp; \ - asm_inline(RISCV_RUNTIME_CONST_64_PREAMBLE \ - RISCV_RUNTIME_CONST_64_BASE \ - RISCV_RUNTIME_CONST_64_POSTAMBLE(sym) \ - : [__ret] "=3Dr" (__ret), [__tmp] "=3Dr" (__tmp)); \ - __ret; \ -}) -#endif -#endif - -#define runtime_const_shift_right_32(val, sym) \ -({ \ - u32 __ret; \ - asm_inline(".option push\n\t" \ - ".option norvc\n\t" \ - "1:\t" \ - SRLI " %[__ret],%[__val],12\n\t" \ - ".option pop\n\t" \ - ".pushsection runtime_shift_" #sym ",\"a\"\n\t" \ - ".long 1b - .\n\t" \ - ".popsection" \ - : [__ret] "=3Dr" (__ret) \ - : [__val] "r" (val)); \ - __ret; \ -}) +#include =20 #define runtime_const_init(type, sym) do { \ extern s32 __start_runtime_##type##_##sym[]; \ diff --git a/arch/x86/include/asm/runtime-const-accessors.h b/arch/x86/incl= ude/asm/runtime-const-accessors.h new file mode 100644 index 000000000000..4c411bc3cb32 --- /dev/null +++ b/arch/x86/include/asm/runtime-const-accessors.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RUNTIME_CONST_ACCESSORS_H +#define _ASM_RUNTIME_CONST_ACCESSORS_H + +#ifdef MODULE +#error "this functionality is not available for modules" +#endif + +#ifdef __ASSEMBLY__ + +.macro RUNTIME_CONST_PTR sym reg + movq $0x0123456789abcdef, %\reg + 1: + .pushsection runtime_ptr_\sym, "a" + .long 1b - 8 - . + .popsection +.endm + +#else /* __ASSEMBLY__ */ + +#define runtime_const_ptr(sym) ({ \ + typeof(sym) __ret; \ + asm_inline("mov %1,%0\n1:\n" \ + ".pushsection runtime_ptr_" #sym ",\"a\"\n\t" \ + ".long 1b - %c2 - .\n" \ + ".popsection" \ + :"=3Dr" (__ret) \ + :"i" ((unsigned long)0x0123456789abcdefull), \ + "i" (sizeof(long))); \ + __ret; }) + +// The 'typeof' will create at _least_ a 32-bit type, but +// will happily also take a bigger type and the 'shrl' will +// clear the upper bits +#define runtime_const_shift_right_32(val, sym) ({ \ + typeof(0u+(val)) __ret =3D (val); \ + asm_inline("shrl $12,%k0\n1:\n" \ + ".pushsection runtime_shift_" #sym ",\"a\"\n\t" \ + ".long 1b - 1 - .\n" \ + ".popsection" \ + :"+r" (__ret)); \ + __ret; }) + +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/x86/include/asm/runtime-const.h b/arch/x86/include/asm/ru= ntime-const.h index 8d983cfd06ea..15d67e2bfc96 100644 --- a/arch/x86/include/asm/runtime-const.h +++ b/arch/x86/include/asm/runtime-const.h @@ -2,41 +2,9 @@ #ifndef _ASM_RUNTIME_CONST_H #define _ASM_RUNTIME_CONST_H =20 -#ifdef __ASSEMBLY__ - -.macro RUNTIME_CONST_PTR sym reg - movq $0x0123456789abcdef, %\reg - 1: - .pushsection runtime_ptr_\sym, "a" - .long 1b - 8 - . - .popsection -.endm - -#else /* __ASSEMBLY__ */ - -#define runtime_const_ptr(sym) ({ \ - typeof(sym) __ret; \ - asm_inline("mov %1,%0\n1:\n" \ - ".pushsection runtime_ptr_" #sym ",\"a\"\n\t" \ - ".long 1b - %c2 - .\n" \ - ".popsection" \ - :"=3Dr" (__ret) \ - :"i" ((unsigned long)0x0123456789abcdefull), \ - "i" (sizeof(long))); \ - __ret; }) - -// The 'typeof' will create at _least_ a 32-bit type, but -// will happily also take a bigger type and the 'shrl' will -// clear the upper bits -#define runtime_const_shift_right_32(val, sym) ({ \ - typeof(0u+(val)) __ret =3D (val); \ - asm_inline("shrl $12,%k0\n1:\n" \ - ".pushsection runtime_shift_" #sym ",\"a\"\n\t" \ - ".long 1b - 1 - .\n" \ - ".popsection" \ - :"+r" (__ret)); \ - __ret; }) +#include =20 +#ifndef __ASSEMBLY__ #define runtime_const_init(type, sym) do { \ extern s32 __start_runtime_##type##_##sym[]; \ extern s32 __stop_runtime_##type##_##sym[]; \ @@ -70,5 +38,5 @@ static inline void runtime_const_fixup(void (*fn)(void *,= unsigned long), } } =20 -#endif /* __ASSEMBLY__ */ +#endif /* !__ASSEMBLY__ */ #endif --=20 2.34.1 From nobody Sat Feb 7 21:24:41 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6F83306D20 for ; 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[46.135.14.82]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4773c53eafbsm6728865e9.12.2025.10.31.10.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 10:42:38 -0700 (PDT) From: Mateusz Guzik To: torvalds@linux-foundation.org Cc: brauner@kernel.org, viro@zeniv.linux.org.uk, jack@suse.cz, linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, tglx@linutronix.de, pfalcato@suse.de, Mateusz Guzik Subject: [PATCH 3/3] fs: hide names_cachep behind runtime access machinery Date: Fri, 31 Oct 2025 18:42:20 +0100 Message-ID: <20251031174220.43458-4-mjguzik@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251031174220.43458-1-mjguzik@gmail.com> References: <20251031174220.43458-1-mjguzik@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The var is used twice for every path lookup, while the cache is initialized early and stays valid for the duration. Signed-off-by: Mateusz Guzik --- fs/dcache.c | 1 + include/asm-generic/vmlinux.lds.h | 3 ++- include/linux/fs.h | 17 +++++++++++++++-- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/fs/dcache.c b/fs/dcache.c index de3e4e9777ea..1afef6cf16b7 100644 --- a/fs/dcache.c +++ b/fs/dcache.c @@ -3259,6 +3259,7 @@ void __init vfs_caches_init(void) { names_cachep =3D kmem_cache_create_usercopy("names_cache", PATH_MAX, 0, SLAB_HWCACHE_ALIGN|SLAB_PANIC, 0, PATH_MAX, NULL); + runtime_const_init(ptr, names_cachep); =20 dcache_init(); inode_init(); diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinu= x.lds.h index dcdbd962abd6..c7d85c80111c 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -939,7 +939,8 @@ =20 #define RUNTIME_CONST_VARIABLES \ RUNTIME_CONST(shift, d_hash_shift) \ - RUNTIME_CONST(ptr, dentry_hashtable) + RUNTIME_CONST(ptr, dentry_hashtable) \ + RUNTIME_CONST(ptr, names_cachep) =20 /* Alignment must be consistent with (kunit_suite *) in include/kunit/test= .h */ #define KUNIT_TABLE() \ diff --git a/include/linux/fs.h b/include/linux/fs.h index 947d7958eb72..bf0606ace221 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -50,6 +50,10 @@ #include =20 #include +#ifndef MODULE +#include +#endif + #include =20 struct backing_dev_info; @@ -3044,8 +3048,17 @@ extern void __init vfs_caches_init(void); =20 extern struct kmem_cache *names_cachep; =20 -#define __getname() kmem_cache_alloc(names_cachep, GFP_KERNEL) -#define __putname(name) kmem_cache_free(names_cachep, (void *)(name)) +/* + * XXX The runtime_const machinery does not support modules at the moment. + */ +#ifdef MODULE +#define __names_cachep_accessor names_cachep +#else +#define __names_cachep_accessor runtime_const_ptr(names_cachep) +#endif + +#define __getname() kmem_cache_alloc(__names_cachep_accessor, GFP_KERNEL) +#define __putname(name) kmem_cache_free(__names_cachep_accessor, (void *)= (name)) =20 extern struct super_block *blockdev_superblock; static inline bool sb_is_blkdev_sb(struct super_block *sb) --=20 2.34.1