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Thu, 30 Oct 2025 23:30:05 -0700 From: Ashish Mhetre To: , , , , , , , , , CC: , , , , , , Ashish Mhetre Subject: [PATCH 3/3] arm64: dts: nvidia: Add nodes for CMDQV Date: Fri, 31 Oct 2025 06:29:59 +0000 Message-ID: <20251031062959.1521704-4-amhetre@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251031062959.1521704-1-amhetre@nvidia.com> References: <20251031062959.1521704-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34A:EE_|CH3PR12MB7716:EE_ X-MS-Office365-Filtering-Correlation-Id: 99cd8215-8bc4-4fee-c334-08de1846f75f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 06:30:20.8490 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99cd8215-8bc4-4fee-c334-08de1846f75f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7716 Content-Type: text/plain; charset="utf-8" The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add device tree nodes for the CMDQV hardware in the Tegra264 SoC device tree and enable them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU instance is paired with its corresponding CMDQV instance via the nvidia,cmdqv property. Signed-off-by: Ashish Mhetre --- .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 8 +++ arch/arm64/boot/dts/nvidia/tegra264.dtsi | 50 +++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra264-p3834.dtsi index 06795c82427a..375d122b92fa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -26,5 +26,13 @@ iommu@5000000 { iommu@6000000 { status =3D "okay"; }; + + cmdqv@5200000 { + status =3D "okay"; + }; + + cmdqv@6200000 { + status =3D "okay"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 872a69553e3c..609f6f5f7ef5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -212,6 +212,7 @@ smmu1: iommu@5000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv1>; }; =20 smmu2: iommu@6000000 { @@ -224,6 +225,25 @@ smmu2: iommu@6000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv2>; + }; + + cmdqv1: cmdqv@5200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0x5200000 0x0 0x830000>; + interrupts =3D ; + interrupt-names =3D "cmdqv"; + }; + + cmdqv2: cmdqv@6200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0x6200000 0x0 0x830000>; + interrupts =3D ; + interrupt-names =3D "cmdqv"; }; =20 mc: memory-controller@8020000 { @@ -288,6 +308,7 @@ smmu0: iommu@a000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv0>; }; =20 smmu4: iommu@b000000 { @@ -300,6 +321,25 @@ smmu4: iommu@b000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv4>; + }; + + cmdqv0: cmdqv@a200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0xa200000 0x0 0x830000>; + interrupts =3D ; + interrupt-names =3D "cmdqv"; + }; + + cmdqv4: cmdqv@b200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0xb200000 0x0 0x830000>; + interrupts =3D ; + interrupt-names =3D "cmdqv"; }; =20 i2c14: i2c@c410000 { @@ -541,6 +581,16 @@ smmu3: iommu@6000000 { =20 #iommu-cells =3D <1>; dma-coherent; + nvidia,cmdqv =3D <&cmdqv3>; + }; + + cmdqv3: cmdqv@6200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + status =3D "disabled"; + + reg =3D <0x00 0x6200000 0x0 0x830000>; + interrupts =3D ; + interrupt-names =3D "cmdqv"; }; }; =20 --=20 2.25.1